Datasheet L6561 Datasheet (ST)

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L6561

POWER FACTOR CORRECTOR

1 FEATURES

■ VERY PRECISE ADJUSTABLE OUTPUT

OVERVOLTAGE PROTECTION

■ MICRO POWER START-UP CURRENT (50µA

TYP.)

■ VERY LOW OPERATING SUPPLY

CURRENT(4mA TYP.)

■ INTERNAL START-UP TIMER

■ CURRENT SENSE FILTER ON CHIP

■ DISABLE FUNCTION

■ 1% PRECISION (@ T

= 25°C) INTERNAL

j

REFERENCE VOLTAGE

■ TRANSITION MODE OPERATION

■ TOTEM POLE OUTPUT CURRENT: ±400mA

■ DIP-8/SO-8 PACKAGES

2 DESCRIPTION

L6561 is the improv ed versi on of the L 6560 stan ­dard Power Factor Corrector. Fully compatible
with the standard version, it has a superior perfor­mant multiplier making the device capable of work­ing in wide input voltage range application s (from
85V to 265V) with an ex ce ll ent T HD. Fur th er more
the start up current has be en red uced at f ew tens
of mA and a disable function has been implement­ed on the ZCD pin, guaranteeing lower current
consumption in stand by mode.

gure 1. Packages

DIP-8

SO-8

Table 1. Order Codes

Part Number Package

L6561 DIP-8

L6561D SO-8

L6561D013TR Tape & Reel

Realised in mixed BCD technology, the chip gives
the following benefits:

– micro power start up current
– 1% precision internal reference voltage
– (Tj = 25°C)
– S oft Output Over Voltage Protection
– no need for external low pass filter on the cur-

rent sense

– v ery low operating quiescent current minimis-

es power dissipation
The totem pole ou tput stage is capable of driving
a Power MOS or IGBT with source and sink cur­rents of ±400mA. The device is ope rating in tran­sition mode and it is optimised for Electronic Lamp
Ballast application, AC-DC adaptors and SMPS.

Figure 2. Block Diagram

INV

V

June 2004

COMP MULT CS

1

VOLTAGE

REGULATOR

8

CC

20V

R1

R2

2.1V

1.6V

6

GND

INTERNAL

SUPPLY 7V

+

-

V

REF2

2.5V

5

ZCD

23 4

­+

OVER-VOLTAGE

DETECTION

UVLO

+

-

ZERO CURRENT

DETECTOR

DISABLE

MULTIPLIER

-

RSQ

+

STARTER

5pF

40K

DRIVER

D97IN547E

V

CC

7

GD

REV. 16

1/13

L6561

Table 2. Absolute Maximum Ratings

Symbol Pin Parameter Value Unit

I

Vcc

I

GD

INV , COMP

MULT

CS 4 Current Sense Input -0.3 to 7 V

ZCD 5 Zero Current Detector 50 (source)

P

tot

T

j

T

stg

Figure 3. Pin Connection (Top view)

8Iq + IZ; (IGD = 0) 30 mA
7 Output Totem Pole Peak Current (2µs) ±700 mA

1, 2, 3 Analog Inputs & Outputs -0.3 to 7 V

-10 (sink)

Power Dissipation @T

Junction Temperature Operating Range -40 to 150 °C
Storage Temperature -55 to 150 °C

= 50 °C (DIP-8)

amb

(SO-8)

1

0.65

mA
mA

W
W

INV

COMP

MULT

CS

1
2
3
4ZCD

DIP8

8
7
6
5

V

CC

GD
GND

Table 3. Thermal Data

Symbol Parameter SO 8 MINIDIP Unit

R

th j-amb

Thermal Resistance Junction to ambient 150 100 °C/W

Table 4. Pin Description

N. Name Function

1 INV Inverting input of the error amplifier. A resistive divider is connected between the output

2 COMP Output of error amplifier. A feedback compensation network is placed between this pin and the

3 MULT Input of the multiplier stage. A resistive divider connects to this pin the rectified mains. A voltage

4 CS Input to the comparator of the control loop. The curren t is sense d by a resisto r and the resulti ng

5 ZCD Zero current detection input. If it is connected to GND, the device is disabled.
6 GND Current return for driver and control circuits.
7 GD Gate driver output. A pu sh pul l ou tpu t st ag e is a ble to drive the Power MOS with peak current of

8V

(1) Parameter guaranteed by design, not tested in production.

regulated voltage and this point, to provide voltage feedback.

INV pin.

signal, proportional to the rectified mains, appears on this pin.

voltage is applied to this pin.

400mA (source and sink).
Supply voltage of driver and control circuits.

CC

2/13

L6561

Table 5. Electrical Characteristics

= 14.5V; T

(V

CC

Symbol Pin Parameter Test Condition Min. Typ. Max. Unit

SUPPLY VOLTAGE SECTION

V

V

CC ON

V

CC OFF

CC

8 Operating Range after turn-on 11 18 V
8 Turn-on Threshold 11 12 13 V
8 Turn-off Threshold 8.7 9.5 10.3 V

Hys 8 Hysteresis 2.2 2.5 2.8 V

SUPPLY CURRENT SECTION

I

START-U

I

q

I

CC

8 Start-up Current before turn-on (VCC =11V) 205090µA
8 Quiescent Current 2.6 4 mA
8 Operating Supply Current CL = 1nF @ 70KHz 4 5.5 mA

Iq 8 Quiescent Current V

8V

V

Z

8 Zener Voltage ICC = 25mA 18 20 22 V

ERROR AMPLIFIER SECTION

V

INV

I

INV

G

V

1 Voltage Feedback Input

1 Input Bias Current -0.1 -1 µA

GB Gain Bandwidth 1 MHz

I

COMP

V

COMP

2 Source Current V

2 Upper Clamp Voltage I

MULTIPLIER SECTION

V

MULT

VCS∆

-----------------

∆

V

mult

3 Linear Operating Voltage 0 to 3

KGain V

CURRENT SENSE COM PARATOR

V

I

CS

t

d (H-L)

CS

4 Current Sense Reference

4 Input Bias Current VOS = 0 -0.05 -1 µA
4 Delay to Output 200 450 ns
4 Current Sense Offset 0 15 mV

ZERO CURRENT DETECTOR

V

V
V

ZCD

ZCD
ZCD

5 Input Thre shold Voltage Rising

5 Upper Clamp Voltage I
5 Upper Clamp Voltage I

= -25°C to 125°C;unless otherwise specified)

amb

= 2.7V 1.4 2.1 mA

pin1

off

CC off

20 50 90 µA

1.4 2.1 mA

Threshold
Line Regulation V

in OVP condition V

≤150mV, VCC > VCC

PIN5

≤ 150mV, VCC < V

PIN5

T

= 25°C 2.465 2.5 2.535 V

amb

12V < V

CC

< 18V 2.44 2.56 V

CC

= 12 to 18V 2 5 mV

Voltage Gain Open loop 60 80 dB

Sink Current V

Lower Clamp Voltage I

= 4V, V

COMP

= 4V, V

COMP

= 0.5mA 5.8 V

SOURCE

= 0.5mA 2.25 V

Sink

= 2.4V -2 -4 -8 mA

INV

= 2.6V 2.5 4.5 mA

INV

0 to 3.5

Output Max. Slope V

Clamp

= from 0V to 0.5V

MULT

V

= Upper Clamp Voltage

COMP

= 1V V

MULT

V

= 2.5V

MULT

V

= Upper Clamp Voltage

COMP

= 4V 0.45 0.6 0.75 1/V

COMP

1.65 1.9

1.6 1.7 1.8 V

(1) 2.1 V

Edge
Hysteresis (1) 0.3 0.5 0.7 V

= 20µA4.55.15.9V

ZCD

= 3mA 4.7 5.2 6.1 V

ZCD

V

3/13

L6561

Table 5. Electrical Characteristics (continued)

= 14.5V; T

(V

CC

Symbol Pin Parameter Test Condition Min. Typ. Max. Unit

V

ZCD

I

ZCD

I

ZCD

I

ZCD

V

DIS

I

ZCD

OUTPUT SECTION

V

GD

t

r

t

f

I

GD off

OUTPUT OVERVOLTAGE SECTION

I

OVP

RESTART TIMER

t

START

5 Lower Clamp Voltage I
5 Sink Bias Current 1V ≤ V
5 Source Current Capability -3 -10 mA
5 Sink Current Capability 3 10 mA
5 Disable threshold 150 200 250 mV
5 Restar t Cu rre nt Aft er Dis able V

7 Dropout Voltage I

7 Output Voltage Rise Time CL = 1nF 40 100 ns
7 Output Voltage Fall Time CL = 1nF 40 100 ns
7 IGD Sink Current VCC =3.5V VGD = 1V 5 10 - mA

2 OVP Triggering Current 35 40 45 µA

= -25°C to 125°C;unless otherwise specified)

amb

= -3mA 0.3 0.65 1 V

ZCD

≤ 4.5V 2 µA

ZCD

< V

ZCD

GDsource

I

GDsource

I

GDsink

I

GDsink

Static OVP Threshold 2.1 2.25 2.4 V

Start Timer 70 150 400 µs

; VCC > V

dis

= 200mA 1.2 2 V

= 20mA 0.7 1 V
= 200mA 1.5 V
= 20mA 0.3 V

CCOFF

-100 -200 -300 µA

3 OVER VOLTAGE PROTECTION OVP

The output voltage is expected to be kept by the opera tion of the PFC circui t close to it s nomi nal value.
This is set by the r atio of the t wo exte rnal r esistors R1 and R2 (see fig . 5), tak ing i nto co nsider ation t hat
the non inverting input of the error amplifier is biased inside the L6561 at 2.5V.

In steady state conditions, the current through R1 and R2 is:

V

2.5–

out

I

R1sc

------------------------- - I
R1

and, if the external compensation network is made only with a capacitor C
equals zero.When the output voltage increases abruptly the current through R1 becomes:

V

I

R1

outsc

----------------------------------------------------- I

Since the current through R2 does not change, ∆I

V

2.5–∆+

out

R1

must flow through the capacitor C

R1

error amplifier.
This current is monitored inside the L6561 and when reaches about 37µA the output volt a ge of th e mu lti-

plier is forced to decrease, thu s redu ci ng th e ener g y drawn fro m the ma ins . If the curr ent exceed s 40µA,
the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off until the
current falls approximately below 10µA.

However, if the over voltage persists, an interna l comparator (Static OVP) confirms the OVP conditi on
keeping the external power swi tch turned off (see fig. 4).Finally, the overv oltage that triggers the OVP
function is:

∆V

= R1 · 40µA.

out

Typical values for R

, R2 and C are shown in the application circuits. The overvoltage can be set indepen-

1

R2

R1scIR1

2.5V

------------===

R2

∆+==

, the current through C

comp

comp

comp

and enter the

4/13

L6561

dently from the average output voltage. The precision in setting the overvoltage threshold is 7% of the ov­ervoltage value (for instance ∆V = 60V ± 4.2V).

3.1 Disable function

The zero current detector (ZCD) pin can be used for device disabling as well. By grounding the ZCD volt­age the device is disabled reducing the supply current consumption at 1.4mA typical (@ 14.5V supply volt­age).

Releasing the ZCD pin the internal start-up timer will restart the device.

Figure 4.

OVER VOLTAGE

V

OUT nominal

40µA
10µA

I

SC

E/A OUTPUT

2.25V

DYNAMIC OVP

STATIC OVP

Figure 5. Overvoltage Protection Circuit

Ccomp.

+Vo

R1

1

-

E/A

R2

D97IN591

+

2.5V

∆I

40µA

2.25V

D97IN592A

∆I

2

X PWM DRIVER

-

+

5/13

L6561

gap

g

Figure 6. Typical Application Circuit (80W, 110VAC)

C7

10nF

R2
100

C6

10nF

R1

8

3

FUSE 4A/250V

Vac

(85V to 135V)

NTC

(*) R3 = 2 x 120KΩ
R6 = 0.619Ω/2
R7 = 2 x 475KΩ, 1%
R9 = 2 x 475KΩ

BRIDGE

4 x 1N4007

+

-

R3 (*)

D3 1N4150

240K

R9 (*)

C1

950K

1µF

250V

R10
10K

TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7)
primary 90T of Litz wire 10 x 0.2mm
secondary 11T of #27 AWG (0.15mm)

1.8mm for a total primary inductance of 0.7mH

D2

1N5248B

C2

22µF

25V

Figure 7. Typical Application Circuit (120W, 220VAC)

C7

10nF

R2

100

C6

10nF

R1

8

3

FUSE 2A/250V

Vac

(175V to 265V)

NTC

(*) R3 = 2 x 220KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 909KΩ

BRIDGE

4 x 1N4007

+

-

R3 (*)

D3 1N4150

440K

C1

R9 (*)

560nF

1.82M

400V

R10
10K

TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
gap 1.25mm for a total primary inductance of 0.8mH

D2

1N5248B

C2

22µF

25V

68K

5

L6561

6

68K

5

L6561

6

T

C3 680nF

21

T

C3 1µF

21

7

4

7

4

D1 BYT03-400

R5 MOS

10

R5 MOS
10

R6 (*)

0.31
1W

R6 (*)

0.41

1W

STP7NA40

D97IN549B

D1 BYT13-600

R7 (*)
998K

STP5NA50

6.34K

D97IN550B

R7 (*)

950K

R8

10K

1%

R8

1%

+

Vo=240V

Po=80W

C5

100µF

315V

Vo=400V

Po=120W

C5
56µF
450V

-

+

-

Figure 8. Typical Application Circuit (80W, Wide-range Mains)

68K

5

L6561

6

T

C3 1µF

21

FUSE 4A/250V

Vac

(85V to 265V)

NTC

(*) R3 = 2 x 120KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 620KΩ

6/13

4 x 1N4007

+

-

C7

10nF

R2
100

C6

12nF

R1

8

3

R3 (*)

D3 1N4150

240K

BRIDGE

C1

R9 (*)

1µF

1.24M

400V

R10
10K

TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)

ap 1.25mm for a total primary inductance of 0.8mH

D2

1N5248B

C2

22µF

25V

7

4

D1 BYT13-600

R5 MOS

STP8NA50

10

R6 (*)

0.41
1W

D97IN553B

R7 (*)

998K

R8

6.34K
1%

+

Vo=400V

Po=80W

C5
47µF
450V

-

Figure 9. Demo Board (EVAL6561-80) Electrical Schematic

NTC

D1

MOS

R10

0.41

2.5

R11

750 k

R12

750 k

R13

9.53 k

1W

4A/250V

Vac

(85V to 265V)

FUSE

R4

180 k

R1

750 k

BRIDGE

C1

W04M

+

-

Boost Inductor Spec (ITAC OIL E2543/E)

1 µF

400V

R2

750 k

C2

10nF

R3

10 k

E25x13x 7 core, 3C85 ferrite

1.5 mm gap for 0.7 mH primary inductance
Primary: 105 turns 20x0.1 mm
Secondary: 11 turns 0.1mm

180 k

22 µF

R5

C29

25V

D8

1N4150

D2

1N5248B

C5 12 nF

C4

100 nF

R14

100

R6

68 k

5

8

3

6

D3 1N4148

C7

10 µF

35 V

T

R50 12 k

C3 470 nF

C23

1 µF

21

91 k

R16

7

4

R15

220

L6561

THD RE DUCER (optio n al)

STTH1L06

R7

33

STP8NM50

R9

0.41
1W

Figure 10. EVAL6561-80: PCB and Component Layout (Top view, real size 57x108mm)

Vo=400V

Po=80W

C6
47 µF
450V

L6561

-

Table 6. EVAL6561-80: Evaluation Results.

Vin (Vac)

Pin (W)

Vo (Vdc)

∆

Vo (Vdc)

Po (W) η (%)

85 87.2 400.1 14 80.7 92.8 0.999 3.7 0.999 2.9
110 85.2 400.1 14 80.7 94.7 0.996 5.0 0.996 3.2
135 84.2 400.1 14 80.7 95.8 0.989 6.2 0.989 3.7
175 83.5 400.1 14 80.7 96.6 0.976 8.3 0.976 4.3
220 83.1 400.1 14 80.7 97.1 0.940 10.7 0.941 5.6
265 82.9 400.1 14 80.7 97.3 0.890 13.7 0.893 8.1

w/o THD reducer with THD reducer

PF THD (%) PF THD (%)

7/13

L6561

)

(˚C)

Figure 11. OVP Current Threshold vs.

Temperature

I

OVP
(µA)

41

40

39

38

-50 -25 0 25 50 75 100 125T (˚C

D94IN047A

Figure 13. Supply Current vs. Supply

Voltage

I

CC

(mA)

10

5
1

0.5

0.1

0.05

0.01

0.005
0

0 5 10 15 20 VCC(V)

D97IN548A

CL = 1nF
f = 70KHz
TA = 25˚C

Figure 12. Undervoltage Lockout Threshold

vs. Temperature

V

CC-ON

(V)

V

CC-OFF

(V)

13

12

11

10

9

-25 0 25 50 75 100 125
T

D94IN044A

Figure 14. Voltage Feedback Input Threshold

vs. Temperature

V

REF

(V)

2.50

2.48

2.46

-50 0 50 100

D94IN048A

T (˚C)

8/13

L6561

Figure 15. Output Saturation Voltage vs. Sink

Current

V

PIN7
(V)

VCC = 14.5V

2.0

1.5

1.0

0.5

0

0 100 200 300 400 IGD (mA)

D94IN046

SINK

Figure 17. Multiplier Characteristics

Family

V

(pin4)

CS

upper voltage

(V)

clamp

1.6

1.4

1.2

5.0

4.5

4.0

1.0

0.8

0.6

0.4

0.2
0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

V

MULT

D97IN555A

(pin3) (V)

V

COMP

3.5

3.2

3.0

2.8

2.6

(pin2)

(V)

Figure 16. Output Saturation Voltage vs.

Source Current

V

PIN7

(V)

VCC = 14.5V

VCC -0.5

VCC -1.0

VCC -1.5

VCC -2.0

0

0 100 200 300 400 IGD (mA)

D94IN053

SOURCE

9/13

L6561

Figure 18. DIP-8 Mechanical Data & Package Dimensions

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150

Z 1.52 0.060

OUTLINE AND

MECHANICAL DATA

DIP-8

10/13

Figure 19. SO-8 Mechanical Data & Package Dimensions

L6561

DIM.

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

(1)

D

E 3.80 4.00 0.15 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

k 0˚ (min.), 8˚ (max.)

ddd 0.10 0.004

Note: (1) Dimensions D does not include mold flash, protru-

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

4.80 5.00 0.189 0.197

sions or gate burrs.
Mold flash , pot rus ions or ga t e burr s shall not exce ed

0.15mm (.006inch) in total (both side).

OUTLINE AND

MECHANICAL DATA

SO-8

0016023 C

11/13

L6561

Table 7. Revision History

Date Revision Description of Chan g es

January 2004 15 First Issue

June 2004 16 Modified the Style-look in compliance with the “Corporate Technical

Publications Design Gu ide ”.
Changed input of the power amplifier connected to Multiplier (Fig. 2).

12/13

L6561

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13/13