easySPIN – fully integrated microstepping motor driver
Features
■ Operating voltage: 8 - 45 V
■ 7.0 A output peak current (3.0 A r.m.s.)
■ Low R
■ Programmable power MOS slew-rate
■ Up to 1/16 microstepping
■ Current control with adaptive decay
■ Non dissipative current sensing
■ SPI interface
■ Low quiescent and standby currents
■ Programmable non dissipative overcurrent
protection on all power MOS
■ Two-level overtemperature protection
Application
■ Bipolar stepper motor
power MOSFETS
DSon
L6474
POWERSO36
an adaptive decay mode which outperforms
traditional implementations.
All data registers, including those used to set
analogue values (i.e. current control value,
current protection trip point, dead time, etc.) are
sent through a standard 5 Mbit/s SPI.
A very rich set of protections (thermal, low bus
voltage, overcurrent) makes the L6474 “bullet
proof” as required by the most demanding motor
control applications.
HTSSOP28
Description
The L6474, realized in analog mixed signal
technology, integrates a dual low R
full bridge with all power switches equipped with
an accurate on-chip current sensing circuitry
suitable for non dissipative current control and
overcurrent protections. Thanks to a new current
control, a 1/16 microstepping is achieved through
Table 1. Device summary
Order codes Package Packing
L6474H HTSSOP28 Tube
L6474HTR HTSSOP28 Tape and reel
L6474PD POWERSO36 Tube
L6474PDTR POWERSO36 Tape and reel
December 2011 Doc ID 022529 Rev 2 1/51
DSon
DMOS
www.st.com
51
Contents L6474
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5 Absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.6 Step sequence control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7 Enable and disable commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8 Internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.8.1 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.8.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.9 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.10 Undervoltage lock-out (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.11 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.12 Reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.13 Programmable DMOS slew-rate, dead-time and blanking-time . . . . . . . . 24
6.14 Integrated analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.15 Internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/51 Doc ID 022529 Rev 2
L6474 Contents
6.16 SYNC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.17 FLAG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Phase current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Peak current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 Auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 28
7.4 Torque regulation (output current amplitude regulation) . . . . . . . . . . . . . . 29
8 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9 Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 Registers and flags description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1.1 ABS_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1.2 EL_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1.3 MARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1.4 TVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1.5 T_FAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1.6 TON_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1.7 TOFF_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.1.8 ADC_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1.9 OCD_TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1.10 STEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1.11 ALARM_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1.12 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1.13 STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2 Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2.1 Command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2.2 Nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2.3 SetParam (PARAM, VALUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.4 GetParam (PARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.5 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.6 Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.7 GetStatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 022529 Rev 2 3/51
List of tables L6474
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Typical application values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. CL values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. EL_POS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers . 34
Table 12. T_FAST register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. Maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Minimum ON time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. Minimum OFF time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. ADC_OUT value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 18. STEP_MODE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. SYNC signal source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. ALARM_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Oscillator management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24. Overcurrent event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25. Programmable power bridge output slew-rate values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 26. External torque regulation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 27. Switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 28. STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 29. STATUS register DIR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 30. Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 31. Nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 32. SetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 33. GetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 34. HardStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 35. Disable command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 36. GetStatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 37. HTSSOP28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 38. POWERSO36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 39. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/51 Doc ID 022529 Rev 2
L6474 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. HTSSOP28 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. POWERSO36 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Bipolar stepper motor control application using L6474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Normal mode and microstepping (16 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. OSCIN and OSCOUT pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Internal 3 V linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Peak current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Adaptive decay - fast decay tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Adaptive decay - switch from normal to slow+fast decay mode and vice versa . . . . . . . . . 28
Figure 12. Fast decay tuning during the falling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. SPI timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. Daisy-chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. Command with three-byte argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 16. Command with three-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17. Command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18. HTSSOP28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. POWERSO36 drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Doc ID 022529 Rev 2 5/51
Block diagram L6474
1 Block diagram
Figure 1. Block diagram
9'' 26&,1 26&287 $'&,1 95(* &3 9%227
67%<5(6
)/$*
6'2
6<1&
67&.
6',
',5
0+]
2VFLOODWRU
9''
&6
&.
([W2VFGULYHU
5HJLVWHUV
&ORFNJHQ
$'&
&RQWURO
/RJLF
9
9ROWDJH5HJ
+6 $
/6$
+6 $
/6$
+6 %
/6%
+6 %
/6%
63,
&XUUHQW'$&V
&RPSDUDWRUV
9''
'*1'
7HPSHUDWXUH
VHQVLQJ
&KDUJH
SXPS
9ERRW 9ERRW
+6 $
/6$
9ERRW 9ERRW
+6 %
/6%
&XUUHQW
VHQVLQJ
96$
96$
+6 $
287$
287$
/6$
3*1'
96%
96%
+6 %
287%
287%
/6%
3*1'
$*1'
!-V
6/51 Doc ID 022529 Rev 2
L6474 Electrical data
2 Electrical data
2.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Test condition Value Unit
VDD Logic interface supply voltage 5.5 V
VS Motor supply voltage VSA = VSB = VS 48 V
Differential voltage between AGND,
V
V
V
V
I
out_peak
1. Maximum output current limit is related to metal connection and bonding characteristics. Actual limit must satisfy maximum
thermal dissipation constraints.
2. TBD.
GND, diff
V
boot
V
REG
ADCIN
V
OSC
out_diff
LOGIC
I
out
T
OP
T
P
tot
PGND and DGND
Bootstrap peak voltage 55 V
Internal voltage regulator output pin
and logic supply voltage
Integrated ADC input voltage range
(ADCIN pin)
OSCIN and OSCOUT pin voltage
range
Differential voltage between V
, OUT2A, PGND and VSB,
OUT1
A
OUT1
, OUT2B, PGND pins
B
SA
,
= VSB = VS 48 V
V
SA
Logic inputs voltage range -0.3 to +5.5 V
(1)
R.m.s. output current 3 A
(1)
Pulsed output current T
< 1 ms 7 A
PULSE
Operating junction temperature 150 °C
Storage temperature range -55 to 150 °C
s
Total power dissipation (TA = 25 ºC)
(2)
±0.3 V
3.6 V
-0.3 to +3.6 V
-0.3 to +3.6 V
TBD W
Doc ID 022529 Rev 2 7/51
Electrical data L6474
2.2 Recommended operating conditions
Table 3. Recommended operating conditions
Symbol Parameter Test condition Value Unit
V
Logic interface supply voltage
DD
V
Motor supply voltage VSA = VSB = VS 8 45 V
S
Differential voltage between
, OUT1A, OUT2A, PGND
V
V
out_diff
SA
and V
, OUT1B, OUT2B,
SB
PGND pins
V
Logic supply voltage
REG,in
Integrated ADC input voltage
V
ADC
(ADCIN pin)
Operating junction temperature -25 125 °C
T
j
2.3 Thermal data
Table 4. Thermal data
Symbol Parameter Package Typ Unit
R
thJA
1. TBD.
2. TBD.
Thermal resistance junction-ambient
3.3 V logic outputs 3.3 V
5 V logic outputs 5
V
= V
SA
V
REG
external source
= VS 45 V
SB
voltage imposed by
HTSSOP28
POWERSO36
3.2 3.3 V
TBD
TBD
REG
V
°C/W
0 V
(1)
(2)
8/51 Doc ID 022529 Rev 2
L6474 Electrical characteristics
3 Electrical characteristics
VSA = VSB = 36 V; VDD = 3.3 V; internal 3 V regulator; TJ = 25 °C, unless otherwise
specified.
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
General
V
SthOn
V
SthOff
V
SthHyst VS
I
q
T
j(WRN)
T
j(SD)
VS UVLO turn-on threshold 7.5 8.2 8.9 V
VS UVLO turn-off threshold 6.6 7.2 7.8 V
UVLO threshold hysteresis 0.7 1 1.3 V
Quiescent motor supply current
Thermal warning temperature 130 °C
Thermal shutdown temperature 160 °C
Charge pump
Voltage swing for charge pump oscillator 10 V
V
pump
f
pump,min
f
pump,max
I
boot
Minimum charge pump oscillator frequency
(1)
Maximum charge pump oscillator frequency
(1)
Average boot current
Output DMOS transistor
High side switch ON resistance
R
DS(on)
Low side switch ON resistance
I
DSS
t
Leakage current
Rise time
r
(3)
Internal oscillator selected;
V
= 3.3 V ext; CP
REG
floating
= f
f
sw,A
= 15.6 kHz
sw,B
POW_SR = ‘10’
= 25 °C, I
T
j
T
= 125 °C,
j
T
= 25 °C, I
j
= 125 °C,
T
j
OUT = V
= 3A 0.37
out
(2)
I
= 3A 0.51
out
= 3A 0.18
out
(2)
I
= 3A 0.23
out
S
OUT = GND -0.3
POW_SR = '00', I
POW_SR = '00', I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
= +1A 100
out
= -1A 80
out
= ±1A 100
out
= ±1A 200
out
= ±1A 300
out
0.5 0.65 mA
660 kHz
800 kHz
1.1 1.4 mA
Ω
3.1
mA
ns
Doc ID 022529 Rev 2 9/51
Electrical characteristics L6474
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
(3)
SR
SR
t
f
out_r
out_f
Fall time
Output rising slew-rate
Output falling slew-rate
Dead time and blanking
POW_SR = '00'; I
POW_SR = '00'; I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
POW_SR = '00', I
POW_SR = '00', I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
POW_SR = '00', I
POW_SR = '00', I
POW_SR = ‘11’, I
POW_SR = ‘10’, I
POW_SR = ‘01’, I
= +1A 90
out
= -1A 110
out
= ±1A 110
out
= ±1A 260
out
= ±1A 375
load
= +1A 285
out
= -1A 360
out
= ±1A 285
out
= ±1A 150
out
= ±1A 95
out
= +1A 320
out
= -1A 260
out
= ±1A 260
out
= ±1A 110
out
= ±1A 75
out
POW_SR = '00' 250
ns
V/µs
V/µs
t
DT
t
blank Blanking time
Dead time
Source-drain diodes
High side diode forward ON voltage I
V
SD,HS
V
Low side diode forward ON voltage I
SD,LS
t
rrHS
t
rrLS
High side diode reverse recovery time I
Low side diode reverse recovery time I
(1)
(1)
POW_SR = ‘11’,
= 16 MHz
f
OSC
POW_SR = ‘10’,
f
= 16 MHz
OSC
POW_SR = ‘01’,
= 16 MHz
f
OSC
375
625
875
POW_SR = '00' 250
POW_SR = ‘11’,
= 16 MHz
f
OSC
POW_SR = ‘10’,
= 16 MHz
f
OSC
POW_SR = ‘01’,
f
= 16 MHz
OSC
= 1 A 1 1.1 V
out
= 1 A 1 1.1 V
out
= 1 A 30 ns
out
= 1 A 100 ns
out
375
625
875
ns
ns
10/51 Doc ID 022529 Rev 2
L6474 Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Logic inputs and outputs
V
Low logic level input voltage 0.8 V
IL
V
High logic level input voltage 2 V
IH
I
IH
I
IL
V
OL
High logic level input current
Low logic level input current
Low logic level output voltage
VOH High logic level output voltage
RPU
R
R
PUDIR
I
logic
PD
CS pull-up and STBY pull-down resistors
DIR input pull-up resistance DIR = GND 60 85 110 kΩ
Internal logic supply current
(4)
V
(5)
(6)
= 5 V 1 µA
IN
V
= 0 V -1 µA
IN
VDD = 3.3 V, IOL = 4 mA 0.3
VDD = 5 V, IOL = 4 mA 0.3
V
= 3.3 V, IOH = 4 mA 2.4
DD
= 5 V, IOH = 4 mA 4.7
V
DD
= GND;
CS
STBY/RST
3.3 V V
= 5 V
externally
REG
supplied, internal oscillator
335 430 565 kΩ
3.7 4.3 mA
V
V
I
logic,STBY
f
Standby mode internal logic supply current
Step clock input frequency 2 MHz
STCK
Internal oscillator and external oscillator driver
Internal oscillator frequency T
f
osc,i
f
Programmable external oscillator frequency 8 32 MHz
osc,e
V
OSCOUTH
V
OSCOUTL
t
rOSCOUT
t
fOSCOUT
t
t
OSCOUT clock source high level voltage
OSCOUT clock source low level voltage
OSCOUT clock source rise and fall time Internal oscillator 20 ns
Internal to external oscillator switching delay 3 ms
extosc
intosc
External to internal oscillator switching delay 1.5 µs
SPI
f
Maximum SPI clock frequency
CK,MAX
t
rCK
t
fCK
t
hCK
t
lCK
t
setCS
SPI clock rise and fall time
SPI clock high and low time
Chip select set-up time
(7)
(7)
(7)
(7)
3.3 V V
supplied
= 25 °C, V
j
externally
REG
REG
2 2.5 µA
= 3.3 V -3% 16 +3% MHz
Internal oscillator 3.3 V
V
externally supplied;
REG
I
OSCOUT
= 4 mA
2.4 V
Internal oscillator 3.3 V
V
externally supplied;
REG
I
OSCOUT
= 4 mA
0.3 V
5 MHz
CL = 30 pF 25 ns
75 ns
350 ns
Doc ID 022529 Rev 2 11/51
Electrical characteristics L6474
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
(7)
(7)
10 ns
800 ns
(7)
(7)
(7)
(7)
(7)
(7)
37 ns
25 ns
20 ns
38 ns
47 ns
57 ns
t
Chip select hold time
holCS
t
Deselect time
disCS
t
setSDI
t
holSDI
t
enSDO
t
disSDO
t
vSDO
t
holSDO
Data input set-up time
Data input hold time
Data output enable time
Data output disable time
Data output valid time
Data output hold time
Current control
I
STEP,max
I
STEP,m in
Max. programmable reference current 4 A
Min. programmable reference current 31 mA
Overcurrent protection
I
OCD,MAX
I
OCD,MIN
I
OCD,RES
t
OCD,Flag
t
OCD,SD
Maximum programmable overcurrent
detection threshold
Minimum programmable overcurrent
detection threshold
Programmable overcurrent detection
threshold resolution
OCD to flag signal delay time dI
OCD to shut down delay time
Standby
qSTBY
t
STBY,min
t
logicwu
t
cpwu
conditions
Minimum standby time 10 µs
Logic power-on and wake-up time 38 45 µs
Charge pump power-on and wake-up time
Quiescent motor supply current in standby
I
Internal voltage regulator
OCD_TH = ‘1111’ 6 A
OCD_TH = ‘0000’ 0.375 A
0.375 A
= 350A/µs 650 1000 ns
out/dt
= 350A/µs
dI
out/dt
POW_SR = '10'
V
= 8 V 26 34
S
S = 36 V 30 36
V
Power bridges disabled, C
= 10 nF, C
= 220 nF
boot
p
600 µs
µA
650 µs
Voltage regulator output voltage 2.9 3 3.2 V
V
REG
I
Voltage regulator output current 40 mA
REG
V
REG, drop
I
REG,STBY
Voltage regulator output voltage drop I
= 40 mA 50 mV
REG
Voltage regulator standby output current 10 mA
Integrated analog to digital converter
Analog to digital converter resolution 5 bit
N
ADC
12/51 Doc ID 022529 Rev 2
L6474 Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
V
1. Accuracy depends on oscillator frequency accuracy.
2. Tested at 25 °C in a restricted range and guaranteed by characterization.
3. Rise and fall time depends on motor supply voltage value. Refer to SR
4. Not valid for STBY/RST
5. Not valid for SW and CS pins which have internal pull-up resistor.
6. FLAG
7. See Figure 13– SPI timings diagram for details.
Analog to digital converter reference voltage V
ADC,ref
f
S
rise and fall time.
Analog to digital converter sampling
frequency
out
pins which have internal pull-down resistor.
and SYNC open drain outputs included.
V
REG
f
/
OSC
512
values (Table 5) in order to evaluate the actual
kHz
Doc ID 022529 Rev 2 13/51
Pin connection L6474
4 Pin connection
Figure 2. HTSSOP28 pin connection (top view)
RST
DIR
Figure 3. POWERSO36 pin connection (top view)
74"
74"
74#
74#
48
&1"%
$1
1(/%
065"
065"
45#:345
"%$*/
73&(
04$*/
04$065
"(/%
7#005
065#
065#
065"
065"
74"
74"
45$,
'-"(
$4
#64:=4:/$
%(/%
4%*
$,
4%0
7%%
74#
74#
065#
065#
1(/%
14/51 Doc ID 022529 Rev 2
L6474 Pin connection
4.1 Pin list
Table 6. Pin description
N. Name Type Function
17 VDD Power Logic outputs supply voltage (pull-up reference)
6 VREG Power
7 OSCIN Analog input
Internal 3 V voltage regulator output and 3.3 V external logic
supply
Oscillator pin 1. To connect an external oscillator or clock source.
If this pin is unused, it should be left floating.
Oscillator pin 2. To connect an external oscillator. When the
8 OSCOUT Analog output
internal oscillator is used this pin can supply 2/4/8/16 MHz. If this
pin is unused, it should be left floating.
10 CP Output Charge pump oscillator output
11 VBOOT Supply voltage
Bootstrap voltage needed for driving the high side power DMOS of
both bridges (A and B)
5 ADCIN Analog input Internal analog to digital converter input
2
VSA Power supply Full bridge A power supply pin. It must be connected to VSB
26
12
VSB Power supply Full bridge B power supply pin. It must be connected to VSA
16
27
PGND Ground Power ground pin
13
1 OUT1A Power output Full bridge A output 1
28 OUT2A Power output Full bridge A output 2
14 OUT1B Power output Full bridge B output 1
15 OUT2B Power output Full bridge B output 2
9 AGND Ground Analog ground
4 DIR Logical input Direction input
21 DGND Ground Digital ground
22 SYNC Open drain output Synchronization signal.
18 SDO Logic output Data output pin for serial interface
20 SDI Logic input Data input pin for serial interface
19 CK Logic input Serial interface clock
23 CS Logic input Chip select input pin for serial interface
Status flag pin. An internal open drain transistor can pull the pin to
24 FLAG Open drain output
GND when a programmed alarm condition occurs (step loss,
OCD, thermal pre-warning or shutdown, UVLO, wrong command,
non performable command)
Standby and reset pin. LOW logic level resets the logic and puts
3 STBY\RST
Logic input
the device into standby mode. If not used, should be connected to
VDD
Doc ID 022529 Rev 2 15/51
Pin connection L6474
Table 6. Pin description (continued)
N. Name Type Function
25 STCK Logic input Step clock input
EPAD Exposed pad Ground Internally connected to PGND, AGND and DGND pins
16/51 Doc ID 022529 Rev 2
L6474 Typical applications
5 Typical applications
Table 7. Typical application values
Name Value
220 nF
C
VS
C
C
C
100 µF
VSPOL
C
100 nF
REG
47 µF
REGPOL
C
100 nF
DD
10 µF
DDPOL
D1 Charge pump diodes
C
220 nF
BOOT
C
10 nF
FLY
R
39 kΩ
PU
R
100 Ω
SW
CSW 10 nF
Figure 4. Bipolar stepper motor control application using L6474
#
"//4
$
(/34
'0)/
30)
#
$$0/,
2
2
05
05
&,!'
39.#
34#+
34"9
$)2
#3
#+
3$/
3$)
/3#).
/3#/54
#
$$
,
#
63
#
&,9
6"//4 #0 63" 63!6$$62%'
!$#).
/54!
/54!
/54"
/54"
0'.$!'.$$'.$
63
66
#
-OTOR
630/,
Doc ID 022529 Rev 2 17/51
Functional description L6474
6 Functional description
6.1 Device power-up
At power-up end, the device state is the following:
● Registers are set to default
● Internal logic is driven by internal oscillator and a 2 MHz clock is provided by the
OSCOUT pin
● Bridges are disabled (High Z)
● UVLO bit in STATUS register is forced low (fail condition)
● FLAG output is forced low.
During power-up the device is under reset (all logic IO disabled and power bridges in high
impedance state) until the following conditions are satisfied:
● V
●
● Internal oscillator is operative.
is greater than V
S
V
is greater than V
REG
SthOn
REGth
= 2.8 V typical
6.2 Logic I/O
Pins CS, CK, SDI, STCK, DIR and STBY\RST are TTL/CMOS 3.3 V-5 V compatible logic
inputs.
Pin SDO is a TTL/CMOS compatible logic output. VDD pin voltage sets the logic output pin
voltage range; when it is connected to VREG or 3.3 V external supply voltage, the output is
3.3 V compatible. When VDD is connected to a 5 V supply voltage, SDO is 5 V compatible.
VDD is not internally connected to V
A 10 µF capacitor should be connected to the VDD pin in order to obtain a proper operation.
Pins FLAG
and SYNC are open drain outputs.
6.3 Charge pump
To ensure the correct driving of the high side integrated MOSFETs, a voltage higher than
the motor power supply voltage needs to be applied to the VBOOT pin. The high side gate
driver supply voltage VBOOT is obtained through an oscillator and a few external
components realizing a charge pump (see Figure 5).
, an external connection is always needed.
REG
18/51 Doc ID 022529 Rev 2
L6474 Functional description
Figure 5. Charge pump circuitry
6.4 Microstepping
The driver is able to divide the single step into up to 16 microsteps. Stepping mode can be
programmed by STEP_SEL parameter in STEP_MODE register (see Ta bl e 1 9 ).
Step mode can only be changed when bridges are disabled. Every time the step mode is
changed, the electrical position (i.e. the point of microstepping sinewave that is generated)
is reset to the first microstep and the absolute position counter value (see Section 6.5)
becomes meaningless.
Figure 6. Normal mode and microstepping (16 microsteps)
Doc ID 022529 Rev 2 19/51
Functional description L6474
6.5 Absolute position counter
An internal 22 bit register (ABS_POS) takes memory of motor motion according to the
selected step mode; the stored value unit is equal to the selected step mode (full, half,
quarter, etc.). The position range is from -2
21
to +221-1 (µ) steps (see Section 9.1.1).
6.6 Step sequence control
The motor movement is defined by the step clock signal applied to the STCK pin. At each
step clock rising edge, the motor is moved by one microstep in the direction selected by DIR
input (high for forward direction and low for reverse direction) and absolute position is
consequently updated.
6.7 Enable and disable commands
The power stage of the device can be enabled and disabled through the respective SPI
commands.
The enable command turns on the power outputs and starts the current control algorithm.
The phase currents are controlled according to present EL_POS value. If a fault condition
requires the power stage to be disabled, the command is ignored.
The disable command immediately forces the power outputs in a high impedance condition.
20/51 Doc ID 022529 Rev 2
L6474 Functional description
6.8 Internal oscillator and oscillator driver
The control logic clock can be supplied by the internal 16 MHz oscillator, an external
oscillator (crystal or ceramic resonator) or a direct clock signal.
These working modes can be selected by EXT_CLK and OSC_SEL parameters in the
CONFIG register (see Ta b le 2 3 ).
At power-up the device starts using the internal oscillator and provides a 2 MHz clock signal
on the OSCOUT pin.
Attention: In any case, before changing clock source configuration, a
hardware reset is mandatory. Switching to different clock
configurations during operation could cause unexpected
behavior.
6.8.1 Internal oscillator
In this mode the internal oscillator is activated and OSCIN is unused. If OSCOUT clock
source is enabled, the OSCOUT pin provides a 2, 4, 8 or 16 MHz clock signal (according to
OSC_SEL value); otherwise it is unused (see Figure 7).
6.8.2 External clock source
Two types of external clock source can be selected: crystal/ceramic resonator or direct clock
source. Four programmable clock frequencies are available for each external clock source:
8, 16, 24 and 32 MHz.
When an external crystal/resonator is selected, the OSCIN and OSCOUT pins are used to
drive the crystal/resonator (see Figure 7). The crystal/resonator and load capacitors (CL)
must be placed as close as possible to the pins. Refer to Ta bl e 8 for the choice of the load
capacitor value according to the external oscillator frequency.
Table 8. CL values according to external oscillator frequency
Crystal/resonator freq.
8 MHz 25 pF (ESR
16 MHz 18 pF (ESR
24 MHz 15 pF (ESR
32 MHz 10 pF (ESR
1. First harmonic resonance frequency.
2. Lower ESR value allows driving greater load capacitors.
If a direct clock source is used, it must be connected to the OSCIN pin and the OSCOUT pin
supplies the inverted OSCIN signal (see Figure 7).
(1)
CL
(2)
max
max
max
max
= 80 Ω)
= 50 Ω)
= 40 Ω)
= 40 Ω)
Doc ID 022529 Rev 2 21/51
Functional description L6474
Figure 7. OSCIN and OSCOUT pin configurations
Note: When OSCIN is UNUSED, it should be left floating.
When OSCOUT is UNUSED it should be left floating.
6.9 Overcurrent detection
When the current in any of the power MOSFETs exceeds a programmed overcurrent
threshold, the STATUS register OCD flag is forced low until the overcurrent event has
expired and a GetStatus command is sent to the IC (see paragraphs 9.1.13 and 9.1.9).
Overcurrent event expires when all the power MOSFET currents fall below the programmed
overcurrent threshold.
The overcurrent threshold can be programmed through the OCD_TH register in one of 16
available values ranging from 375 mA to 6 A with steps of 375 mA (see Ta bl e 9 , paragraph
9.1.9).
It is possible to set whether or not an overcurrent event causes the MOSFET turn-off
(bridges in high impedance status) acting on the OC_SD bit in the CONFIG register (see
paragraph 9.1.12). The OCD flag in the STATUS register is raised anyway (see Ta bl e 2 8 ,
paragraph 9.1.13).
When the IC outputs are turned off by an OCD event, they cannot be turned on until the
OCD flag is released by a GetStatus command.
22/51 Doc ID 022529 Rev 2
L6474 Functional description
Attention: The overcurrent shutdown is a critical protection feature. It is
not recommended to disable it.
6.10 Undervoltage lock-out (UVLO)
The L6474 provides a motor supply UVLO protection. When the motor supply voltage falls
below the VSthOff threshold voltage, the STATUS register UVLO flag is forced low. When a
GetStatus command is sent to the IC, and the undervoltage condition has expired, the
UVLO flag is released (see paragraphs 9.1.13 and 9.2.7). Undervoltage condition expires
when the motor supply voltage goes over the VSthOn threshold voltage. When the device is
in undervoltage condition no motion can be performed. The UVLO flag is forced low by logic
reset (power-up included) even if no UVLO condition is present.
6.11 Thermal warning and thermal shutdown
An internal sensor allows the L6474 to detect when the device internal temperature exceeds
a thermal warning or an overtemperature threshold.
When the thermal warning threshold (T
register is forced low (see paragraph 9.1.13) until the temperature decreases below T
and a GetStatus command is sent to the IC (see paragraphs 9.1.13 and 9.2.7).
When the thermal shutdown threshold (T
shutdown condition: the TH_SD bit in the STATUS register is forced low, the power bridges
are disabled, bridges in high impedance state and the HiZ bit in the STATUS register are
raised (see paragraph 9.1.13).
Thermal shutdown condition only expires when the temperature goes below the thermal
warning threshold (T
On exiting thermal shutdown condition, the bridges are still disabled (HiZ flag high).
j(WRN)
6.12 Reset and standby
The device can be reset and put into standby mode through a dedicated pin. When the
STBY
\RST pin is driven low, the bridges are left open (High Z state), the internal charge
pump is stopped, the SPI interface and control logic are disabled, and the internal 3 V
voltage regulator maximum output current is reduced to I
heavily reduces the power consumption. At the same time the register values are reset to
default and all protection functions are disabled. STBY\RST
least for tSTBY, min. in order to ensure the complete switch to standby mode.
On exiting standby mode, as well as for IC power-up, a delay of up to tlogicwu must be given
before applying a new command to allow proper oscillator and logic startup and a delay of
up to tcpwu must be given to allow the charge pump startup.
) is reached, the TH_WRN bit in the STATUS
j(WRN)
) is reached, the device goes into thermal
j(OFF)
).
REG,STBY
; as a result the L6474
input must be forced low at
j(WRN)
On exiting standby mode the bridges are disabled (HiZ flag high).
Doc ID 022529 Rev 2 23/51
Functional description L6474
Attention: It is not recommended to reset the device when outputs are
active. The device should be switched to high impedance
state before being reset.
6.13 Programmable DMOS slew-rate, dead-time and blanking-time
Using the POW_SR parameter in the CONFIG register, it is possible to set the commutation
speed of the power bridges output (see Ta bl e 2 5, paragraph 9.1.17).
6.14 Integrated analog to digital converter
The L6474 integrates a NADC bit ramp-compare analog to digital converter with a reference
voltage equal to VREG. The analog to digital converter input is available through the ADCIN
pin and the conversion result is available in the ADC_OUT register (see paragraph 9.1.13).
Sampling frequency is equal to the clock frequency divided by 512.
The ADC_OUT value can be used for the torque regulation or is at the user’s disposal.
6.15 Internal voltage regulator
The L6474 integrates a voltage regulator which generates a 3 V voltage starting from the
motor power supply (VSA and VSB). In order to make the voltage regulator stable, at least
22 µF should be connected between the VREG pin and ground (suggested value is 47 µF).
The internal voltage regulator can be used to supply the VDD pin in order to make the
device digital output range 3.3 V compatible (Figure 8). A digital output range 5 V
compatible can be obtained connecting the VDD pin to an external 5 V voltage source. In
both cases, a 10 µF capacitance should be connected to the VDD pin in order to obtain a
correct operation.
The internal voltage regulator is able to supply a current up to I
consumption included (I
can be supplied is I
REG, STBY
If an external 3.3 V regulated voltage is available, it can be applied to the VREG pin in order
to supply all the internal logic and avoid power dissipation of the internal 3 V voltage
regulator (Figure 8). The external voltage regulator should never sink current from the
VREG pin.
). When the device is in standby mode the maximum current that
logic
, internal consumption included (I
REG,MAX, internal logic
logic, STBY
).
24/51 Doc ID 022529 Rev 2
L6474 Functional description
Figure 8. Internal 3 V linear regulator
6"!4
6S
6
$$
6
62%' 6$$ 63! 63"
6
2%'
62%' 6$$ 63! 63"
6
S
M#
6.16 SYNC pin
This pin works as a synchronization signal: the output status is an echo of one of the bits of
the EL_POS register according to a SYNC_SEL and STEP_SEL parameter combination
(see paragraph 9.1.10).
6.17 FLAG pin
By default, an internal open drain transistor pulls the FLAG pin to ground when at least one
of the following conditions occurs:
● Power-up or standby/reset exit
● Overcurrent detection
● Thermal warning
● Thermal shutdown
● UVLO
● Switch turn-on event
● Wrong command
● Non performable command.
,OGIGSUPPLIEDBY
).4%2.!,VOLTAGEREGULATOR
)#
)#
!'.$$'.$
,OGIGSUPPLIEDBY
%84%2.!,VOLTAGEREGULATOR
!'.$$'.$
It is possible to mask one or more alarm conditions by programming the ALARM_EN
register (see paragraph 9.1.11, Ta b le 2 1 ). If the corresponding bit of the ALARM_EN
register is low, the alarm condition is masked and it does not cause a FLAG pin transition; all
other actions imposed by alarm conditions are performed anyway. In case of daisy-chain
configuration, FLAG pins of different ICs can be or-wired to save host controller GPIOs.
Doc ID 022529 Rev 2 25/51
Phase current control L6474
7 Phase current control
The L6474 performs a peak current control technique described in detail in Section 7.1.
Furthermore, the L6474 automatically selects the best decay mode in order to follow the
current profile.
Current control algorithm parameters can be programmed by T_FAST, TON_MIN,
TOFF_MIN and CONFIG registers (see paragraphs 9.1.5, 9.1.6, 9.1.7 and 9.1.12 for
details).
The current amplitude can be set through the TVAL register (see paragraph 9.1.4). The
output current amplitude can also be regulated by ADCIN voltage value (see paragraph
6.14).
Each bridge is driven by an independent control system that shares with the other bridge the
control parameters only.
7.1 Peak current control
The L6474 implements a peak current control algorithm with fixed OFF time. The control
cycle begins in the ON state: the opposite high side DMOS low side DMOS of the power
bridges are turned on according to the required current direction. In this way, the phase
current is increased according to the electrical model of the motor.
When the target current value is reached (this value is internally generated according to the
present value of the EL_POS register), the device switches to the OFF state in order to
make the phase current decay. During the OFF state both slow and fast decay can be
performed; the better decay combination is automatically selected by L6472 as described in
section 7.2.
The t
the TOFF_MIN register. If TOFF is greater than TOFF_MIN, it defines the OFF time of the
system. Otherwise the TOFF_MIN value is used.
Figure 9. Peak current control
value sets through the TOFF parameter of the CONFIG register and the value of
OFF
26/51 Doc ID 022529 Rev 2
L6474 Phase current control
7.2 Auto-adjusted decay mode
During the current control, the device automatically selects the best decay mode in order to
follow the current profile reducing the current ripple.
At reset, the OFF time is performed by turning on both the low side MOS of the power stage
and the current recirculates in the lower half of the bridge (slow decay).
If, during a PWM cycle, the target current threshold is reached in a time shorter than the
TON_MIN value, a fast decay of TOFF_FAST/8 (T_FAST register) is immediately
performed, turning on the opposite MOS of both half bridges and the current recirculates
back to the supply bus.
After this time, the bridge returns to the ON state: if the time needed to reach the target
current value is still less than TON_MIN, a new fast decay is performed with a period twice
the previous one. Otherwise, the normal control sequence is followed as described in
section 7.1. The maximum fast decay duration is set by TOFF_FAST value.
Figure 10. Adaptive decay - fast decay tuning
STFASTDECAY
4FAST4/&&?&!34
RDFASTDECAY
4FAST4/&&?&!34
4ON4/.?-).
4FAST4/&&?&!34
NDFASTDECAY
4FAST4/&&?&!34
REFERENCECURRENT
.OTESTARTINGFROM
FASTANDSLOWDECAYDURINGTHE/&&PHASE
ND
FASTDECAYTHESYSTEMWILLCOMBINE
4IME
When two or more fast decays are performed with present target current, the control system
adds a fast decay at the end of every OFF time, keeping the OFF state duration constant
(t
is split into t
OFF
OFF,SLOW
and t
OFF,FAST
). When the current threshold is increased by a
micro-step change (rising step), the system returns to normal decay mode (slow decay only)
and the t
value is halved.
FAS T
Reaching the current sinewave zero crossing causes the current control system to return to
the reset state.
Doc ID 022529 Rev 2 27/51
Phase current control L6474
Figure 11. Adaptive decay - switch from normal to slow+fast decay mode and vice
versa
reference current
1st fast decay
t
OFF
Target current is increased (raising step)
system returns to slow decay mode and t
nd
fast decay
switch to fast + slow decay mode
2
t
FAST
value is halved
FAST
t
OFF,SLOW
Time
t
OFF
t
OFF,FAST
reference current
7.3 Auto-adjusted fast decay during the falling steps
When the target current is decreased by a micro-step change (falling step), the device
performs a fast decay in order to reach the new value as fast as possible. Anyway,
exceeding the fast duration could cause a strong ripple on the step change. The L6474
automatically adjusts these fast decays reducing the current ripple.
At reset, the fast decay value (t
value is doubled every time, within the same falling step, an extra fast decay is necessary to
obtain an ON time greater than TON_MIN. The maximum t
FALL_STEP.
At the next falling step, the system uses the last t
Stopping the motor or reaching the current sinewave zero crossing causes the current
control system to return to the reset state.
) is set to FALL_STEP/4 (T_FAST register). The t
FAL L
value is equal to
FALL
value of the previous falling step.
FALL
Time
FALL
28/51 Doc ID 022529 Rev 2
L6474 Phase current control
Figure 12. Fast decay tuning during the falling steps
&ALLINGSTEP
REFERENCECURRENT
STFASTDECAY
T
&!,,?34%0
&!,,
ND
FASTDECAY
T
&!,,?34%0
&!,,
&ALLINGSTEP
STFASTDECAY
T
&!,,?34%0
&!,,
4IME
7.4 Torque regulation (output current amplitude regulation)
The output current amplitude can be regulated in two ways: writing the TVAL register or
varying the ADCIN voltage value.
The EN_TQREG bit (CONFIG register) sets the torque regulation method. If this bit is high,
ADC_OUT prevalue is used to regulate output current amplitude (see paragraph 9.1.8).
Otherwise the internal analog to digital converter is at the user’s disposal and the output
current amplitude is managed by the TVAL register (see paragraph 9.1.4).
The voltage applied to the ADCIN pin is sampled at fS frequency and converted in an NADC
bit digital signal. The analog to digital conversion result is available in the ADC_OUT
register.
Doc ID 022529 Rev 2 29/51
Serial interface L6474
8 Serial interface
The integrated 8-bit serial peripheral interface (SPI) is used for a synchronous serial
communication between the host microprocessor (always master) and the L6474 (always
slave).
The SPI uses chip select (CS
output (SDO) pins. When CS
(high-impedance).
The communication starts when CS
data communication.
All commands and data bytes are shifted into the device through the SDI input, most
significant bit first. The SDI is sampled on the rising edges of the CK.
All output data bytes are shifted out of the device through the SDO output, most significant
bit first. The SDO is latched on the falling edges of the CK. When a return value from the
device is not available, an all zero byte is sent.
After each byte transmission, the CS
tdisCS in order to allow the device to decode the received command and put the return
value into the shift register.
All timing requirements are shown in Figure 13 (see respective Section 3: Electrical
characteristics for values).
Multiple devices can be connected in a daisy-chain configuration, as shown in Figure 14.
Figure 13. SPI timings diagram
), serial clock (CK), serial data input (SDI) and serial data
is high, the device is unselected and the SDO line is inactive
is forced low. The CK line is used for synchronization of
input must be raised and be kept high for at least
30/51 Doc ID 022529 Rev 2
L6474 Serial interface
Figure 14. Daisy-chain configuration
Doc ID 022529 Rev 2 31/51
Programming manual L6474
9 Programming manual
9.1 Registers and flags description
The following is a map of the user registers available (detailed description in respective
paragraphs):
Table 9. Registers map
Address
[Hex]
h01 ABS_POS Current position 22 000000 0 R, WR
h02 EL_POS Electrical position 9 000 0 R, WR
h03 MARK Mark position 22 000000 0 R, WR
h04 RESERVED Reserved address 24
h05 RESERVED Reserved address 16
h06 RESERVED Reserved address 16
h07 RESERVED Reserved address 16
h08 RESERVED Reserved address 16
h15 RESERVED Reserved address 16 R, WR
h09 TVAL Reference current 7 29 1.3125 A R, WR
h0A RESERVED Reserved address 8
h0B RESERVED Reserved address 8
h0C RESERVED Reserved address 8
h0D RESERVED Reserved address 16
h0E T_FAST Fast decay/fall step time 8 19 1 µs / 5 µs R, WH
h0F TON_MIN Minimum ON time 7 29 20.5 µs R, WH
h10 TOFF_MIN Minimum OFF time 7 29 20.5 µs R, WH
Register
name
Register function Len. [bit]
Reset
Hex
Reset Value
Remarks
(1)
h11 RESERVED Reserved address 8
h12 ADC_OUT ADC output 5 XX
h13 OCD_TH OCD threshold 4 8 3.38A R, WR
h14 RESERVED Reserved address 8
h16 STEP_MODE Step mode 8 7 16 microsteps, no synch R, WH
h17 ALARM_EN Alarms enables 8 FF All alarms enabled R, WR
h18 CONFIG IC configuration 16 2E88
32/51 Doc ID 022529 Rev 2
(2)
Internal oscillator, 2 MHz
OSCOUT clock, supply
voltage compensation
disabled, overcurrent
shutdown enabled, slewrate = 290 V/µs TOFF = 40
µs
R
R, WH
L6474 Programming manual
Table 9. Registers map (continued)
Address
[Hex]
h19 STATUS Status 16 XXXX
h1A RESERVED Reserved address
h1B RESERVED Reserved address
1. R: Readable, WH: writable only when outputs are in high impedance, WR: always writable.
2. According to startup conditions.
Register
name
Register function Len. [bit]
Reset
Hex
High impedance state,
(2)
UVLO/Reset flag set.
9.1.1 ABS_POS
The ABS_POS register contains the current motor absolute position in agreement to the
selected step mode; the stored value unit is equal to the selected step mode (full, half,
quarter, etc.). The value is in 2's complement format and it ranges from -2
At power-on the register is initialized to “0” (HOME position).
9.1.2 EL_POS
The EL_POS register contains the current electrical position of the motor. The two MSbits
indicate the current step and the other bits indicate the current microstep (expressed in
step/128) within the step.
Table 10. EL_POS register
Reset Value
21
to +221-1.
Remarks
(1)
R
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
When the EL_POS register is written by the user the new electrical position is instantly
imposed. When the EL_POS register is written its value must be masked in order to match
with the step mode selected in the STEP_MODE register in order to avoid a wrong
microstep value generation (see paragraph 9.1.10); otherwise the resulting microstep
sequence is incorrect.
Any attempt to write the register when the outputs are enabled causes the command to be
ignored and the NOTPERF_CMD flag to rise (see paragraph 9.1.13).
9.1.3 MARK
The MARK register contains an absolute position called MARK, according to the selected
step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.).
It is in 2's complement format and it ranges from -2
9.1.4 TVAL
The TVAL register contains the current value that is assigned to the torque regulation DAC.
The available range is from 31.25 mA to 4 A with a resolution of 31.25 mA, as shown in
Ta bl e 2.
STEP MICROSTEP
21
to +221-1.
Doc ID 022529 Rev 2 33/51
Programming manual L6474
Table 11. Torque regulation register
TVAL [6..0] Output current amplitude
0 0 0 0 0 0 0 31.25 mA
0 0 0 0 0 0 1 62.5 mA
…
…
…
…
…
…
…
1 1 1 1 1 1 0 3.969 A
1 1 1 1 1 1 1 4 A
…
9.1.5 T_FAST
The T_FAST register contains the maximum fast decay time (TOFF_FAST) and the
maximum fall step time (FALL_STEP) used by the current control system (see Sections 7.2
and 7.3 for details):
Table 12. T_FAST register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TOFF_FAST FAST_STEP
The available range for both parameters is from 0.5 µs to 8 µs.
Table 13. Maximum fast decay times
TOFF_FAST [3..0]
FAST_STEP[3..0]
0 0 0 0 0.5 µs
0 0 0 1 1 µs
…
1 1 1 0 7.5 µs
1 1 1 1 8 µs
Any attempt to write to the register when the outputs are enabled causes the command to
be ignored and the NOTPERF_CMD to rise (see Section 9.1.13).
9.1.6 TON_MIN
The TON_MIN register contains the minimum ON time value used by the current control
system (see Section 7.2).
The available range for both parameters is from 0.5 µs to 64 µs.
…
…
…
Fast decay time
…
34/51 Doc ID 022529 Rev 2
L6474 Programming manual
Table 14. Minimum ON time
Time
0 0 0 0 0 0 0 0.5 µs
0 0 0 0 0 0 1 1 µs
…
…
…
…
…
…
…
…
1 1 1 1 1 1 0 63.5 µs
1 1 1 1 1 1 1 64 µs
Any attempt to write to the register when the outputs are enabled causes the command to
be ignored and the NOTPERF_CMD to rise (see Section 9.1.13).
9.1.7 TOFF_MIN
The TOFF_MIN register contains the minimum OFF time value used by the current control
system (see Section 7.1 for details).This parameter imposes the OFF time of the current
control system only if its value is greater than the TSW one.
The available range for both parameters is from 0.5 µs to 64 µs.
Table 15. Minimum OFF time
Time
0 0 0 0 0 0 0 0.5 µs
0 0 0 0 0 0 1 1 µs
…
…
…
…
…
…
…
…
1 1 1 1 1 1 0 63.5 µs
1 1 1 1 1 1 1 64 µs
Any attempt to write to the register when the outputs are enabled causes the command to
be ignored and the NOTPERF_CMD to rise (see Section 9.1.13).
Doc ID 022529 Rev 2 35/51
Programming manual L6474
9.1.8 ADC_OUT
The ADC_OUT register contains the result of the analog to digital conversion of the ADCIN
pin voltage.
Any attempt to write to the register causes the command to be ignored and the
NOTPERF_CMD flag to rise (see Section 9.1.13).
Table 16. ADC_OUT value and torque regulation feature
VADCIN/ VREG ADC_OUT [4..0] Output current amplitude
0 0 0 0 0 0 125 mA
1/32 0 0 0 0 1 250 mA
…
30/32 1 1 1 1 0 3.875 A
31/32 1 1 1 1 1 4 A
…
…
…
…
…
…
9.1.9 OCD_TH
The OCD_TH register contains the overcurrent threshold value (see Section 6.9 for details).
The available range is from 375 mA to 6 A, steps of 375 mA as shown in Ta bl e 1 7 .
Table 17. Overcurrent detection threshold
OCD_TH [3..0] Overcurrent detection threshold
0 0 0 0 375 mA
0 0 0 1 750 mA
…
1 1 1 0 5.625 A
1 1 1 1 6 A
…
…
…
…
36/51 Doc ID 022529 Rev 2
L6474 Programming manual
9.1.10 STEP_MODE
The STEP_MODE register has the following structure:
Table 18. STEP_MODE register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 SYNC_SEL 1
1. When the register is written this bit should be set to 1.
The STEP_SEL parameter selects one of five possible stepping modes:
Table 19. Step mode selection
STEP_SEL[2..0] Step mode
0 0 0 Full step
0 0 1 Half step
0 1 0 1/4 microstep
0 1 1 1/8 microstep
1 X X 1/16 microstep
(1)
STEP_SEL
Every time the step mode is changed, the electrical position (i.e. the point of microstepping
sinewave that is generated) is reset to the first microstep.
Warning: Every time STEP_SEL is changed the value in ABS_POS
register loses meaning and should be reset.
Any attempt to write the register when the outputs are enabled causes the command to be
ignored and the NOTPERF_CMD flag to rise (see paragraph 9.1.13).
The SYNC output provides a synchronization signal according to SYNC_SEL parameter.
Doc ID 022529 Rev 2 37/51
Programming manual L6474
The synchronization signal is obtained starting from electrical position information (EL_POS
register) according to Tab l e 1 0:
Table 20. SYNC signal source
SYNC_SEL[2..0] Source
0 0 0 EL_POS[7]
0 0 1 EL_POS[6]
0 1 0 EL_POS[5]
0 1 1 EL_POS[4]
1 0 0 EL_POS[3]
1 0 1 UNUSED
1 1 0 UNUSED
1 1 1 UNUSED
1. When this value is selected the BUSY output is forced low.
(1)
(1)
(1)
38/51 Doc ID 022529 Rev 2
L6474 Programming manual
9.1.11 ALARM_EN
The ALARM_EN register allows to select which alarm signals are used to generate the
FLAG output. If the respective bit of the ALARM_EN register is set high, the alarm condition
forces the FLAG pin output down.
Table 21. ALARM_EN register
ALARM_EN bit Alarm condition
0 (LSB) Overcurrent
1 Thermal shutdown
2 Thermal warning
3 Undervoltage
4 RESERVED
5 RESERVED
6 Switch turn-on event
7 (MSB) Wrong or not performable command
9.1.12 CONFIG
The CONFIG register has the following structure:
Table 22. CONFIG register
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
0 TOFF POW_SR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OC_SD RESERVED EN_TQREG 0 EXT_CLK OSC_SEL
Doc ID 022529 Rev 2 39/51
Programming manual L6474
The OSC_SEL and EXT_CLK bits set the system clock source:
Table 23. Oscillator management
EXT_CLK OSC_SEL[2..0] Clock source OSCIN OSCOUT
0 0 0 0
0 0 0 1
Internal oscillator: 16 MHz Unused Unused
0 0 1 0
0 0 1 1
1 0 0 0 Internal oscillator: 16 MHz Unused
1 0 0 1 Internal oscillator: 16 MHz Unused
1 0 1 0 Internal oscillator: 16 MHz Unused
1 0 1 1 Internal oscillator: 16 MHz Unused
0 1 0 0 External crystal or resonator: 8 MHz Crystal/resonator driving
0 1 0 1
0 1 1 0
0 1 1 1
1 1 0 0
External crystal or resonator: 16
MHz
External crystal or resonator: 24
MHz
External crystal or resonator: 32
MHz
Ext. clock source: 8 MHz
(Crystal/resonator driver disabled)
Crystal/resonator driving
Crystal/resonator driving
Crystal/resonator driving
Clock source
Supplies a 2 MHz
clock
Supplies a 4 MHz
clock
Supplies a 8 MHz
clock
Supplies a 16 MHz
clock
Crystal/resonator
driving
Crystal/resonator
driving
Crystal/resonator
driving
Crystal/resonator
driving
Supplies inverted
OSCIN signal
1 1 0 1
1 1 1 0
1 1 1 1
Ext. clock source: 16 MHz
(Crystal/resonator driver disabled)
Ext. clock source: 24 MHz
(Crystal/resonator driver disabled)
Ext. clock source: 32 MHz
(Crystal/resonator driver disabled)
The OC_SD bit sets whether or not an overcurrent event causes the bridges to turn off; the
OCD flag in the status register is forced low anyway:
Table 24. Overcurrent event
OC_SD Overcurrent event
1 Bridges shut down
0 Bridges do not shut down
The POW_SR bits set the slew rate value of power bridge output:
40/51 Doc ID 022529 Rev 2
Clock source
Clock source
Clock source
Supplies inverted
OSCIN signal
Supplies inverted
OSCIN signal
Supplies inverted
OSCIN signal
L6474 Programming manual
Table 25. Programmable power bridge output slew-rate values
POW_SR [1..0] Output Slew-rate (1) [V/ìs]
(1)
0 0 180
0 1 180
1 0 290
1 1 530
1. See SRout_r and SRout_f parameters in the electrical characteristics Table 5 for details.
The TQREG bit sets if the torque regulation (see Section 7.4) is performed through the
ADCIN voltage (external) or TVAL register (internal):
Table 26. External torque regulation enable
TQREG External torque regulation enable
0 Internal registers
1 ADC input
The TOFF time is used by current control system. If its value is lower than the TOFF_MIN
one, the OFF time is equal to TOFF_MIN.
Table 27. OFF time
0 0 0 0 0 4 µs
0 0 0 0 1 4 µs
0 0 0 1 0 8 µs
…
1 1 1 1 1 124 µs
Any attempt to write the CONFIG register when the outputs are enabled causes the
command to be ignored and the NOTPERF_CMD flag to rise (see Section 9.1.13).
9.1.13 STATUS
Table 28. STATUS register
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NOTPERF_CMD 0 0 DIR 0 0 1 HiZ
When HiZ flag is high, it indicates that the bridges are in high impedance state. Enable
command makes the device exit from High Z state unless error flags forcing a High Z state
are active.
TOFF [4..0] OFF time
…
…
…
…
…
1 1 1 OCD TH_SD TH_WRN UVLO WRONG_CMD
Doc ID 022529 Rev 2 41/51
Programming manual L6474
The UVLO flag is active low and is set by an undervoltage lock-out or reset events (powerup included). The TH_WRN, TH_SD, OCD flags are active low and indicate, respectively,
thermal warning, thermal shutdown and overcurrent detection events.
The NOTPERF_CMD and WRONG_CMD flags are active high and indicate, respectively,
that the command received by SPI can't be performed or does not exist at all.
The UVLO, TH_WRN, TH_SD, OCD, NOTPERF_CMD and WRONG_CMD flags are
latched: when the respective conditions make them active (low or high), they remain in that
state until a GetStatus command is sent to the IC.
The DIR bit indicates the current motor direction:
Table 29. STATUS register DIR bit
DIR Motor direction
1 Forward
0 Reverse
Any attempt to write to the register causes the command to be ignored and the
NOTPERF_CMD to rise (see paragraph 9.1.13).
9.2 Application commands
The commands summary is given in Ta bl e 3 0.
Table 30. Application commands
Command Mnemonic Command binary code Action
SetParam(PARAM,VALUE) 000 [PARAM] Writes VALUE in PARAM register
9.2.1 Command management
[7..5] [4] [3] [2..1] [0]
NOP 000 0 0 00 0 Nothing
Enable 101 1 1 00 0 Enable the power stage
Disable 101 0 1 00 0
GetStatus 110 1 0 00 0 Returns the status register value
RESERVED 111 0 1 01 1 RESERVED COMMAND
RESERVED 111 1 1 00 0 RESERVED COMMAND
Puts the bridges in High Impedance status
immediately
The host microcontroller can control motor motion and configure the L6474 through a
complete set of commands.
All commands are composed of a single byte. After the command byte, some bytes of
arguments should be needed (see Figure 15). Argument length can vary from 1 to 3 bytes.
42/51 Doc ID 022529 Rev 2
L6474 Programming manual
Figure 15. Command with three-byte argument
By default, the device returns an all zeroes response for any received byte, the only
exceptions are GetParam and GetStatus commands. When one of these commands is
received, the following response bytes represent the related register value (see Figure 16).
Response length can vary from 1 to 3 bytes.
Figure 16. Command with three-byte response
During response transmission, new commands can be sent. If a command requiring a
response is sent before the previous response is completed, the response transmission is
aborted and the new response is loaded into the output communication buffer (see
Figure 17).
Figure 17. Command response aborted
When a byte that does not correspond to a command is sent to the IC it is ignored and the
WRONG_CMD flag in the STATUS register is raised (see Section 9.1.13).
9.2.2 Nop
Table 31. Nop command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Nothing is performed.
0 0 0 0 0 0 0 0 From host
Doc ID 022529 Rev 2 43/51
Programming manual L6474
9.2.3 SetParam (PARAM, VALUE)
Table 32. SetParam command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 PARAM From host
VALUE Byte 2 (if needed)
VALUE Byte 1 (if needed)
VALUE Byte 0
The SetParam command sets the PARAM register value equal to VALUE; PARAM is the
respective register address listed in Ta b le 1 6 .
The command should be followed by the new register VALUE (most significant byte first).
The number of bytes composing the VALUE argument depends on the length of the target
register (see Ta bl e 16 ).
Some registers cannot be written (see Ta b le 1 6 ); any attempt to write one of those registers
causes the command to be ignored and the WRONG_CMD flag to rise at the end of
command byte, the same is true when an unknown command code is sent (see
Section 9.1.13).
Some registers can only be written in particular conditions (see Ta b le 1 6 ); any attempt to
write one of those registers when the conditions are not satisfied causes the command to be
ignored and the NOTPERF_CMD flag to rise at the end of last argument byte (see
Section 9.1.13).
Any attempt to set an inexistent register (wrong address value) causes the command to be
ignored and the WRONG_CMD flag to rise at the end of command byte, the same is true
when an unknown command code is sent.
9.2.4 GetParam (PARAM)
Table 33. GetParam command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 1 PARAM from host
This command reads the current PARAM register value; PARAM is the respective register
address listed in Ta bl e 1 6 .
The command response is the current value of the register (most significant byte first). The
number of bytes composing the command response depends on the length of the target
register (see Ta bl e 16 ).
ANS Byte 2 (if needed) to host
ANS Byte 1 (if needed) to host
ANS Byte 0 to host
The returned value is the register one at the moment of GetParam command decoding. If
register values change after this moment the response is not accordingly updated.
All registers can be read anytime.
44/51 Doc ID 022529 Rev 2
L6474 Programming manual
Any attempt to read an inexistent register (wrong address value) causes the command to be
ignored and the WRONG_CMD flag to rise at the end of command byte, the same is true
when an unknown command code is sent.
9.2.5 Enable
Table 34. HardStop command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 1 1 1 0 0 0 from host
The Enable command turns on the power stage of the device.
When the motor is in high-impedance state, an Enable command forces the bridges to exit
from high impedance state.
This command can be given anytime and is immediately executed.
9.2.6 Disable
Table 35. Disable command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 1 0 1 0 0 0 from host
The Disable command immediately disables the power bridges (high-impedance state) and
raises the HiZ flag.
This command can be given anytime and is immediately executed.
9.2.7 GetStatus
Table 36. GetStatus command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 0 1 0 0 0 0 from host
The GetStatus command returns the Status register value. The GetStatus command resets
the STATUS register warning flags. The command forces the system to exit from any error
state. The GetStatus command DOES NOT reset the HiZ flag.
STATUS MSByte to host
STATUS LSByte to host
Doc ID 022529 Rev 2 45/51
Package mechanical data L6474
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 37. HTSSOP28 mechanical data
mm
Dim
Min. Typ. Max.
A 1.2
A1 0.15
A2 0.8 1.0 1.05
b 0.19 0.3
c 0.09 0.2
(1)
D
D1 5.5
E 6.2 6.4 6.6
(2)
E1
E2 2.8
9.6 9.7 9.8
4.3 4.4 4.5
E 0.65
L 0.45 0.6 0.75
L1 1.0
K 0° 8°
Aaa 0.1
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
do not exceed 0.15 mm per side.
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions do not exceed
0.25 mm per side.
46/51 Doc ID 022529 Rev 2
L6474 Package mechanical data
Figure 18. HTSSOP28 mechanical data
Doc ID 022529 Rev 2 47/51
Package mechanical data L6474
Table 38. POWERSO36 mechanical data
mm inch
Dim.
Min. Typ. Max. Min. Typ. Max.
A 3.60 0.1417
a1 0.10 0.30 0.003 0.0118
a2 3.30 0.1299
a3 0 0.10 0 0.0039
b 0.22 0.38 0.008 0.0150
c 0.23 0.32 0.009 0.0126
D (1) 15.80 16.00 0.622 0.6299
D1 9.40 9.80 0.370 0.3858
E 13.90 14.50 0.547 0.5709
E1 (1) 10.90 11.10 0.429 0.4370
E2 2.90 0.1142
E3 5.8 6.2 0.228 0.2441
e 0.65 0.025
e3 11.05 0.435
G 0 0.10 0.000 0.0039
H 15.50 15.90 0.610 0.6260
h 1.10 0.0433
L 0.80 1.10 0.031 0.0433
N 10° 10°
S 0° 8° 0° 8°
48/51 Doc ID 022529 Rev 2
L6474 Package mechanical data
Figure 19. POWERSO36 drawings
11
D
'(7$,/$
$
$
H
'(7$,/%
H
+
OHDG
'(7$,/$
D
(
'
D
VOXJ
F
(
K[Û
%277209,(:
%
(
'
&
6($7,1*3/$1(
*&
&23/$1$5,7<
E
0
$%
*DJH3ODQH
3620(&
'(7$,/%
6
/
(
Doc ID 022529 Rev 2 49/51
Revision history L6474
11 Revision history
Table 39. Document revision history
Date Revision Changes
02-Dec-2011 1 Initial release.
22-Dec-2011 2
Deleted previous chapter 6.4.1 Automatic full-step mode.
Minor text changes.
50/51 Doc ID 022529 Rev 2
L6474
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2011 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 022529 Rev 2 51/51
Loading...