ST L6452 User Manual

Dual 13x16 Matrix Head Ink Jet Driver

PQFP100

Features

■ DRIVES TWO 13X16 MATRIX HEADS

■ HEAD TEMPERATURE SENSING

■ POWER UP SYSTEM

■ ELECTRICAL NOZZLE CHECK

■ 8 BIT A/D

■ 5 BIT D/A

■ ± 4KV ESD PROTECTED OUTPUTS

Description

L6452 is a device designed to drive two 13x16
matrix ink jet print heads in printer applications.

The output stage is able to source simultaneously
400 mA on each of the 16 power lines (columns)
with a duty cycle of 33% in normal printing and
66% in head pre-heating. On the address lines
(rows), the load is only capacitive (MOS FET
driving capability). The driver can control two print
heads, but only one is active at a time. The
address scanning counter is included and can be
disabled to allow a different scanning scheme.

L6452

In order to avoid output activation during the
supply transient, an internal power-up system is
implemented.

As supporting function, L6452 is capable of
sensing the head silicon temperature and to
electrically check each nozzle.

The device is also integrating a thermal
protection

.

Order codes

Part number Op. Temp range, ° CPackage Packing

E-L6452 0 to 70 PQFP100 Tray

L6452DIE8 0 to 70 DIE --

Rev 2

February 2006 1/22

www.st.com

22

Contents L6452

Contents

1 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Counter Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Decoder Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Print Head Temperature Control Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Print Head Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22

L6452 Block diagrams

PRINT HEAD

DRIVER

PRINT HEAD

TEMPERATURE

CONTROL

POWER &

LOGICAL

SUPPLIES

CONTROL

LINES

A/D & PRINT HEAD

TEMPERATURE

CONTROL LINES

ANALOG

INPUTS

PRINT HEAD

A

PRINT HEAD

B

D97IN523

13 ADDRESS LINES

CHANNEL B

16 POWER LINES

13 ADDRESS LINES

CHANNEL A

NCEN

TRIGGER

LONGPULSE

SHORTPULSE

DATA BIT 15

DATA BIT 1

DATA BIT 0

1

0

NCOUT

OUTPUT15

OUTPUT1

OUTPUT0

Va

D97IN525B

1.25mA

FROM 16 BIT
DATA LATCH

1 Block diagrams

Figure 1. Block diagram

Figure 2. Block Diagram: Power Line Output Stage.

3/22

16 BIT SERIAL

INPUT &

PARALLEL

OUTPUT

16 BIT LATCH

16 POWER

OUTPUT
STAGES

OUTPUT0

OUTPUT1

OUTPUT2

OUTPUT3

OUTPUT4

OUTPUT5

OUTPUT6

OUTPUT7

OUTPUT8

OUTPUT9

OUTPUT10

OUTPUT11

OUTPUT12

OUTPUT13

OUTPUT14

OUTPUT15

NCOUT

SDI

SDC

LATCHCLEAR

LATCHDATA

NCEN

LONGPULSE

SHORTPULSE

SELECTOR

4 to 13 LINES

DECODER

13 MOS

DRIVERS

CHANNEL A

HSA1

ENIC

S3

UPC/S2

RESC/S1

CLKC/S0

HSA2

HSA3

HSA4

HSA5

HSA6

HSA7

HSA8

HSA9

HSA10

HSA11

HSA12

HSA13

13 MOS

DRIVERS

CHANNEL B

HSB1

HSB2

HSB3

HSB4

HSB5

HSB6

HSB7

HSB8

HSB9

HSB10

HSB11

HSB12

HSB13

C0

C1

C2

C3

0 to 13
UP/DOWN
COUNTER

CHSEL

ENCH

D97IN524A

Block diagrams L6452

Figure 3. Block Diagram: Nozzle activation part

4/22

L6452 Pin description

1

2

3

5

6

4

7

8

9

10

361137 38 39 40 41

95 94 93 929091 89 88 87 86 85

70

69

68

66

65

67

75

74

73

71

72

OUTPUT13

OUTPUT14

POWGND

OUTPUT15

CRLATCH

V

C

OUTPUT10

V

C

OUTPUT11

V

C

OUTPUT12

RESET

CONVSTART

ADCK

NCOUT

ADDATA

CH0BUF

ANALOGND

ADCGND

V

a

VREF

CH5

RXA

RXB

REXT

CSGND

V

a

VDDVSTEP-UP

STEPUPBOOST

STEPUPGND

CLKC/S0

ENCH

HSA4

HSA5

HSA6

HSA8

HSA9

HSA7

ENIC

GND

HSA1

HSA3

HSA2

D97IN489C

96

VXA

97

VXB

98

ONENABLE

99

CRCLOCK

100

CRDATA

LATCHDATA

SDI

SDC

LONGPULSE

31 32 33 34 35

64

63

61

60

62

HSA10

HSA11

HSA13

V

r

HSA12

12

13

14

15

16

OUTPUT7

POWGND

OUTPUT8

OUTPUT9

V

C

17

18

19

20

V

C

OUTPUT5

OUTPUT6

V

C

21

22

23

24

25

OUTPUT1

OUTPUT2

V

C

OUTPUT4

OUTPUT3

59

57

56

58

HSB13

HSB11

HSB10

HSB12

HSB9

HSB8

HSB6

HSB5

HSB7

45 46 47 48 49

50

84 838182

CH4

CH3

CH1

CH2

RESC/S1

UPC/S2

CHSEL

S3

42 43 44

26

27

28

29

30

NCEN

LATCHCLEAR

OUTPUT0

V

C

POWGND

55

54

52

51

53

HSB4

HSB3

HSB1

GND

HSB2

80

79

78

76

77

2 Pin description

Figure 4. Pin connection (Top view)

Table 1. Pin function

Pin # Name Function

1 CRlatch

2, 5, 6, 8, 9,

11, 12, 14,
16, 18, 19,
21, 22, 24,

25, 28

Output15...0

A rising edge transfer the information from CR shift register into the
control register latching the data on the falling edge

High side DMOS outputs. To be active, ShortPulse and/or LongPulse
and NcEn must have a low level

5/22

Pin description L6452

Table 1. Pin function - continued

Pin # Name Function

3, 7, 10, 13,

17, 20, 23,

26

4, 15, 27,

51, 79, 92

29 LatchClear A high level resets all bit in the latch

30 NcEn

Vc

GND logic and power ground

Outputs Power Supply

A high level enables the internal current sources and disables all
DMOS outputs. To be active, the internal current sources must have
their corresponding bit set in the 16 bit latch and
set to low level. This function is called Nozzle Check Enable.

LongPulse must be

31 LatchData

32 SDI Serial data input of the shift register

33 SDC

34 LongPulse

35 ShortPulse

36 Reset A low level disables all functions and clears all registers

37 ConvStart A high level enables the A/D to start the new conversion

38 ADCK

39 NCOut

40 CH0buf Analog output signal (CH0 buffered)

41 ADDATA A/D serial data output

42 AnalogGND Analog ground connection

43 ADCGND Ground of internal ADC

A rising edge latches the 16 bit stored in the shift register in the 16 bit
latch

The data bit presented to the SDI pin is stored into the register on the
rising edge of this pin

A low level activates all outputs having their corresponding bit in the
16 bit latch set (this pin has an internal pull-up resistor)

A low level activates all outputs having their corresponding bit in the
16 bit latch reset (this pin has an internal pull-up resistor)

A/D clock signal; the ADDATA signal are valid on the falling edge of
this pin

If NcEn is high this output provides a high level when the open load is
detected on the output. If NcEn is low this output provides a high level
when a short circuit is detected on HSA/B output

44, 90 Va Power supply

45 Vref Reference voltage generator

46 to 50 CH5..CH1 A/D input signals

52 to 64 HSB1..HSB13 Head selector address output channel B

65 Vr Head Select Power Supply

66 to 78 HSA13..HSA1 Head selector address output channel A

Enable Internal Counter:

80 EnlC

6/22

A high level enables the counter and the internal decoder will activate
of the HSx outputs according to the counter’s outputs. Signal S0
becomes ClkC and S1 becomes ResC

L6452 Pin description

Table 1. Pin function - continued

Pin # Name Function

81 ChSel

82 S3 Decoder input signals when EnIC is low

83 UpC/S2

84 ResC/S1

85 EnCh

86 ClkC/S0

87 StepUpGND Ground of step up block

88 StepUpBoost Boost voltage

89 VstepUp Driving voltage of power DMOS stage

91 VDD 5V logic supply

93 Rext

Channel Select:
A low level enables channel A and a high level enables channel B

UpCount/S2:
A high level enables the internal counter to up counting. A low level

enables down counting depending on EnlC value it becomes S2.

Reset Count/S1:
A low level resets the internal counter depending on EnlC value it

becomes S1.

Enable Channel:
A low level enables the selected channel (this input has an internal

pull up resistor)

A high level clocks the internal counter depending on EnlC value it
becomes S0.

An external resistor connected to ground fixes the internal current
source value

94, 95 RxB, RxA Current source outputs

96, 97 VxA, VxB RxA, RxB voltage after an optional external filter

98 OnEnable

99 CRclock

100 CRdata Control register serial data input

A low level enables the current source generator according the A/B
and ON/

Data on pin CRdata are stored into the register on the rising edge of
this pin

OFF control register bit

7/22