ST L6452 User Manual

L6452

Dual 13x16 Matrix Head Ink Jet Driver

Features

■DRIVES TWO 13X16 MATRIX HEADS

■HEAD TEMPERATURE SENSING

■POWER UP SYSTEM

■ELECTRICAL NOZZLE CHECK

■8 BIT A/D

■5 BIT D/A

■± 4KV ESD PROTECTED OUTPUTS

Description

L6452 is a device designed to drive two 13x16 matrix ink jet print heads in printer applications.

The output stage is able to source simultaneously 400 mA on each of the 16 power lines (columns) with a duty cycle of 33% in normal printing and 66% in head pre-heating. On the address lines (rows), the load is only capacitive (MOS FET driving capability). The driver can control two print heads, but only one is active at a time. The address scanning counter is included and can be disabled to allow a different scanning scheme.

PQFP100

In order to avoid output activation during the supply transient, an internal power-up system is implemented.

As supporting function, L6452 is capable of sensing the head silicon temperature and to electrically check each nozzle.

The device is also integrating a thermal protection.

Order codes

Part number	Op. Temp range, ° C	Package	Packing
E-L6452	0 to 70	PQFP100	Tray
L6452DIE8	0 to 70	DIE	--

	Rev 2
February 2006	1/22
	www.st.com

Contents

L6452

Contents

1	Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
3	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	3.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	3.2	DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	3.3	Counter Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.4	Decoder Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
4	Print Head Temperature Control Part . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	4.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	4.2	Print Head Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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L6452

Block diagrams

1 Block diagrams

Figure 1. Block diagram

POWER &					16 POWER LINES
LOGICAL
SUPPLIES
					13 ADDRESS LINES
CONTROL			PRINT HEAD		CHANNEL A	PRINT HEAD
			DRIVER
LINES						A
					13 ADDRESS LINES
					CHANNEL B				PRINT HEAD
									B

A/D & PRINT HEAD	PRINT HEAD
TEMPERATURE	TEMPERATURE
CONTROL LINES	CONTROL
	ANALOG	D97IN523
	INPUTS
Figure 2. Block Diagram: Power Line Output Stage.
		Va
		1.25mA
DATA BIT 0
	1
	0
		OUTPUT0
DATA BIT 1
FROM 16 BIT
DATA LATCH
		OUTPUT1
DATA BIT 15
LONGPULSE		OUTPUT15
SHORTPULSE
		TRIGGER
NCEN		NCOUT
		D97IN525B
		3/22

Block diagrams

L6452

Figure 3. Block Diagram: Nozzle activation part

LONGPULSE
SHORTPULSE
				OUTPUT0
				OUTPUT1
				OUTPUT2
				OUTPUT3
				OUTPUT4
				OUTPUT5
	16 BIT SERIAL			OUTPUT6
			16 POWER	OUTPUT7
	INPUT &	16 BIT LATCH
			OUTPUT
	PARALLEL			OUTPUT8
			STAGES
	OUTPUT
				OUTPUT9
				OUTPUT10
				OUTPUT11
				OUTPUT12
				OUTPUT13
				OUTPUT14
				OUTPUT15
SDI
SDC
LATCHCLEAR
LATCHDATA
NCEN				NCOUT
				HSA1
				HSA2
				HSA3
				HSA4
				HSA5
			13 MOS	HSA6
			DRIVERS	HSA7
			CHANNEL A	HSA8
0 to 13				HSA9
UP/DOWN				HSA10
COUNTER		C0
				HSA11
		C1		HSA12
				HSA13
		4 to 13 LINES
	SELECTOR	DECODER
		C2
ENIC				HSB1
		C3		HSB2
S3				HSB3
UPC/S2				HSB4
RESC/S1				HSB5
CLKC/S0			13 MOS	HSB6
			DRIVERS	HSB7
			CHANNEL B	HSB8
				HSB9
				HSB10
CHSEL				HSB11
ENCH				HSB12
				HSB13
	D97IN524A
4/22

L6452

Pin description

2 Pin description

Figure 4. Pin connection (Top view)

											ONENABLE																																				VSTEP-UP				STEPUPBOOST				STEPUPGND
				CRDATA				CRCLOCK							VXB				VXA				RXA				RXB				REXT				CSGND				V				V																CLKC/S0				ENCH				RESC/S1				UPC/S2				S3				CHSEL
																																							DD				a
	100 99										98			97				96				95			94				93				92				91				90				89				88				87				86				85				84				83				82				81
CRLATCH		1
OUTPUT15		2
VC		3
POWGND		4
OUTPUT14		5
OUTPUT13		6
VC		7
OUTPUT12		8
OUTPUT11		9

VC 10

OUTPUT10 11

OUTPUT9 12

VC 13

OUTPUT8 14

POWGND 15

OUTPUT7 16

VC 17

OUTPUT6 18

OUTPUT5 19

VC 20

OUTPUT4 21

OUTPUT3 22

VC 23

OUTPUT2 24

OUTPUT1 25

VC 26

POWGND 27

OUTPUT0 28

LATCHCLEAR 29

NCEN 30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

LATCHDATA

SDI

SDC

LONGPULSE

SHORTPULSE

RESET

CONVSTART

ADCK

NCOUT

CH0BUF

ADDATA

ANALOGND

ADCGND

a

VREF

CH5

CH4

CH3

CH2

CH1

V

80				ENIC
79				GND
78				HSA1
77				HSA2
76				HSA3
75				HSA4
74				HSA5
73				HSA6
72				HSA7
71				HSA8
70				HSA9
69				HSA10
68				HSA11
67				HSA12
66				HSA13
65				Vr
64				HSB13
63				HSB12
62				HSB11
61				HSB10
60				HSB9
59				HSB8
58				HSB7
57				HSB6
56				HSB5
55				HSB4
54				HSB3
53				HSB2
52				HSB1
51				GND

D97IN489C

Table 1.	Pin function
Pin #		Name	Function
1		CRlatch	A rising edge transfer the information from CR shift register into the
			control register latching the data on the falling edge
2, 5, 6, 8, 9,
11, 12, 14,
			High side DMOS outputs. To be active, ShortPulse and/or LongPulse
16, 18, 19,		Output15...0
			and NcEn must have a low level
21, 22, 24,
25, 28

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	Pin description										L6452
		Table 1.	Pin function - continued
		Pin #			Name				Function
		3, 7, 10, 13,
		17, 20, 23,				Vc			Outputs Power Supply
		26
		4, 15, 27,				GND			logic and power ground
		51, 79, 92
		29			LatchClear				A high level resets all bit in the latch
									A high level enables the internal current sources and disables all
		30				NcEn			DMOS outputs. To be active, the internal current sources must have
									their corresponding bit set in the 16 bit latch and LongPulse must be
									set to low level. This function is called Nozzle Check Enable.
		31			LatchData				A rising edge latches the 16 bit stored in the shift register in the 16 bit
									latch
		32				SDI			Serial data input of the shift register
		33				SDC			The data bit presented to the SDI pin is stored into the register on the
									rising edge of this pin
									A low level activates all outputs having their corresponding bit in the
		34			LongPulse
									16 bit latch set (this pin has an internal pull-up resistor)
									A low level activates all outputs having their corresponding bit in the
		35			ShortPulse
									16 bit latch reset (this pin has an internal pull-up resistor)
		36							A low level disables all functions and clears all registers
						Reset
		37			ConvStart				A high level enables the A/D to start the new conversion
		38			ADCK				A/D clock signal; the ADDATA signal are valid on the falling edge of
									this pin
									If NcEn is high this output provides a high level when the open load is
		39			NCOut				detected on the output. If NcEn is low this output provides a high level
									when a short circuit is detected on HSA/B output
		40			CH0buf				Analog output signal (CH0 buffered)
		41			ADDATA				A/D serial data output
		42		AnalogGND					Analog ground connection
		43			ADCGND				Ground of internal ADC
		44, 90				Va			Power supply
		45				Vref			Reference voltage generator
		46 to 50			CH5..CH1				A/D input signals
		52 to 64		HSB1..HSB13					Head selector address output channel B
		65				Vr			Head Select Power Supply
		66 to 78		HSA13..HSA1					Head selector address output channel A
									Enable Internal Counter:
		80				EnlC			A high level enables the counter and the internal decoder will activate
									of the HSx outputs according to the counter’s outputs. Signal S0
									becomes ClkC and S1 becomes ResC

6/22

L6452

Pin description

Table 1.

Pin function - continued

Pin #

Name

Function

81

ChSel

Channel Select:

A low level enables channel A and a high level enables channel B

82

S3

Decoder input signals when EnIC is low

UpCount/S2:

83

UpC/S2

A high level enables the internal counter to up counting. A low level

enables down counting depending on EnlC value it becomes S2.

Reset Count/S1:

84

ResC/S1

A low level resets the internal counter depending on EnlC value it

becomes S1.

Enable Channel:

85

EnCh

A low level enables the selected channel (this input has an internal

pull up resistor)

86

ClkC/S0

A high level clocks the internal counter depending on EnlC value it

becomes S0.

87

StepUpGND

Ground of step up block

88

StepUpBoost

Boost voltage

89

VstepUp

Driving voltage of power DMOS stage

91

VDD

5V logic supply

93

Rext

An external resistor connected to ground fixes the internal current

source value

94, 95

RxB, RxA

Current source outputs

96, 97

VxA, VxB

RxA, RxB voltage after an optional external filter

A low level enables the current source generator according the

A/B

98

OnEnable

and ON/OFF control register bit

99

CRclock

Data on pin CRdata are stored into the register on the rising edge of

this pin

100

CRdata

Control register serial data input

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