ST L6393 User Manual

L6393

Half-bridge gate driver

Features

■High voltage rail up to 600 V

■dV/dt immunity ± 50 V/nsec in full temperature range

■Driver current capability:

–290 mA source,

–430 mA sink

■Switching times 75/35 nsec rise/fall with 1 nF load

■3.3 V, 5 V CMOS/TTL inputs comparators with hysteresis

■Integrated bootstrap diode

■Uncommitted comparator

■Adjustable dead-time

■Compact and simplified layout

■Bill of material reduction

■Flexible, easy and fast design

Application

■Motor driver for home appliances

■Factory automation

■Industrial drives and fans

■HID ballasts

■Power supply units

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Description

The L6393 is a high-voltage device manufactured with the BCD “OFF-LINE” technology. It is a single chip half-bridge gate driver for N-channel power MOSFET or IGBT.

The high side (floating) section is designed to stand a voltage rail up to 600 V.

The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP.

The IC embeds an uncommitted comparator available for protections against overcurrent, overtemperature, etc.

Table 1.	Device summary
	Order codes	Package	Packaging
	L6393N	DIP-14	Tube
	L6393D	SO-14
	L6393DTR		Tape and reel

August 2010

Doc ID 14497 Rev 4

1/19

www.st.com

Contents	L6393

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
3	Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
4	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	4.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	4.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	4.3	Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	5.1	AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	5.2	DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
6	Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
7	Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
8	Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	8.1	CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18

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L6393	Block diagram

1 Block diagram

Figure 1. Block diagram

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Doc ID 14497 Rev 4

3/19

Pin connection	L6393

2 Pin connection

Figure 2. Pin connection (top view)

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Table 2.

Pin description

Pin N#

Pin name

Type

Function

1

PHASE

I

Driver logic input (active high)

2

(1)

I

Shut down input (active low)

SD

3

I

Driver logic input (active low)

BRAKE

4

VCC

P

Lower section supply voltage

5

DT

I

Dead time setting

6

CPOUT

O

Comparator output (open drain)

7

GND

P

Ground

8

CP-

I

Comparator negative input

9

CP+

I

Comparator positive input

10

LVG (1)

O

Low side driver output

11

NC

Not connected

12

OUT

P

High side (floating) common voltage

13

HVG (1)

O

High side driver output

14

BOOT

P

Bootstrapped supply voltage

1.The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.

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L6393	Truth table

3 Truth table

Table 3.

Truth table

Inputs

Outputs

PHASE

LVG

HVG

SD

BRAKE

L

X

X

L

L

H

L

L

H

L

H

L

H

H

L

H

H

L

H

L

H

H

H

L

H

Note:

X: don’t care

In the L6393 IC the two input signals PHASE and

are fed into an AND logic port and

BRAKE

the resulting signal is in phase with the high side output HVG and in opposition of phase with

the low side output LVG. This means that if

BRAKE

is kept to high level, the PHASE signal

drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG

output. If

BRAKE

is set to low level the low side output LVG is always ON and the high side

output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides

the possibility to control the power stages using the PHASE signal to select the current

direction in the bridge and the

BRAKE

signal to perform current slow decay on the low sides.

From the point of view of the logic operations the two signals PHASE and

are

BRAKE

completely equivalent, that means the two signals can be exchanged without any change in

the behavior on the resulting output signals (see the Figure 1 on page 3).

Note:

The dead time between the turn OFF of one power switch and the turn ON of the other

power switch is defined by the resistor connected between DT pin and the ground.

Doc ID 14497 Rev 4

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Electrical data	L6393

4 Electrical data

4.1Absolute maximum ratings

	Table 4.	Absolute maximum ratings
	Symbol		Parameter		Value		Unit
				Min		max
	VCC		Supply voltage	-0.3		21	V
	VOUT		Output voltage	Vboot - 21		Vboot + 0.3	V
	Vboot		Bootstrap voltage	-0.3		620	V
	Vhvg		High side gate output voltage	VOUT - 0.3		Vboot + 0.3	V
	Vlvg		Low side gate output voltage	-0.3		VCC + 0.3	V
	Vcp+		Comparator positive input voltage	-0.3		VCC + 0.3	V
	Vcp-		Comparator negative input voltage	-0.3		VCC + 0.3	V
	Vi		Logic input voltage	-0.3		15	V
	Vod		Open drain voltage	-0.3		15	V
	dVOUT/dt		Allowed output slew rate			50	V/ns
	Ptot		Total power dissipation (TA = 25 °C)			800	mW
	TJ		Junction temperature			150	°C
	TSTG		Storage temperature	-50		150	°C
Note:	ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (human body model)

4.2Thermal data

Table 5.	Thermal data
Symbol		Parameter	SO-14	DIP-14	Unit
Rth(JA)		Thermal resistance junction to ambient max.	165	100	°C/W

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