High-voltage high and low side driver
Features
■ High voltage rail up to 600 V
■ dV/dt immunity ± 50 V/nsec in full temperature
range
■ Driver current capability:
– 290 mA source,
– 430 mA sink
■ Switching times 75/35 nsec rise/fall with 1 nF
load
■ 3.3 V, 5 V TTL/CMOS inputs with hysteresis
■ Integrated bootstrap diode
■ Comparator for fault protections
■ Smart shut-down function
■ Adjustable dead-time
■ Interlocking function
■ Compact and simplified layout
■ Bill of material reduction
■ Effective fault protection
■ Flexible, easy and fast design
L6391
Description
The L6391 is a high-voltage device manufactured
with the BCD “OFF-LINE” technology. It is a single
chip half-bridge gate driver for N-channel power
MOSFET or IGBT.
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
An integrated comparator is available for
protections against overcurrent, overtemperature,
etc.
Applications
■ Motor driver for home appliances, factory
automation, industrial drives and fans.
■ HID ballasts, power supply units.
Table 1. Device summary
Order codes Package Packaging
L6391N DIP-14 Tube
L6391D SO-14 Tube
L6391DTR SO-14 Tape and reel
December 2010 Doc ID 17892 Rev 1 1/21
www.st.com
21
Contents L6391
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21 Doc ID 17892 Rev 1
L6391 Block diagram
1 Block diagram
Figure 1. Block diagram
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Doc ID 17892 Rev 1 3/21
Pin connection L6391
2 Pin connection
Figure 2. Pin connection (top view)
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Table 2. Pin description
Pin n # Pin name Type Function
1 LIN
2 SD/OD
3 HIN I High side driver logic input (active high)
4 VCC P Lower section supply voltage
5 DT I Dead time setting
6 NC Not connected
7 GND P Ground
8 CP- I Comparator negative input
I Low side driver logic input (active low)
(1)
I/O
Shut down logic input (active low)/open drain
comparator output
!-V
9 CP+ I Comparator positive input
10 LVG
(1)
O Low side driver output
11 NC Not connected
12 OUT P High side (floating) common voltage
(1)
13 HVG
O High side driver output
14 BOOT P Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/21 Doc ID 17892 Rev 1
L6391 Truth table
3 Truth table
Table 3. Truth table
Input Output
SD
LXXLL
HHLL L
HLHLL
HLLHL
HHHL H
Note: X: don't care
LIN HIN LVG HVG
Doc ID 17892 Rev 1 5/21
Electrical data L6391
4 Electrical data
4.1 Absolute maximum ratings
Table 4. Absolute maximum rating
Val ue
Symbol Parameter
Min Max
Vcc Supply voltage -0.3 21 V
Output voltage V
out
Bootstrap voltage -0.3 620 V
boot
High side gate output voltage V
hvg
Low side gate output voltage -0.3 Vcc + 0.3 V
lvg
Comparator negative input voltage -0.3 Vcc + 0.3 V
cp-
Comparator positive input voltage -0.3 Vcc + 0.3 V
cp+
V
Logic input voltage -0.3 15 V
i
Open drain voltage -0.3 15 V
OD
/dt Allowed output slew rate 50 V/ns
Total power dissipation (TA = 25 °C) 800 mW
tot
Junction temperature 150 °C
J
Storage temperature -50 150 °C
stg
dV
V
V
V
V
V
V
V
out
P
T
T
- 21 V
boot
- 0.3 V
out
+ 0.3 V
boot
+ 0.3 V
boot
Unit
Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (human body model)
4.2 Thermal data
Table 5. Thermal data
Symbol Parameter SO-14 DIP-14 Unit
R
th(JA)
Thermal resistance junction to ambient 165 100 °C/W
6/21 Doc ID 17892 Rev 1
L6391 Electrical data
4.3 Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Pin Parameter Test condition Min Max Unit
V
cc
(1)
V
BO
V
out
V
CP-
V
CP+
f
sw
T
J
1. VBO = V
2. LVG off. Vcc = 12.5 V
Logic is operational if V
3. At least one of the comparator's input must be lower than 2.5 V to guarantee proper operation.
4 Supply voltage 12.5 20 V
14-12 Floating supply voltage 12.4 20 V
12 DC output voltage - 9
Comparator negative
8
input voltage
Comparator positive
9
input voltage
[ 2.5 V V
V
CP+
V
[ 2.5 V V
CP-
(2)
Switching frequency HVG, LVG load CL = 1 nF 800 kHz
Junction temperature -40 125 °C
- V
boot
out
> 5 V
boot
580 V
(3)
CC
(3)
CC
V
V
Doc ID 17892 Rev 1 7/21
Electrical characteristics L6391
5 Electrical characteristics
5.1 AC operation
Table 7. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
ton
t
off
t
sd
t
isd
MT
1 vs 10
3 vs 13
10, 13
High/low side driver turn-on
propagation delay
High/low side driver turn-off
propagation delay
2 vs
Shutdown to high/low side
driver propagation delay
Comparator triggering to
high/low side driver turn-off
propagation delay
Delay matching, HS and LS
turn-on/off
= 0 V
V
out
V
= Vcc
boot
= 1 nF
C
L
= 0 to 3.3 V
V
i
See Figure 3.
Measured applying a voltage step from 0
V to 3.3 V to pin CP+; CP-=0.5 V
50 125 200 ns
50 125 200 ns
50 125 200 ns
200 250 ns
30 ns
RDT = 0Ω, CL = 1 nF 0.1 0.18 0.25 µs
= 37kΩ, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 µs
R
DT
(2)
(1)
= 136kΩ, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 µs
R
DT
R
= 260kΩ, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 µs
DT
= 0Ω, CL = 1 nF 80 ns
R
DT
= 37kΩ, CL = 1 nF, CDT = 100 nF 120 ns
R
DT
R
= 136kΩ, CL = 1 nF, CDT = 100 nF 250 ns
DT
= 260kΩ, CL = 1 nF, CDT = 100 nF 400 ns
R
DT
= 1 nF 75 120 ns
L
DT 5 Dead time setting range
MDT Matching dead time
t
r
t
1. See Figure 4 on page 9
2. MDT = | DT
10,13
f
Rise time C
Fall time CL = 1 nF 35 70 ns
- DTHL | see Figure 5 on page 12
LH
8/21 Doc ID 17892 Rev 1
L6391 Electrical characteristics
Figure 3. Timing
LIN
LVG
HIN
HVG
50%
50%
50%
tr tf
90%
10%
ton toff
50%
tr tf
90%
10%
ton toff
90%
10%
90%
10%
SD
50%
tf
90%
LVG/HVG
tsd
Figure 4. Typical dead time vs. DT resistor value
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Doc ID 17892 Rev 1 9/21
Electrical characteristics L6391
5.2 DC operation
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
V
cc_hys
V
cc_thON
V
cc_thOFF
I
qccu
I
qcc
4
UV hysteresis 1.2 1.5 1.8 V
V
cc
Vcc UV turn ON threshold 11.5 12 12.5 V
Vcc UV turn OFF threshold 10 10.5 11 V
Undervoltage quiescent
supply current
Quiescent current
Bootstrapped supply voltage section
V
BO_hys
V
BO_thON
V
BO_thOFF
I
QBOU
I
QBO
V
V
14-12
UV hysteresis 1.2 1.5 1.8 V
V
BO
UV turn ON threshold 10.6 11.5 12.4 V
BO
UV turn OFF threshold 9.1 10 10.9 V
BO
Undervoltage VBO quiescent
current
VBO quiescent current
(1)
V
= 9.5 V
cc
SD = 5 V; LIN = 5 V;
HIN = GND;
= 0 Ω;
R
DT
CP+=GND; CP-=5 V
Vcc = 15 V
= 5 V; LIN = 5 V;
SD
HIN = GND;
= 0 Ω;
R
DT
CP+=GND; CP-=5 V
= 9 V
V
BO
= 5 V; LIN and
SD
HIN = 5 V;
= 0 Ω;
R
DT
CP+=GND; CP-=5 V
V
= 15 V
BO
= 5 V; LIN and
SD
HIN = 5 V;
= 0 Ω;
R
DT
CP+=GND; CP-=5 V
100 150 μA
500 1000 μA
70 110 μA
200 μA
I
R
DS(on)
LK
High voltage leakage current V
Bootstrap driver on
resistance
(2)
= V
out
= V
hvg
LVG ON 120 Ω
Driving buffers section
I
so
I
si
High/low side source short
circuit current
10,
13
High/low side sink short
circuit current
= V
V
IN
= V
V
IN
< 10 μs) 200 290 mA
ih (tp
< 10 μs) 250 430 mA
il (tp
10/21 Doc ID 17892 Rev 1
= 600 V 10 μA
boot
L6391 Electrical characteristics
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)
Symbol Pin Parameter Test condition Min Typ Max Unit
Logic inputs
V
V
I
HINh
V
il_S
il
1, 2, 3
ih
Low logic level voltage 0.8 V
High logic level voltage 2.25 V
1, 3
Single input voltage
HIN logic “1” input bias
current
LIN and HIN connected
together and floating
HIN = 15 V 110 175 260 μA
3
I
HINl
I
LINl
HIN logic “0” input bias
current
LIN
logic “0” input bias
current
HIN = 0 V 1 μA
LIN
= 0 V 3 6 20 μA
1
I
LINh
I
SDh
LIN logic “1” input bias
current
SD
logic “1” input bias
current
= 15 V 1 μA
LIN
= 15 V 10 40 100 μA
SD
2
I
SDl
1. V
BO = Vboot
2. R
DSON
R
DSON
where I1 is pin 14 current when V
- V
is tested in the following way:
= [(VCC - V
SD logic “0” input bias
current
out
) - (VCC - V
CBOOT1
CBOOT2
CBOOT
)] / [I1(VCC,V
= V
CBOOT1, I2
= 0 V 1 μA
SD
) - I2(VCC,V
CBOOT1
when V
CBOOT
Table 9. Sense comparator (VCC = 15 V, TJ = +25 °C)
= V
CBOOT2
CBOOT2
0.8 V
)]
.
Symbol Pin Parameter Test conditions Min Typ Max Unit
V
io
I
ib
V
ol
t
d_comp
8, 9 Input offset voltage -15 15 mV
8, 9 Input bias current V
Open drain low level output
2
voltage
Comparator delay
= 1 V, V
CP+
= - 3 mA VCP+=1V;
I
od
= 0.5 V 1 μA
CP-
VCP-=0.5V;
=100 kΩ to 5 V on
R
pull
SD
/OD pin; VCP-=0.5V;
voltage step on CP+ = 0 ÷
0.5 V
90 130 ns
3.3V,
SR 2 Slew rate C
= 180 pF; Rpu = 5 kΩ 60 V/μs
L
Doc ID 17892 Rev 1 11/21
Waveforms definitions L6391
6 Waveforms definitions
Figure 5. Dead time and interlocking waveforms definitions
LIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
LVG
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
LVG
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
LVG
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
DTLH
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DTLH
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
DTHL
DTHL
(*) HIN and LIN can be connected togheter and driven by just one control signal
12/21 Doc ID 17892 Rev 1
L6391 Smart shut down function
7 Smart shut down function
L6391 integrates a comparator committed to the fault sensing function. The comparator
input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function.
The output signal of the comparator is fed to an integrated MOSFET with the open drain
output available on pin 2, shared with the SD
device is set in shut down state and both its outputs are set to low level leaving the halfbridge in tri-state.
Figure 6. Smart shut down timing waveforms
CP-
CP+
input. When the comparator triggers, the
PROTECTION
HIN/LIN
HVG/LVG
SD/OD
upper
threshold
lower
threshold
open drain gate
(internal)
the driver outputs are set in SD state
immediately after the comparator
triggering even if the SD signal
Fast shut down:
has not yet reach
the lower input threshold
FROM/TO
CONTROLLER
1
real disable time
SHUT DOWN CIRCUIT
V
BIAS
SD
R
SD/OD
SD
C
2
TIME CONSTANTS
ON_OD
R
1
2
ON_OD
= (R
= R
SDCSD
SMART
LOGIC
// RSD)
SD
SD
C
Doc ID 17892 Rev 1 13/21
Smart shut down function L6391
In common over-current protection architectures the comparator output is usually connected
to the SD
input and an RC network is connected to this SD/OD line in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Differently from the common fault detection systems, L6391 Smart shut down architecture
allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the
propagation delay between the fault detection event and the actual outputs switch-off. In fact
the time delay between the fault and the outputs turn off is no more dependent on the RC
value of the external network connected to the pin. In the smart shut down circuitry, the fault
signal has a preferential path which directly switches off the outputs after the comparator
triggering. At the same time the internal logic turns on the open drain output and holds it on
until the SD
voltage goes below the SD logic input lower threshold. The Smart shut down
system provides the possibility to increase the time constant of the external RC network
(that is the disable time after the fault event) up to very large values without increasing the
delay time of the protection. Any external signal provided to the SD
pin is not latched and
can be used as control signal in order to perform, for instance, PWM chopping through this
pin. In fact when a PWM signal is applied to the SD
input and the logic inputs of the gate
driver are stable, the outputs switch from the low level to the state defined by the logic inputs
and vice versa.
14/21 Doc ID 17892 Rev 1
L6391 Typical application diagram
8 Typical application diagram
Figure 7. Application diagram
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Doc ID 17892 Rev 1 15/21
Bootstrap driver L6391
9 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 8). In the L6391 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in
Figure 9. An internal charge pump (Figure 9) provides the DMOS driving voltage.
9.1 C
To choose the proper C
capacitor. This capacitor C
Equation 1
The ratio between the capacitors C
It has to be:
Equation 2
e.g.: if Q
300 mV.
If HVG has to be supplied for a long time, the C
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 μA, so if HVG T
to supply 1 μC to C
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
BOOT
selection and charging
value the external MOS can be seen as an equivalent
BOOT
is related to the MOS total gate charge:
EXT
C
EXT
and C
EXT
C
BOOT
is 30 nC and V
gate
. This charge on a 1 μF capacitor means a voltage drop of 1V.
EXT
is 10 V, C
gate
EXT
Q
gate
--------------=
V
gate
is proportional to the cyclical voltage loss.
BOOT
>>> C
EXT
is 3 nF. With C
selection has to take into account also
BOOT
= 100 nF the drop would be
BOOT
is 5 ms, C
ON
BOOT
has
This structure can work only if V
LVG is on. The charging time (T
is close to GND (or lower) and in the meanwhile the
OUT
) of the C
charge
BOOT
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
16/21 Doc ID 17892 Rev 1
is the time in which both conditions are
(typical value:
DSon
L6391 Bootstrap driver
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
Q
gate
V
drop
ch eargRdson
I
==
→
V
drop
------------------
T
ch earg
R
dson
where Q
bootstrap DMOS and T
is the gate charge of the external power MOS, R
gate
is the charging time of the bootstrap capacitor.
charge
is the on resistance of the
dson
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap
DMOS is about 1 V, if the T
is 5 μs. In fact:
charge
Equation 4
30nC
V
drop
V
has to be taken into account when the voltage drop on C
drop
-------------- -
5μs
120Ω 0.7V∼⋅=
is calculated: if this drop
BOOT
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 8. Bootstrap driver with high voltage fast recovery diode
D
BOOT
V
CC
HVG
LVG
BOOT
OUT
H.V.
C
BOOT
TO LOAD
Figure 9. Bootstrap driver with internal charge pump
V
CC
HVG
LVG
BOOT
H.V.
OUT
b
Doc ID 17892 Rev 1 17/21
C
BOOT
TO LOAD
Package mechanical data L6391
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 10. DIP-14 mechanical data
mm. inch
Dim.
Min Typ Max Min Typ Max
a1 0.51 0.020
B 1.39 1.65 0.055 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 15.24 0.600
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100
Figure 10. Package dimensions
18/21 Doc ID 17892 Rev 1
L6391 Package mechanical data
Table 11. SO-14 mechanical data
mm. inch
Dim.
Min Typ Max Min Typ Max
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S 8° (max.)
Figure 11. Package dimensions
Doc ID 17892 Rev 1 19/21
Revision history L6391
11 Revision history
Table 12. Document revision history
Date Revision Changes
14-Dec-2010 1 First release
20/21 Doc ID 17892 Rev 1
L6391
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Doc ID 17892 Rev 1 21/21
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