ST L6390 User Manual

L6390

High-voltage high/low-side driver

Features

■High-voltage rail up to 600 V

■dV/dt immunity ±50 V/nsec in full temperature range

■Driver current capability:

–290 mA source

–430 mA sink

■Switching times 75/35 nsec rise/fall with 1 nF load

■3.3 V, 5 V TTL/CMOS inputs with hysteresis

■Integrated bootstrap diode

■Operational amplifier for advanced current sensing

■Comparator for fault protection

■Smart shutdown function

■Adjustable deadtime

■Interlocking function

■Compact and simplified layout

■Bill of material reduction

■Effective fault protection

■Flexible, easy and fast design

Applications

■Motor driver for home appliances, factory automation, industrial drives

■HID ballasts, power supply units

Datasheet − production data

SO-16 DIP-16

Description

The L6390 is a high-voltage device manufactured with BCD™ “offline” technology. It is a single-chip half bridge gate driver for N-channel Power MOSFETs or IGBT.

The high-side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy microcontroller/DSP interfacing.

The IC embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control.

An integrated comparator is available for protection against overcurrent, overtemperature, etc.

Table 1.	Device summary
	Order code	Package		Packaging
	L6390N	DIP-16		Tube
	L6390D	SO-16		Tube
	L6390DTR	SO-16		Tape and reel
July 2012		Doc ID 14493	Rev 7	1/26

This is information on a product in full production.

www.st.com

Contents	L6390

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
3	Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
4	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	4.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	4.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	4.3	Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	5.1	AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	5.2	DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
6	Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
7	Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
8	Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
9	Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	9.1	CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
10	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25

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L6390	Block diagram

1 Block diagram

Figure 1.			Block diagram
	4		BOOTSTRAP DRIVER	FLOATING STRUCTURE			16
VCC							BOOT
			from LVG	UV
			UV
				DETECTION
		DETECTION				HVG
						DRIVER
	3			LEVEL		S	15
HIN						R	HVG
				SHIFTER
		5V	LOGIC
			SHOOT
			THROUGH				14
			PREVENTION
							OUT
LIN	1					VCC
							LVG
							DRIVER
	2						LVG
SD/OD			SD				11
			LATCH		5V
			SMART
	8		SD	COMPARATOR			10
GND					+
							CP+
					-		+
						VREF
DT	5		DEAD		VCC
			TIME
				OPAMP			9
	7				+		OP+
OPOUT
					-		OP-
							6

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Pin connection	L6390

2 Pin connection

Figure 2. Pin connection (top view)
						1			16			BOOT
			LIN
	SD/OD					2			15			HVG
		HIN							14			OUT
							3
	VCC						4		13			NC
			DT						12			NC
							5
		OP-							11			LVG
							6
OPOUT									10			CP+
							7
	GND								9			OP+
								8

Table 2.	Pin description
Pin n #	Pin name					Type	Function
1						I	Low-side driver logic input (active low)
			LIN
							Shutdown logic input (active low)/open drain
2		SD/OD (1)				I/O
							(comparator output)
3		HIN				I	High-side driver logic input (active high)
4		VCC				P	Lower section supply voltage
5			DT			I	Deadtime setting
6		OP-				I	Op amp inverting input
7		OPOUT				O	Op amp output
8		GND				P	Ground
9		OP+				I	Op amp non inverting input
10		CP+				I	Comparator input
11		LVG (1)				O	Low-side driver output
12, 13			NC				Not connected
14		OUT				P	High-side (floating) common voltage
15		HVG (1)				O	High-side driver output
16		BOOT				P	Bootstrap supply voltage

1.The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows the omission of the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.

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L6390	Truth table

3 Truth table

	Table 3.			Truth table
					Input					Output
								HIN	LVG		HVG
		SD				LIN
		L				X		X	L		L
		H				H		L	L		L
		H				L		H	L		L
		H				L		L	H		L
		H				H		H	L		H
Note:	X: don't care.

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Electrical data	L6390

4 Electrical data

4.1Absolute maximum ratings

	Table 4.	Absolute maximum ratings
	Symbol	Parameter		Value		Unit
			Min.		Max.
	Vcc	Supply voltage	- 0.3		21	V
	Vout	Output voltage	Vboot - 21		Vboot + 0.3	V
	Vboot	Bootstrap voltage	- 0.3		620	V
	Vhvg	High-side gate output voltage	Vout - 0.3		Vboot + 0.3	V
	Vlvg	Low-side gate output voltage	- 0.3		Vcc + 0.3	V
	Vop+	Op amp non-inverting input	- 0.3		Vcc + 0.3	V
	Vop-	Op amp inverting input	- 0.3		Vcc + 0.3	V
	Vcp+	Comparator input voltage	- 0.3		Vcc + 0.3	V
	Vi	Logic input voltage	- 0.3		15	V
	Vod	Open drain voltage	- 0.3		15	V
	dVout/dt	Allowed output slew rate			50	V/ns
	Ptot	Total power dissipation (TA = 25 °C)			800	mW
	TJ	Junction temperature			150	°C
	Tstg	Storage temperature	-50		150	°C
Note:	ESD immunity for pins 14, 15 and 16 is guaranteed up to 1 kV (human body model).

4.2Thermal data

Table 5.	Thermal data
Symbol	Parameter	SO-16	DIP-16	Unit
Rth(JA)	Thermal resistance junction-to-ambient	155	100	°C/W

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L6390	Electrical data

4.3Recommended operating conditions

Table 6.	Recommended operating conditions
Symbol	Pin	Parameter	Test condition	Min.	Max.	Unit
Vcc	4	Supply voltage		12.5	20	V
(1)	16-14	Floating supply voltage		12.4	20	V
VBO
V	14	DC output voltage		- 9 (2)	580	V
out
fsw		Switching frequency	HVG, LVG load CL = 1 nF		800	kHz
TJ		Junction temperature		-40	125	°C

1.VBO = Vboot - Vout.

2.LVG off. Vcc = 12.5 V. Logic is operational if Vboot > 5 V. Refer to AN2738 for more details.

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Electrical characteristics	L6390

5 Electrical characteristics

5.1AC operation

	Table 7.	AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
	Symbol	Pin	Parameter			Test condition	Min.	Typ.	Max.	Unit
	ton		High/low-side driver turn-on	V		= 0 V	50	125	200	ns
		1 vs. 11	propagation delay		out
		3 vs. 15		Vboot = Vcc
			High/low-side driver turn-off
	toff			CL = 1 nF			50	125	200	ns
			propagation delay
				Vi = 0 to 3.3 V
		2 vs.	Shutdown to high/low-side
	tsd			See Figure 3.			50	125	200	ns
		11, 15	driver propagation delay
			Comparator triggering to	Measured applying a voltage
	tisd		high/low-side driver turn-off				50	200	250	ns
				step from 0 V to 3.3 V to pin CP+.
			propagation delay
	MT		Delay matching, HS and LS						30	ns
			turn-on/off
				RDT = 0, CL = 1 nF			0.1	0.18	0.25	μs
				RDT = 37 kΩ, CL = 1 nF,			0.48	0.6	0.72	μs
				CDT = 100 nF
	DT	5	Deadtime setting range (1)	RDT = 136 kΩ, CL = 1 nF,			1.35	1.6	1.85	μs
				CDT = 100 nF
				RDT = 260 kΩ, CL = 1 nF,			2.6	3.0	3.4	μs
				CDT = 100 nF
				RDT = 0, CL = 1 nF					80	ns
				RDT = 37 kΩ, CL = 1 nF,					120	ns
				CDT = 100 nF
	MDT		Matching deadtime (2)	RDT = 136 kΩ, CL = 1 nF,					250	ns
				CDT = 100 nF
				RDT = 260 kΩ, CL = 1 nF,					400	ns
				CDT = 100 nF
	tr	11, 15	Rise time	CL = 1 nF				75	120	ns
	tf		Fall time	CL = 1 nF				35	70	ns

1.See Figure 4 on page 9.

2.MDT = | DTLH - DTHL | see Figure 5 on page 13.

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