ST L6387E User Manual

High-voltage high and low side driver
Features
High voltage rail up to 600 V
dV/dt immunity ±50 V/nsec in full temperature
range
– 400 mA source, – 650 mA sink
Switching times 50/30 nsec rise/fall with 1nF
load
CMOS/TTL Schmitt trigger inputs with
hysteresis and pull down
Internal bootstrap diode
Outputs in phase with inputs
Interlocking function
L6387E
DIP-8 SO-8
Description
The L6387E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The high side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.

Figure 1. Block diagram

V
HIN
LIN
BOOTSTRAP DRIVER
3
CC
2
1
UV
DETECTION
LOGIC
LEVEL
SHIFTER
R
S
LVG
DRIVER
V
CC
HVG
DRIVER
D00IN1135
Vboot
8
H.V.
HVG
7
OUT
6
LVG
5
GND
4
Cboot
TO LOAD
September 2008 Rev 2 1/15
www.st.com
15
Contents L6387E
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 C
selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BOOT
6 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
L6387E Electrical data

1 Electrical data

1.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit
V
V
V
V
V
dV
P
T
Output voltage -3 to V
out
Supply voltage - 0.3 to +18 V
cc
Floating supply voltage -1 to 618 V
boot
High side gate output voltage -1 to V
hvg
Low side gate output voltage -0.3 to Vcc +0.3 V
lvg
V
Logic input voltage -0.3 to Vcc +0.3 V
i
Allowed output slew rate 50 V/ns
out/dt
Total power dissipation (TJ = 85 °C) 750 mW
tot
Junction temperature 150 °C
T
j
Storage temperature -50 to 150 °C
s
boot
-18 V
V
boot
Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)

1.2 Thermal data

Table 2. Thermal data

Symbol Parameter SO-8 DIP-8 Unit
R
Thermal Resistance Junction to ambient 150 100 °C/W
th(JA)

1.3 Recommended operating conditions

Table 3. Recommended operating conditions

Symbol Pin Parameter Test condition Min Typ Max Unit
V
out
V
BS
f
sw
V
cc
T
1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V
2. VBS = V
6 Output voltage
(2)
8 Floating supply voltage
Switching frequency HVG,LVG load CL = 1nF 400 kHz
3 Supply voltage 17 V
J
Junction temperature -45 125 °C
- V
boot
out
3/15
(1)
(1)
17 V
580 V
Pin connection L6387E

2 Pin connection

Figure 2. Pin connection (Top view)

Table 4. Pin description

LIN
HIN
V
CC
GND
1
2
3
4 LVG
D97IN517A
V
8
7
6
5
boot
HVG
OUT
Pin Type Function
1 LIN I Low side driver logic input
2 HIN I High side driver logic input
3 V
Low voltage power supply
cc
4 GND Ground
5 LVG
(1)
O Low side driver output
6 VOUT O High side driver floating reference
7 HVG
8 V
1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low.
(1)
O High side driver output
Bootstrap supply voltage
boot
4/15
L6387E Electrical characteristics

3 Electrical characteristics

3.1 AC operation

Table 5. AC operation electrical characteristcs (VCC = 15V; TJ = 25°C)
Symbol Pin Parameter Test condition Min Typ Max Unit
1 vs 5
t
on
2 vs 7
1 vs 5
t
off
2 vs 7
t
r
t
f
High/low side driver turn-on propagation delay
High/low side driver turn-off propagation delay
5, 7 Rise time CL = 1000pF 50 ns
5, 7 Fall time CL = 1000pF 30 ns

3.2 DC operation

Table 6. DC operation electrical characteristcs (VCC = 15V; TJ = 25°C)
Symbol Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section
V
V
V
I
V
cc
ccth1
ccth2
cchys
qccu
Supply voltage 17 V
Vcc UV turn on threshold 5.5 6 6.5 V
Vcc UV turn off threshold 5 5.5 6 V
Vcc UV hysteresis 0.5 V
3
Undervoltage quiescent supply current
= 0V 110 ns
V
out
= 0V 105 ns
V
out
V
≤ 5V 150 220 µA
cc
Quiescent current Vcc = 15V 250 320 µA
Bootstrap driver on resistance
(1)
R
I
qcc
dson
Bootstrapped supply voltage section
V
I
QBS
I
BS
LK
Bootstrap supply voltage 17 V
VBS quiescent current HVG ON 100 µA
8
High voltage leakage current
High/low side driver
I
so
I
si
Source short circuit current V
5,7
Sink short circuit current VIN = Vil (tp < 10µs) 450 650 mA
Vcc 12.5V 125
= V
V
hvg
V
boot
= Vih (tp < 10µs) 300 400 mA
IN
out
= 600V
=
10 µA
5/15
Input logic L6387E
Table 6. DC operation electrical characteristcs (continued)(VCC = 15V; TJ = 25°C)
Symbol Pin Parameter Test condition Min Typ Max Unit
Logic inputs
V
il
V
ih
I
ih
I
il
1. R
DS(on)
is pin 8 current when V
where I
1
Low level logic threshold voltage
High level logic threshold
1,2
voltage
High level logic input current VIN = 15V 50 70 µA
Low level logic input current VIN = 0V 1 µA
is tested in the following way:

4 Input logic

L6387E Input Logic is VCC (17V) compatible. An interlocking features is offered (see truth table below) to avoid undesired simultaneous turn ON of both Power Switches driven.

Table 7. Input logic

HIN 0011
Input
LIN 0101
R
DSON
CBOOT
V
()V
CCVCBOOT1
------------------------------------------------------------------------------------------------------ -=
I
()I2VCC,V
1VCC,VCBOOT1
= V
CBOOT1
, I2 when V
CBOOT
()
CCVCBOOT2
()
= V
CBOOT2
CBOOT2
1.5 V
3.6 V
HVG 0010
Output
LVG 0100
6/15
L6387E Bootstrap driver

5 Bootstrap driver

A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 3 a). In the L6387E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in
Figure 3 b. An internal charge pump (Figure 3 b) provides the DMOS driving voltage. The
diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
5.1 C
To choose the proper C capacitor. This capacitor C
The ratio between the capacitors C It has to be:
e.g.: if Q 300mV.
If HVG has to be supplied for a long time, the C the leakage losses.
e.g.: HVG steady state consumption is lower than 200µA, so if HVG T to supply 1µC to C
The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current).
This structure can work only if V LVG is on. The charging time (T fulfilled and it has to be long enough to charge the capacitor.
BOOT
selection and charging
value the external MOS can be seen as an equivalent
BOOT
is related to the MOS total gate charge:
EXT
C
EXT
and C
EXT
C
is 30nC and V
gate
. This charge on a 1µF capacitor means a voltage drop of 1V.
EXT
is 10V, C
gate
EXT
is close to GND (or lower) and in the meanwhile the
OUT
) of the C
charge
Q
gate
-------------- -=
V
gate
is proportional to the cyclical voltage loss.
BOOT
>>>C
BOOT
EXT
is 3nF. With C
BOOT
is the time in which both conditions are
BOOT
= 100nF the drop would be
BOOT
selection has to take into account also
is 5ms, C
ON
BOOT
has
The bootstrap driver introduces a voltage drop due to the DMOS R
(typical value: 125
DSON
). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Q
gate
-------------------
T
ch earg
R
dson
is the on resistance of the
dson
where Q
is the gate charge of the external power MOS, R
gate
bootstrap DMOS, and T
==
V
dropIch eargRdsonVdrop
is the charging time of the bootstrap capacitor.
charge
7/15
Bootstrap driver L6387E
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the T
V
has to be taken into account when the voltage drop on C
drop
is 5µs. In fact:
charge
V
drop
30nC
-------------- -
5µs
1250.8V=
is calculated: if this drop
BOOT
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used.

Figure 3. Bootstrap driver

D
BOOT
V
S
HVG
LVG
V
V
BOOT
OUT
H.V.
C
BOOT
TO LOAD
a
V
V
BOOT
OUT
H.V.
C
BOOT
TO LOAD
V
S
HVG
LVG
b
8/15
D99IN1056
L6387E Typical characteristic

6 Typical characteristic

Figure 4. Typical rise and fall times vs
time
(nsec)
250
200
150
100
50
0
Figure 6. Turn on time vs temperature Figure 7. Turn Off time vs temperature
250
200
150
100
Ton (ns)
load capacitance
D99IN1054
Tr
Tf
0 1 2 3 4 5 C (nF)
For both high and low side buffers @25˚C Tamb
@ Vcc = 15V
Typ.
Figure 5. Quiescent current vs supply
voltage
Iq
(µA)
10
10
10
10
4
3
2
2 4 6 8 10 12 14 16 V
0
250
200
150
Typ.
100
Toff (ns)
@ Vcc = 15V
D99IN1055
(V)
S
50
0
-45 -25 0 25 50 75 100 125 Tj (°C)
Figure 8. Output source current vs
1000
current (mA)
temperature
@ Vcc = 15V
800
600
Typ.
400
200
0
-45 -25 0 25 50 75 100 125 Tj (°C)
50
0
-45 -25 0 25 50 75 100 125 Tj (°C)
Figure 9. Output sink current vs
temperature
1000
800
600
Typ.
400
current (mA)
200
0
-45 -25 0 25 50 75 100 125
@ Vcc = 15V
Tj (°C)
9/15
Package mechanical data L6387E

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
10/15
L6387E Package mechanical data

Figure 10. DIP-8 mechanical data and package dimensions

DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0.260
I 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
OUTLINE AND
MECHANICAL DATA
DIP-8
11/15
Package mechanical data L6387E

Figure 11. SO-8 mechanical data and package dimensions

DIM.
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
(1)
D
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
(2)
E1
e 1.270 0.0500
h 0.250 0.500 0.0098 0.0197
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
k0˚8˚0˚8˚
ccc 0.100 0.0039
Notes: 1. Dimensions D does not include mold flash,
2. Dimension “E1” does not include interlead flash
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
4.800 4.900 5.000 0.1890 0.1929 0.1969
3.800 3.900 4.000 0.1496 0.1535 0.1575
protrusions or gate burrs. Mold flash, po trusions or gate burrs shall not exceed 0.15m m in total (both side).
or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.
OUTLINE AND
MECHANICAL DATA
SO-8
12/15
0016023 D
L6387E Order codes

8 Order codes

Table 8. Order codes

Part number Package Packaging
L6387E DIP-8 Tube
L6387ED SO-8 Tube
L6387ED013TR SO-8 Tape and reel
13/15
Revision history L6387E

9 Revision history

Table 9. Document revision history

Date Revision Changes
11-Oct-2007 1 First release
19-Sep-2008 2 Minor text changes on Table 6
14/15
L6387E
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