ST L6360 User Manual

L6360

IO-Link communication master transceiver IC

Features

■Supply voltage from 18 to 32.5 V

■Programmable output stages: high-side, low-side or push-pull (< 2 Ω)

■Up to 500 mA L+ protected high-side driver

■Supports COM1, COM2 and COM3 mode

■Additional IEC61131-2 type-1 input

■Short-circuit and overcurrent output protection through current limitation and programmable cutoff current

■3.3 V / 5 V, 50 mA linear regulator

■5 mA IO-Link digital input

■Fast mode I2C for IC control, configuration and diagnostic

■Diagnostic dual LED sequence generator and driver

■5 V and 3.3 V compatible I/Os

■Overvoltage protection (> 36 V)

■Overtemperature protection

■ESD protection

■Miniaturized: VFQFPN-26L 3.5 x 5 x 1 mm package

Applications

■Industrial sensors

■Factory automation

■Process control

Description

The L6360 is a monolithic IO-Link master port compliant with PHY2 (3 wires) supporting COM1 (4.8 kbaud), COM2 (38.4 kbaud) and COM3 (230.4 kbaud) modes.

The C/QO output stage is programmable: highside, low-side or push-pull; also cutoff current,

Datasheet −production data

VFQFPN-26L 3.5 x 5 x 1 mm

cutoff current delay time, and restart delay are programmable.

Cutoff current and cutoff current delay time, combined with thermal shutdown and automatic restart protect the device against overload and short-circuit.

C/QO and L+ output stages are able to drive resistive, inductive and capacitive loads. Inductive loads up to 10 mJ can be driven.

Supply voltage is monitored and low voltage conditions are detected.

The L6360 transfers, through the PHY2(C/QO pin), data received from a host microcontroller through the USART (IN C/QO pin), or to the USART (OUT C/QI pin) data received from PHY2 (C/QI pin).

To enable full IC control, configuration and monitoring (i.e. fault conditions stored in the status register), the communication between the system microcontroller and the L6360 is based on a Fast mode 2-wire I2C.

The L6360 has nine registers to manage the programmable parameters and the status of the IC.

Monitored fault conditions are: L+ line, overtemperature, C/Q overload, linear regulator undervoltage, and parity check.

Internal LED driver circuitries, in open drain configuration, provide two programmable sequences to drive two LEDs.

March 2012

Doc ID 022817 Rev 2

1/65

This is information on a product in full production.

www.st.com

Contents	L6360

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
2	Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
3	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
4	Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . .	11
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
6	Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	6.1 I²C single master bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18

6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.4 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.5 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.7 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.8 I2C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.9 Internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.10 Startup default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.3 Demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3.1 Fast demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.2 Slow demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

	6.4 I2C protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
	6.4.1	Protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	6.4.2	Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
7	Physical layer communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		53

7.1 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2 IEC 61131-2 type 1 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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L6360 Contents

8	Diagnostic LED sequence generator and driver . . . . . . . . . . . . . . . . .		55
9	Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
10	Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		57
11	EMC protection considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		58
	11.1	Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
	11.2	I/O lines protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
12	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		63
13	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		64

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Contents	L6360

List of tables

Table 1.	Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Table 2.	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Table 3.	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Table 4.	Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Table 5.	Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Table 6.	Electrical characteristics - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Table 7.	Electrical characteristics - linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Table 8.	Electrical characteristics - logic inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Table 9.	Electrical characteristics - LED driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Table 10.	Electrical characteristics - I2C (Fast mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Table 11.	Main parameters typical variation vs. +/- 1% variation of Rbias value . . . . . . . . . . . . . . . . .	17
Table 12.	Register addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Table 13.	ENCGQ: C/Q pull-down enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Table 14.	ICOQ: C/QO HS and LS cutoff current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Table 15.	tdcoq: C/QO HS and LS cutoff current delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Table 16.	trcoq: C/QO restart delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Table 17.	tdbq: C/QI de-bounce time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Table 18.	ENCGI: I/Q pull-down enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Table 19.	CQPDG: C/Q pull-down generator switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Table 20.	L+COD: L+ cutoff disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Table 21.	tdcol: L+ HS cutoff current delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Table 22.	trcol: L+ restart delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Table 23.	tdbi: I/Q de-bounce time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Table 24.	C/Q output stage configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Table 25.	Parameters default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Table 26.	Registers default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Table 27.	Current Write mode direction bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Table 28.	Sequential Write mode direction bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
Table 29.	Read mode: register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Table 30.	Address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
Table 31.	Linear regulator selection pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Table 32.	Supply voltage protection component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Table 33.	Refined supply voltage protection component description . . . . . . . . . . . . . . . . . . . . . . . . .	59
Table 34.	VH protection component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Table 35.	Typical protection in IO-Link applications component description . . . . . . . . . . . . . . . . . . .	61
Table 36.	IO-Link and SIO applications extended protection component description . . . . . . . . . . . .	62
Table 37.	Mechanical data for VFQFPN - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch . . . . . . . . . . . . . . . . .	63
Table 38.	Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64

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L6360	List of figures

List of figures

Figure 1.	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 2.	Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Figure 3.	Rise/fall time test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 4.	Normalized rise and fall time vs. output capacitor value (typ. values in push-pull
	configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 5.	A master transmitter addressing a slave receiver with a 7-bit address
	(the transfer is not changed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 6.	A master reads data from the slave immediately after the first byte . . . . . . . . . . . . . . . . . .	19
Figure 7.	Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 8.	I2C communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 9.	Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 10.	Power-on bit behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 11.	Overtemperature (OVT) bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 12.	Cutoff behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 13.	Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 14.	Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 15.	Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 16.	LED1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 17.	LED2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 18.	Parity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 19.	Power stage. Q2 is not present on L+ output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
Figure 20.	Fast demagnetization principle schematic. Load connected to L- . . . . . . . . . . . . . . . . . . .	38
Figure 21.	Fast demagnetization waveform. Load connected to L- . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 22.	Slow demagnetization schematic block. Load connected to L- . . . . . . . . . . . . . . . . . . . . .	39
Figure 23.	Slow demagnetization waveform. Load connected to GND . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 24.	Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 25.	Current Write mode flow chart procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 26.	Current Write mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 27.	Sequential Write mode flow chart procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 28.	Sequential Write mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
Figure 29.	Microcontroller parity check calculus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
Figure 30.	Register sequence in sequential Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Figure 31.	Current Read mode flow chart procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 32.	Current Read mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 33.	Current read communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 34.	Sequential/random Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 35.	Sequential/random read communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
Figure 36.	Block diagram communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Figure 37.	System communication mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Figure 38.	C/Q or L+ channel cutoff protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
Figure 39.	C/Q or L+ channel current limitation and cutoff protection with latched restart . . . . . . . . .	54
Figure 40.	LED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 41.	Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 42.	Linear regulator principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 43.	Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Figure 44.	Supply voltage protection with uni-directional Transil. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 45.	Refined supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
Figure 46.	VH protection vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60

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List of figures	L6360

Figure 47. Typical protection in IO-Link applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 48. IO-Link and SIO applications extended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 49. Package outline for VFQFPN - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch . . . . . . . . . . . . . . . . . . 63

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L6360	Block diagram

1 Block diagram

Figure 1. Block diagram

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Table 1.	Device summary
Order code			Package	Packaging
	L6360		VFQFPN 3.5 x 5 x 1 - 26 leads	Tray
	L6360TR		VFQFPN 3.5 x 5 x 1 - 26 leads	Tape and reel

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Pin connections	L6360

2 Pin connections

Figure 2. Pin connections (top view)

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6##

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,

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Table 2.

Pin description

Pin

Name

Description

Type

1

VCC

IC power supply

Supply

2

L-

L- line (IC ground)

Supply

3

VH

Linear regulator supply voltage

Supply

4

VDD

Linear regulator output voltage

Output

5

SA1

Serial address 1

Input

6

SA2

Serial address 2

Input

7

Rbias

External resistor for internal reference generation

Input

8

SEL

Linear regulator 3.3 V/5 V voltage selection. Output is 5 V

Input

when SEL pin is pulled to GND.

9

ENC/Q

C/Q output enable

Input

10

INC/Q

C/Q channel logic input

Input

11

OUTC/Q

C/Q channel logic output

Output

12

OUTI/Q

I/Q channel logic output

Output

8/65	Doc ID 022817 Rev 2

L6360				Pin connections
	Table 2.	Pin description (continued)
	Pin	Name	Description		Type
	13	ENL+	L+ switch enable. When ENL+ is high the switch is closed		Input
	14	IRQ	Interrupt request signal (open drain)		Output
	15	SCL	Serial clock line		Input
	16	SDA	Serial data line		Input/output
	17	RST	Reset - active low		Input
	18	SA0	Serial address 0		Input
	19	LED1	Status/diagnostic LED (open drain)		Output
	20	LED2	Status/diagnostic LED (open drain)		Output
	21	L-	L- line (IC ground)		Supply
	22	VCC	IC power supply		Supply
	23	L+	L+ line		Supply
	24	I/Q	I/Q channel line		Input
	25	C/QI	Transceiver (C/Q channel) line		Input
	26	C/QO	Transceiver (C/Q channel) line		Output

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Absolute maximum ratings	L6360

3 Absolute maximum ratings

Table 3.	Absolute maximum ratings
Symbol		Parameter	Value			Unit
VCC		Supply voltage	VCLAMP			V
VSEL		Linear regulator selection pin voltage	-0.3 to 4			V
VDD		Linear regulator output voltage	5.5			V
VH		Linear regulator input voltage	VCC			V
VINC/Q, ENC/Q, ENL+		INC/Q, ENC/Q, ENL+ voltage	-0.3 to VDD + 0.3			V
V ,	, , ,	I2C voltage	-0.3 to V	DD	+ 0.3	V
SDA SCL	SA0 1 2
VLED1, 2		LED1, 2 voltage	-0.3 to VDD + 0.3			V
VC/QI, VI/Q		C/QI, I/Q voltage	-0.3 to VCC + 0.3			V
VRST		Reset voltage	-0.3 to VDD + 0.3			V
VIRQ		IRQ voltage	-0.3 to VDD + 0.3			V
VRbias		External precision resistance voltage	-0.3 to 4			V
VESD		Electrostatic discharge (human body model)	2000			V
ICLAMP		Current through VCLAMP in surge test (1 kV, 500 Ω) condition	2			A
IC/QO, IL+		C/QO, L+ current (continuous)	Internally limited			A
IOUTC//Q, IOUTI/Q		OUTC/Q, OUTI/Q output current	± 5			mA
ISDA		I2C transmission data current (open drain pin)	10			mA
IIRQ		Interrupt request signal current	10			mA
ILED1, 2		LED1, 2 current	10			mA
Eload		L+ demagnetization energy	10			mJ
PTOT		Power dissipation at TC = 25 °C	Internally limited			W
PLR		Linear regulator power dissipation	200			mW
TJ		Junction operating temperature	Internally limited			°C
TSTG		Storage temperature	-55 to 150			°C

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L6360	Recommended operating conditions

4 Recommended operating conditions

Table 4.	Recommended operating conditions
Symbol	Parameter		Test condition	Min.		Typ.	Max.		Unit
VCC	Supply voltage			18			32.5		V
VH	Linear regulator input voltage			7			VCC		V
fSCL	SCL clock frequency		-				400		kHz
Rbias	Precision resistance			-0.1%		124	0.1%		kΩ
TJ	Junction temperature			-25			125		°C
Table 5.	Thermal data
Symbol	Parameter			Typ.			Unit
Rth j-case	Thermal resistance, junction-to-case			6			°C/W
Rth j-amb	Thermal resistance, junction-to-ambient(1)			50			°C/W

1. Mounted on FR4 PCB with 2 signal Cu layers and 2 power Cu layers interconnected through vias.

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Electrical characteristics	L6360

5 Electrical characteristics

(18 V < VCC < 30 V; -25 °C < TJ < 125 °C; VDD = 5 V; unless otherwise specified.)

Table 6.	xxx
	Electrical characteristics - power section
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
VCLAMP	Voltage clamp	I = 5 mA	36			V
VUV	Undervoltage ON-threshold		16	17	18	V
VUVH	Undervoltage hysteresis		0.3	1		V
VREGLN5H	Linear regulator undervoltage high	SEL = L	4.3		4.7	V
	threshold
VREGLN5L	Linear regulator undervoltage low	SEL = L	3.6		4.2	V
	threshold
VREG5HYS	Linear regulator undervoltage	SEL = L	0.1			V
	hysteresis
VREGLN33H	Linear regulator undervoltage high	SEL = H	2.8		3.1	V
	threshold
VREGLN33L	Linear regulator undervoltage low	SEL = H	2.5		2.7	V
	threshold
VREG33HYS	Linear regulator undervoltage	SEL = H	0.1			V
	hysteresis
VQTHH	C/QI and I/Q upper voltage threshold		10.5		12.9	V
VQTHL	C/QI and I/Q lower voltage threshold		8		11.4	V
VQHY	C/Q and I/Q hysteresis voltage		1			V
Vdemag	L+ demagnetization voltage	I = 5 mA	-8.5	-6.5	-4.8	V
VfHS	C/Q high-side freewheeling diode	I = 10 mA		0.5		V
	forward voltage
VfLS	C/Q low-side freewheeling diode	I = 10 mA		0.5		V
	forward voltage
VLTHOFF	L+ line diagnostic lower threshold		9	10	11	V
VLTHY	L+ line diagnostic hysteresis		0.1	1		V
VLTHON	L+ line diagnostic upper threshold		10	11	12	V
IS	Supply current	OFF-state		100		µA
		ON-state VCC at 32.5 V		4		mA
IOFFCQ	OFF-state C/QO current	ENC/Q = 0, VC/Q = 0 V			1	µA
			70	115	190	mA
ICOQ	C/QO lowand high-side cutoff current	Programmable	150	220	300	mA
		(see Control register 1)	290	350	440	mA
			430	580	720	mA

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Doc ID 022817 Rev 2

L6360			Electrical characteristics
Table 6.	Electrical characteristics - power section (continued)
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
ILIMQ	C/QO lowand high-side limitation		500		1600	mA
	current
IOFFL	L+ OFF-state current	ENL+ = 0,	0		200	µA
		VL+ = 0 V
ICOL	L+ cutoff current		480	580	730	mA
ILIML	L+ limitation current		500		1600	mA
IINC/Qi	C/QI pull-down current	Programmable (see section	5		6.5	mA
		Control register 2)	2		3.3	mA
IINI/Q	I/Q pull-down current	(see Control register 2)	2		3	mA
RONL	L+ high-side ON-state resistance	IOUT = 0.2 A at TJ = 25 °C		1		Ω
		IOUT = 0.2 A at TJ = 125 °C			2	Ω
RONCQH	C/QO high-side ON-state resistance	IOUT = 0.2 A at TJ = 25 °C		1		Ω
		IOUT = 0.2 A at TJ = 125 °C			2	Ω
RONCQL	C/QO low-side ON-state resistance	IOUT = 0.2 A at TJ = 25 °C		0.6		Ω
		IOUT = 0.2 A at TJ = 125 °C			1.2	Ω
tdINC/Q	INC/Q to C/QO propagation delay time	Push-pull (CQO rising edge)		140		ns
		Push-pull (CQO falling edge)		160		ns
tENC/Q	ENC/Q to C/QO propagation delay time	Push-pull (CQO rising edge)		110		ns
		Push-pull (CQO falling edge)		225		ns
trPP	C/Q rise time in push-pull	10% to 90%. See Figure 3	250		860	ns
	configuration
tfPP	C/Q fall time in push-pull configuration	10% to 90%. See Figure 3	290		860	ns
trHS	C/Q rise time in high-side			410		ns
	configuration
tfHS	C/Q fall time in high-side configuration			700		ns
trLS	C/Q rise time in low-side configuration			750		ns
tfLS	C/Q fall time in low-side configuration			530		ns
tENL	ENL to L+ propagation delay time			1		µs
trL+	L+ rise time			3		µs
tfL+	L+ fall time			25		µs
	C/QI to OUTC/Q (falling) propagation			40		ns
tdC/Qi	delay time
	C/QI to OUTC/Q (rising) propagation			100		ns
	delay time
	I/Q to OUTI/Q (falling) propagation			40		ns
tdI/Q	delay time
	I/Q to OUTI/Q (rising) propagation			100		ns
	delay time

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Electrical characteristics						L6360
Table 6.	Electrical characteristics - power section (continued)
Symbol	Parameter	Test condition	Min.	Typ.		Max.	Unit
				100			µs
tdcoq	C/QO lowand high-side cutoff current	Programmable		150			µs
	delay time	(see Control register 1)		200			µs
				250			µs
trcoq	C/QO restart delay time	Programmable		255 × tdcoq
		(see Control register 1)		Latched(1)
				0			µs
tdbq	C/QI de-bounce time	Programmable		5			µs
		(see Control register 1)		20			µs
				100			µs
				0			µs
tdbl	I/Q de-bounce time	Programmable		5			µs
		(see Control register 2)		20			µs
				100			µs
tdcol	L+ cutoff current delay time	Programmable		500			µs
		(see Control register 2)		0			µs
trcol	L+ restart delay time	Programmable		64			ms
		(see Control register 2)		Latched	(1)
TJSD	Junction temperature shutdown			150			°C
TJHYST	Junction temperature thermal			20			°C
	hysteresis
TJRST	Junction temperature restart threshold			130			°C

1. Unlatch through I2C communication.

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L6360

Electrical characteristics

Table 7.

Electrical characteristics - linear regulator

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDD

Linear regulator output voltage

SEL = L

4.84

5

5.13

V

SEL = H

3.22

3.3

3.37

V

ILIMLR

Linear regulator output current

65

mA

limitation

Table 8.

Electrical characteristics - logic inputs and outputs

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VIL

Input low-level voltage

0.8

V

VIH

Input high-level voltage

2.2

V

VIHIS

Input hysteresis voltage

0.2

V

IIN

Input current

VIN = 5 V

1

µA

VOL

Output low-level voltage

IOUT = -2 mA

0.5

V

VOH

Output high-level voltage

IOUT = 2 mA

VDD - 0.5 V

V

VLIRQ

Open drain output low-level

IOUT = 2 mA

0.5

V

voltage

Table 9.

Electrical characteristics - LED driving

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VLED1, 2

Open drain output low-level

ILED = 2 mA

0.5

V

voltage

-

ILED

LED1, 2 leakage current

VLED1 = VLED2 = 5 V

3

nA

Table 10. Electrical characteristics - I2C (Fast mode)(1)

Symbol	Parameter	Test condition	Min.	Max.	Unit
VIL(SDA)	SDA low-level input voltage			0.3	V
VIH(SDA)	SDA high-level input voltage		0.7 x VDD		V
VIL(SCL)	SCL low-level input voltage			0.3	V
VIH(SCL)	SCL high-level input voltage		0.7 x VDD		V
IIN	I2C SDA, SCL input current	(0.1 x VDD) <VIN < (0.9 x VDD)	-10	10	µA
tr(SDA)	I2C SDA rise time		20 + 0.1 Cb	300	ns
tr(SCL)	I2C SCL rise time		20 + 0.1 Cb	300	ns
tf(SDA)	I2C SDA fall time		20 + 0.1 Cb	300	ns
tf(SCL)	I2C SCL fall time		20 + 0.1 Cb	300	ns
tsu(SDA)	SDA setup time		100		ns
th(SDA)	SDA hold time			0.9	µs

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Electrical characteristics						L6360
Table 10.	Electrical characteristics - I2C (Fast mode)(1) (continued)
Symbol		Parameter	Test condition	Min.	Max.	Unit
tsu(STA)		Repeated START condition		0.6		µs
		setup
tsu(STO)		STOP condition setup time		0.6		µs
tw(START/STOP)		STOP to START condition time		1.3		µs
		(bus free)
tw(SCLL)		SCL clock low time		1.3		µs
tw(SCLH)		SCL clock high time		0.6		µs
Cb		Capacitance for each bus line			400	pF
CI		Capacitance for each I/O pin			10	pF

1. Values based on standard I2C protocol requirement.

Figure 3. Rise/fall time test setup

# 1/

N&				N&

,

!-

Figure 4. Normalized rise and fall time vs. output capacitor value (typ. values in push-pull configuration)

					T200
					T&00
			## N&

!-

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L6360		Electrical characteristics
Table 11.	Main parameters typical variation vs. +/- 1% variation of Rbias value
		Typ. variation vs. Rbias
Symbol	Parameter		Rbias [kΩ]
		122.74	124	125.24
Is	Supply current	0.76%	0	-0.50%
IINC/Qi	Input current C/QI pin (5.5 mA)	0.93%	0	-0.93%
IINC/Qi	Input current C/QI pin (2.5 mA)	0.75%	0	-1.13%
IINI/Q	Input current I/Q pin (2.5 mA)	0.85%	0	-0.85%
tdcoq	C/QO lowand high-side cutoff current delay time	-2.44%	0	2.00%
ICOQ	C/QO lowand high-side cutoff current (115 mA)	1.19%	0	-1.28%
tdcol	L+ cutoff current delay time (500 µs)	-0.95%	0	0.47%
ICOL	L+ cutoff current	1.36%	0	-0.91%
trcol	L+ restart delay time	-0.93%	0	0.97%
VUV	Undervoltage ON-threshold	0.00%	0	0.00%
VDD	Linear regulator output voltage (3.3 V)	-0.03%	0	0.03%
VDD	Linear regulator output voltage (5 V)	-0.02%	0	0.02%
ILIMQ	C/QO high-side limitation current	0.64%	0	-0.71%
ILIMQ	C/QO low-side limitation current	0.28%	0	-1.47%
ILIML	L+ limitation current	0.47%	0	-2.09%
VQTHH	C/QI and I/Q upper voltage threshold	0.00%	0	0.00%
VQTHL	C/QI and I/Q lower voltage threshold	0.00%	0	0.00%
VQHY	C/Q and I/Q hysteresis voltage	0.00%	0	0.00%
trPP	C/Q rise time in push-pull configuration	-1.59%	0	1.18%
tfPP	C/Q fall time in push-pull configuration	-2.14%	0	0.94%
tdINC/Q	INC/Q to C/QO propagation delay time	-1.44%	0	0.75%
tdINC/Q	INC/Q to C/QO propagation delay time	-2.36%	0	0.18%
tdC/Qi	C/QI to OUTC/Q propagation delay time	0.49%	0	1.13%
tdC/Qi	C/QI to OUTC/Q propagation delay time	1.82%	0	0.03%
tdbq	C/QI de-bounce time (100 µs)	-1.76%	0	1.50%
tdcoq	C/QO lowand high-side cutoff current delay time (200 µs)	-1.27%	0	2.00%
ICOQ	C/QO low-side cutoff current (220 mA)	0.39%	0	-1.56%
ICOQ	C/QO low-side cutoff current (350 mA)	0.36%	0	-1.43%
ICOQ	C/QO low-side cutoff current (580 mA)	0.65%	0	-1.72%
trcoq	C/QO restart delay time	-0.90%	0	0.97%
ICOQ	C/QO high-side cutoff current (220 mA)	0.84%	0	-0.84%
ICOQ	C/QO high-side cutoff current (350 mA)	1.38%	0	-0.69%
ICOQ	C/QO high-side cutoff current (580 mA)	1.08%	0	-1.08%

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Device configuration	L6360

6 Device configuration

SDA and SCL configure the L6360 device through I2C.

6.1I²C single master bus interface

6.1.1Introduction

The I2C bus interface serves as an interface between the microcontroller and the serial I2C bus.

It provides single master functions, and controls all I2C bus-specific sequencing, protocol and timing.

It supports fast I2C mode (400 kHz).

6.1.2Main features

●Parallel bus / I2C protocol converter

●Interrupt generation

●Fast I2C mode

●7-bit addressing.

6.1.3General description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa.

The interface is connected to the I2C bus by a data pin (SDA) and a clock pin (SCL).

6.1.4SDA/SCL line control

SDA is a bi-directional line, SCL is the clock input. SDA should be connected to a positive supply voltage via a current-source or pull-up resistor. When the bus is free, both lines are HIGH.

The output stages of devices connected to the bus must have an open drain or open collector output to perform the wired AND function. Data on the I2C bus can be transferred at rates up to 400 Kbit/s in fast mode.

The number of interfaces connected to the bus is limited by the bus capacitance.

For a single master application, the master's SCL output can be a push-pull driver provided that there are no devices on the bus which would stretch the clock.

Transmitter mode: the microcontroller interface holds the clock line low before transmission.

Receiver mode: the microcontroller interface holds the clock line low after reception.

When the I2C microcontroller cell is enabled, the SDA and SCL ports must be configured as floating inputs.

In this case, the value of the external pull-up resistors used depends on the application.

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L6360	Device configuration

When the I2C microcontroller cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.

On the L6360, the SDA output is an open drain pin.

6.1.5Mode selection

Possible data transfer formats are:

●The master transmitter transmits to the slave receiver. The transfer direction is not changed (see Figure 5).

●The slave receiver acknowledges each byte.

●The master reads data from the slave immediately after the first byte (see Figure 6). At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter.

This first acknowledge is still generated by the slave.

Subsequent acknowledges are generated by the master. The STOP condition is generated by the master which sends a not-acknowledge (A) just prior to the STOP condition.

Figure 5. A master transmitter addressing a slave receiver with a 7-bit address (the transfer is not changed)

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Device configuration	L6360

On the microcontroller, the interface can operate in the two following modes:

●Master transmitter/receiver

●Idle mode (default state)

The microcontroller interface automatically switches from idle to master receiver after it detects a START condition and from master receiver to idle after it detects a STOP condition.

On the L6360 the interface can operate in the two following modes:

●Slave transmitter/receiver

●Idle mode (default state)

The interface automatically switches from idle to slave transmitter after it detects a START condition and from slave transmitter to idle after it detects a STOP condition.

6.1.6Functional description

By default, the I2C microcontroller interface operates in idle; to switch from default Idle mode to Master mode a START condition generation is needed.

The transfer sequencing is shown in Figure 7.

Figure 7. Transfer sequencing

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