ST L6258 User Manual

L6258

PWM controlled high current DMOS universal motor driver

Features

■Able to drive both windings of a bipolar stepper motor or two DC motors

■Output current up to 1.2A each winding

■Wide voltage range: 12V to 34V

■Four quadrant current control, ideal for microstepping and DC motor control

■Precision PWM control

■No need for recirculation diodes

■TTL/CMOS compatible inputs

■Cross conduction protection

■Thermal shutdow

Description

L6258 is a dual full bridge for motor control applications realized in BCD technology, with the capability of driving both windings of a bipolar stepper motor or bidirectionally control two DC motors.

L6258 and a few external components form a complete control and drive circuit. It has high efficiency phase shift chopping that allows a very low current ripple at the lowest current control levels, and makes this device ideal for steppers as well as for DC motors.

Not For New Design

PowerSO36

The power stage is a dual DMOS full bridge capable of sustaining up to 34V, and includes the diodes for current recirculation. The output current capability is 1.2A per winding in continuous mode, with peak start-up current up to 1.5A. A thermal protection circuitry disables the outputs if the chip temperature exceeds the safe limits.

Table 1.	Device summary
	Order Code	Package	Packing
	L6258
(Replaced by E-L6258EX and E-		PowerSO36	Tube
	L6258EXTR)

March 2010	Doc ID 4588 Rev 10	1/32
This is information on a product still in production but not recommended for new designs.		www.st.com

Contents	L6258

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	2.1	Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.2	Input logic (I0 - I1 - I2 - I3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.3	Phase input ( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	2.4	Triangular generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	2.5	Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	2.6	Current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	2.7	Current control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
3	PWM current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16

3.1 Open loop transfer function analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Load attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Error amplifier and sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Effect of the Bemf of the current control loop stability . . . . . . . . . . . . . . . 22

4	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
	4.1	Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	4.2	Motor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	4.3	Unused inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	4.4	Notes on PCB design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
5	Operation mode time diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
6	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
7	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31

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L6258	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Charge pump capacitor's values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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List of figures	L6258

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Power bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Current control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Output comparator waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Ax bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Aloop bode plot (uncompensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Aloop bode plot (compensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Electrical model of the load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. Full step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. Half step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. 4 bit microstep operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15. PowerSO36 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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L6258	Block diagram

1 Block diagram

Figure 1. Block diagram

					R1 1M
				RC1			CC1			CBOOT
	CP	VCP2	EA_IN1					EA_OUT1		VS	VBOOT
								TRI_0
VCP1	CHARGE							+	C		OUT1A
	PUMP					ERROR		-
			VR							POWER
					+		AMP			BRIDGE
VREF1								+		1	OUT1B
		INPUT			-				C
I3_1								TRI_180			SENSE1B
		&						-
I2_1	DAC	SENSE									Rs
I1_1		AMP
I0_1
PH_1											SENSE1A
VDD(5V)	VR GEN	VR (VDD/2)	THERMAL								DISABLE
			PROT.
											VS
VREF1						ERROR		TRI_0
I3_2			VR						+		OUT2A
		INPUT			+		AMP			C
I2_2									-
	DAC	&			-					POWER
I1_2		SENSE								BRIDGE
									+		OUT2B
I0_2		AMP								2
									-	C	SENSE2B
PH_2
								TRI_180
TRI_CAP	TRIANGLE	TRI_0									Rs
	GENERATOR	TRI_180
CFREF
											SENSE2A
	GND		EA_IN2					EA_OUT2			D96IN430D
					RC2		CC2
					R2 1M

Table 2.	Absolute maximum rating
Parameter		Description	Value	Unit
	Vs	Supply voltage	36	V
	VDD	Logic supply voltage	7	V
	Vref1/Vref2	Reference voltage	2.5	V
	IO	Output current (peak)	1.5	A
	IO	Output current (continuous)	1.2	A
	Vin	Logic input voltage range	-0.3 to 7	V
	Vboot	Bootstrap supply	60	V
	Vboot - Vs	Maximum Vgate applicable	15	V
	Tj	Junction temperature	150	°C
	Tstg	Storage temperature range	-55 to 150	°C

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Block diagram	L6258
Figure 2.	Pin connection (top view)

PWR_GND		1		36		PWR_GND
PH_1		2	35			SENSE1
I1_1		3	34			OUT1B
I0_1		4	33			I3_1
OUT1A		5	32			I2_1
DISABLE		6	31			VS
TRI_CAP		7	30			EA_OUT1
VDD		8	29			EA_IN1
		9	28
GND						VREF1
VCP1		10	27			SIG_GND
VCP2		11	26			VREF2
VBOOT		12	25			EA_IN2
VS		13	24			EA_OUT2
OUT2A		14	23			I2_2
I0_2		15	22			I3_2
I1_2		16	21			OUT2B
PH_2		17	20			SENSE2
PWR_GND		18		19		PWR_GND

D96IN432E

Table 3.	Pin functions
Pin #		Name	Description
1, 36		PWR_GND	Ground connection (1). They also conduct heat from die to
			printed circuit copper.
			These TTL compatible logic inputs set the direction of
2, 17		PH_1, PH_2	current flow through the load. A high level causes current to
			flow from OUTPUT A to OUTPUT B.
			Logic input of the internal DAC (1). The output voltage of the
3		I1_1	DAC is a percentage of the Vref voltage applied according to
			the thruth Table 5 on page 12.
4		I0_1	See pin 3
5		OUT1A	Bridge output connection (1)
6		DISABLE	Disables the bridges for additional safety during switching.
			When not connected the bridges are enabled
7		TRI_cap	Triangular wave generation circuit capacitor. The value of
			this capacitor defines the output switching frequency

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L6258				Block diagram
	Table 3.	Pin functions (continued)
	Pin #		Name	Description
	8		VDD (5V)	Supply voltage input for logic circuitry
	9		GND	Power ground connection of the internal charge pump circuit
	10		VCP1	Charge pump oscillator output
	11		VCP2	Input for external charge pump capacitor
	12		VBOOT	Overvoltage input for driving of the upper DMOS
	13, 31		VS	Supply voltage input for output stage. They are shorted
				internally
	14		OUT2A	Bridge output connection (2)
				Logic input of the internal DAC (2). The output voltage of the
	15		I0_2	DAC is a percentage of the VRef voltage applied according
				to the truth Table 5 on page 12.
	16		I1_2	See pin 15
	18, 19		PWR_GND	Ground connection. They also conduct heat from die to
				printed circuit copper
	20, 35		SENSE2, SENSE1	Negative input of the transconductance input amplifier (2, 1)
	21		OUT2B	Bridge output connection and positive input of the
				tranconductance (2)
	22		I3_2	See pin 15
	23		I2_2	See pin 15
	24		EA_OUT_2	Error amplifier output (2)
	25		EA_IN_2	Negative input of error amplifier (2)
				Reference voltages for the internal DACs, determining the
	26, 28		VREF2, VREF1	output current value. Output current also depends on the
				logic inputs of the DAC and on the sensing resistor value
	27		SIG_GND	Signal ground connection
	29		EA_IN_1	Negative input of error amplifier (1)
	30		EA_OUT_1	Error amplifier output (1)
	32		I2_1	See pin 3
	33		I3_1	See pin 3
	34		OUT1B	Bridge output connection and positive input of the
				tranconductance (1)
Note:	The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1
	and 36 are connected together.

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Block diagram

L6258

Figure 3. Thermal characteristics

Conditions

Power Dissipated

T Ambient

Thermal J-A resistance

(W)

(˚C)

(˚C/W)

5.3

70

15

pad

layout + ground layers + 16

via hol

PCB ref.: 4 LAYER cm 12 x 12

4.0

70

20

pad layout + ground layers

PCB ref.: 4 LAYER cm 12 x 12

2.3

70

35

pad layout + 6cm2 on board heat sink

PCB ref.: 2 LAYER cm 12 x 12

	12
(W)	10
	8
Dissipated
	6
Power
	4
	2
	0
		0

D02IN1370

15˚C/W

20˚C/W

35˚C/W

20	40	60	80	100	120	140	160
		Ambient Temperature (˚C)				D02IN1371

Table 4.	Electrical characteristics
	(VS = 40V; VDD = 5V; Tj = 25°; unless otherwise specified.)
Parameter	Description	Test condition	Min.	Typ.	Max.	Unit
VS	Supply voltage		12		34	V
VDD	Logic supply voltage		4.75		5.25	V
VBOOT	Storage voltage	VS = 12 to 40V	VS+6		VS+12	V
VSense	Max drop across sense				1.25	V
	resistor
VS(off)	Power off reset	Off threshold	6		7.2	V
VDD(off)	Power off reset	Off threshold	3.3		4.1	V
IS(on)	VS quiescent current	Both bridges ON, no			15	mA
		load
IS(off)	VS quiescent current	Both bridges OFF			7	mA
IDD	VDD operative current				15	mA

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L6258						Block diagram
	Table 4.	Electrical characteristics (continued)
		(VS = 40V; VDD = 5V; Tj = 25°; unless otherwise specified.)
	Parameter	Description	Test condition	Min.	Typ.		Max.	Unit
	TSD-H	Shut down hysteresis			25			°C
	TSD	Thermal shutdown			150			°C
	fosc	Triangular oscillator	CFREF = 1nF	12.5	15		18.5	KHz
		frequency(1)
	TRANSISTORS
	IDSS	Leakage current	OFF State				500	µA
	Rds(on)	On resistance	ON state		0.6		0.75	W
	Vf	Flywheel diode voltage	If =1.0A		1		1.4	V
	CONTROL LOGIC
	Vin(H)	lnput voltage	All Inputs	2			VDD	V
	Vin(L)	Input voltage	All inputs	0			0.8	V
	Iin	Input current (2)	0 < Vin < 5V	-150			+10	µA
	Idis	Disable pin input current		-10			+150	µA
	Vref1/ref2	Reference voltage	Operating	0			2.5	V
	Iref	Vref terminal input current	Vref = 1.25	-2			5	µA
	FI =	PWM loop transfer ratio			1.94
	Vref/Vsense
	VFS	DAC full scale precision	Vref = 2.5V I0/I1/I2/I3 = L	1.23	1.29		1.34	V
	Voffset	Current loop offset	Vref = 2.5V I0/I1/I2/I3 = H	-30			+30	mV
		DAC factor ratio	Normalized @ full scale	-2			+2	%
			value
	SENSE AMPLIFIER
	Vcm	lnput common mode		-0.7			VS+0.7	V
		voltage range
	Iinp	Input bias	sense1/sense2	-200			0	µA
	ERROR AMPLIFIER
	GV	Open loop voltage gain			70			dB
	SR	Output slew rate	Open loop		0.2			V/µs
	GBW	Gain bandwidth product			400			kHz

1.Chopping frequency is twice fosc value.

2.This is true for all the logic inputs except the disable input.

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Functional description	L6258

2 Functional description

The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.

The current control is generated through a switch mode regulation.

With this system the direction and the amplitude of the load current are depending on the relation of phase and duty cycle between the two outputs of the current control loop.

The L6258 power stage is composed by power DMOS in bridge configuration as it is shown in Figure 4, where the bridge outputs OUT_A and OUT_B are driven to Vs with an high level at the inputs IN_A and IN_B while are driven to ground with a low level at the same inputs.

The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same phase and 50% of duty cycle.

In this case the outputs of the two half bridges are continuously switched between power supply (Vs) and ground, but keeping the differential voltage across the load equal to zero.

In Figure 4 is shown the timing diagram of the two outputs and the load current for this working condition.

Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while we consider negative the current flowing into load with a direction from OUT_B to OUT_A.

Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive positive current into the load.

In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge formed by T1 and T4 when the output OUT_A is driven to Vs and the output OUT_B is driven to ground, while there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs are connected to ground.

Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is higher than the current charging time constant during the period in which the current flows into the load through the diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude depending on the difference in duty cycle of the two driving signals.

In Figure 4 is shown the timing diagram in the case of positive load current

On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions of the previous case when both the outputs are driven to Vs or to ground.

So, in this case the load current will be negative with an average amplitude always depending by the difference in duty cycle of the two driving signals.

In Figure 4 is shown the timing diagram in the case of negative load current.

Figure 5 shows the device block diagram of the complete current control loop.

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