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L6235Q
User Manual
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ST L6235Q User Manual

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DMOS driver for 3-phase brushless dc motor
Features
■ Operating supply voltage from 8 to 52 V
■ 5.6 A output peak current
■ R
■ Operating frequency up to 100 kHz
■ Non-dissipative overcurrent protection
■ Diagnostic output
■ Constant t
■ Slow decay synchronous rectification
■ 60° and 120° Hall effect decoding logic
■ Brake function
■ Tacho output for speed loop
■ Cross conduction protection
■ Thermal shutdown
■ Undervoltage lockout
■ Integrated fast freewheeling diodes

Figure 1. Block diagram

0.3 Ω typ. value @ TJ = 25 °C
PWM current controller
OFF
L6235Q
QFN-48
(7 x 7 mm)
Description
The L6235Q is a DMOS fully integrated 3-phase motor driver with overcurrent protection. Realized in BCDmultipower technology, the device combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a 3-phase BLDC motor including: a 3-phase DMOS bridge, a constant OFF time PWM current controller and the decoding logic for single ended Hall sensors that generates the required sequence for the power stage. Available in QFN48 7x7 package, the L6235Q features a non­dissipative overcurrent protection on the high-side power MOSFETs and thermal shutdown.
VBOOT V
VCP
DIAG
EN
BRAKE
FWD/REV
H
3
H
2
H
1
RCPULSE
TACHO
BOOT
CHARGE
TACHO
MONOSTABLE
10V 5V
REGULATOR
PUMP
OCD
VOLTAGE
THERMAL
PROTECTION
OCD1
OCD2
OCD
HALL-EFFECT
SENSORS
DECODING
LOGIC
OCD3
ONE SHOT
MONOSTABLE
GATE
LOGIC
PWM
MASKING
TIME
V
BOOT
OCD1
10V
V
BOOT
OCD2
10V
V
BOOT
OCD3
10V
COMPARATOR
SENSE
VS
A
OUT
1
OUT
2
SENSE
A
VS
B
OUT
3
SENSE
+
-
B
VREF
RCOFF
AM02555v1
November 2011 Doc ID 018997 Rev 2 1/33
www.st.com
33
Contents L6235Q
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Tacho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 18
4.8 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 25
7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/33 Doc ID 018997 Rev 2
L6235Q Electrical data

1 Electrical data

1.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Parameter Value Unit
V
Supply voltage VSA = VSB = VS 60 V
S
V
OD
V
BOOT
V
IN,VEN
V
REF
V
RCOFF
V
SENSE
I
S(peak)
I
Differential voltage between VSA, OUT1A, OUT2A, SENSEA and
, OUT1B, OUT2B, SENSE
VS
B
B
Bootstrap peak voltage VSA = VSB = VS V
Input and enable voltage range -0.3 to +7 V
Voltage range at pin V
Voltage range at pin RC
REF
OFF
Voltage range at pins SENSEA and SENSE
B
Pulsed supply current (for each VSA
SB
pin)
and V
DC supply current (for each VSA and
S
VSB pin)
VSA = VSB = VS = 60 V; VSENSEA = VSENSEB =
60 V
GND
+ 10 V
S
-0.3 to +7 V
-0.3 to +7 V
-1 to +4 V
V
= VSB = VS;
SA
< 1 ms
t
PULSE
VS
= VSB = VS 2.5 A
A
7.1 A
, TOP
T
stg
Storage and operating temperature range

1.2 Recommended operating conditions

Table 2. Recommended operating conditions

Symbol Parameter Parameter Min. Max. Unit
V
Supply voltage VSA = VSB = VS 8 52 V
S
Differential voltage between
V
V
V
SENSE
I
OUT
f
OD
REF
T
sw
VSA, OUT1A, OUT2A, SENSEA and
, OUT1B, OUT2B, SENSEB
VS
B
Voltage range at pin V
-0.1 5 V
REF
Voltage range at pins SENSEA and SENSE
B
DC output current VSA = VSB = VS;2.5 A
Operating junction temperature -25 +125 °C
j
Switching frequency 100 kHz
= VSB = VS;
VS
A
V
SENSEA
Pulsed tW < t
DC -1 1 V
= V
SENSEB
rr
-40 to 150 °C
52 V
-6 6 V
Doc ID 018997 Rev 2 3/33
Pin connection L6235Q

2 Pin connection

Figure 2. Pin connection (top view)

OUT1
OUT1
GND
TACHO
NC
NC
NC
NC
NC
NC
NC
NC
SENSEA
RCOFF
NC
48 47 46 45 44 43 42 41 40 39 38 37
1
EPAD
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
NC
SENSEB
RCPULSE
SENSEA
SENSEB
H1
H3
DIAG
EN
VREF
FWD/REV
Note: The exposed PAD must be connected to GND pin.
H2
BRAKE
VCP
VBOOT
OUT2
OUT3
OUT2
OUT3
NC
NC
36
NC
35
VSA
34
VSA
33
NC
32
NC
31
GND
30
NC
29
NC
28
NC
27
VSB
26
VSB
25
NC
AM02556v1

Table 3. Pin description

Pin Name Type Function
43 H1 Sensor input Single ended Hall effect sensor input 1.
44 DIAG
45, 46 SENSE
48 RC
OFF
Open drain
output
Power supply
A
RC pin
2, 3 OUT1 Power output Output 1
6, 31 GND GND Ground terminals.
12 TACHO
Open drain
output
13 RCPULSE RC pin
Overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when an overcurrent on one of the high-side MOSFETs is detected or during thermal protection.
Half bridge 1 and half bridge 2 source pin. This pin must be connected together with pin SENSEB to power ground through a sensing power resistor.
RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF time.
Frequency-to-voltage open drain output. Every pulse from pin H shaped as a fixed and adjustable length pulse.
RC network pin. A parallel RC network connected between this pin and ground sets the duration of the monostable pulse used for the frequency-to-voltage converter.
is
1
4/33 Doc ID 018997 Rev 2
L6235Q Pin connection
Table 3. Pin description (continued)
Pin Name Type Function
Half bridge 3 source pin. This pin must be connected together with
15, 16 SENSE
Power supply
B
17 FWD/REV Logic input
pin SENSE this pin also the inverting input of the sense comparator is connected.
Selects the direction of the rotation. High logic level sets forward operation, whereas low logic level sets reverse operation. If not used, it must be connected to GND or +5 V.
to power ground through a sensing power resistor. At
A
18 EN Logic input
19 VREF Logic input
Chip enable. Low logic level switches off all power MOSFETs. If not used, it must be connected to +5 V.
Current controller reference voltage. Do not leave this pin open or connect to GND.
Brake input pin. Low logic level switches on all high-side power
20 BRAKE Logic input
MOSFETs, implementing the brake function. If not used, it must be connected to +5 V.
21 VBOOT Supply voltage Bootstrap voltage needed for driving the upper power MOSFETs.
22, 23 OUT
26, 27 VSB Power supply
34, 35 VSA Power supply
38, 39 OUT
Power output Output 3.
3
Half bridge 3 power supply voltage. It must be connected to the supply voltage together with pin VS
Half bridge 1 and half bridge 2 power supply voltage. It must be connected to the supply voltage together with pin VS
Power output Output 2.
2
.
A
.
B
40 VCP Output Charge pump oscillator output.
41 H2 Sensor input Single ended Hall effect sensor input 2.
42 H
Sensor input Single ended Hall effect sensor input 3.
3
Doc ID 018997 Rev 2 5/33
Electrical characteristics L6235Q

3 Electrical characteristics

VS = 48 V, TA = 25 °C, unless otherwise specified.

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit
V
Sth(ON)
V
Sth(OFF)
Turn-on threshold 6.6 7 7.4 V
Turn-off threshold 5.6 6 6.4 V
IS Quiescent supply current
Thermal shutdown temperature 165 °C
T
j(OFF)
Output DMOS transistors
High-side switch ON resistance
R
DS(ON)
Low-side switch ON resistance
I
DSS
Leakage current
Source drain diodes
V
Forward ON voltage ISD = 2.5 A, EN = low 1.15 1.3 V
SD
t
rr
t
fr
Reverse recovery time If = 2.5 A 300 ns
Forward recovery time 200 ns
Logic input (H1, H2, H3, EN, FWD/REV, BRAKE)
All bridges OFF; Tj = -25 °C to 125 °C
(1)
510mA
Tj = 25 °C 0.34 0.4
Tj =125 °C
(1)
0.53 0.59
Ω
Tj = 25 °C 0.28 0.34
Tj =125 °C
EN = low; OUT = V
(1)
0.47 0.53
2mA
S
EN = low; OUT = GND -0.15 mA
V
V
I
I
V
th(ON)
V
th(OFF)
V
th(HYS)
IH
IL
IH
Low level logic input voltage -0.3 0.8 V
IL
High level logic input voltage 2 7 V
Low level logic input current GND logic input voltage -10 µA
High level logic input current 7 V logic input voltage 10 µA
Turn-on input threshold 1.8 2.0 V
Turn-off input threshold 0.8 1.3 V
Input threshold hysteresis 0.25 0.5 V
Switching characteristics
t
D(on)EN
t
D(off)EN
t
D(on)IN
t
D(off)IN
Enable to out turn ON delay time
Enable to out turn OFF delay time
Other logic inputs to output turn ON delay time
Other logic inputs to out turn OFF delay time
(2)
(2)
I
I
I
I
=2.5 A, resistive load 100 250 400 ns
LOAD
=2.5 A, resistive load 300 550 800 ns
LOAD
=2.5 A, resistive load 2 ns
LOAD
=2.5 A, resistive load 2 ns
LOAD
6/33 Doc ID 018997 Rev 2
L6235Q Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
Output rise time
RISE
t
Output fall time
FAL L
Dead time protection 0.5 1 µs
t
DT
Charge pump frequency Tj = -25 °C to 125 °C (7) 0.6 1 MHz
f
CP
PWM comparator and monostable
(2)
(2)
I
I
=2.5 A, resistive load 40 250 ns
LOAD
=2.5 A, resistive load 40 250 ns
LOAD
I
RCOFF
V
offset
t
PROP
t
BLANK
t
ON(MIN)
t
OFF
I
BIAS
Source current at pin RC
OFF
Offset voltage on sense comparator V
Turn OFF propagation delay
Internal blanking time on SENSE comparator
(3)
V
RCOFF =
REF
2.5 V 3.5 5.5 mA
= 0.5 V ±5 mV
Minimum ON time 1.5 2 µs
R
PWM recirculation time
Input bias current at pins VREF VREF
B
and
A
OFF
= 100 kΩ; C
R
OFF
= 20 kΩ; C
= 1 nF 13 µs
OFF
= 1 nF 61 µs
OFF
Tacho monostable
I
RCPULSE
t
PULSE
R
TAC H O
Source current at pin RCPULSE V
Monostable of time
RCPULSE
R
PUL
R
PUL
Open drain ON resistance 40 60 Ω
= 2.5 V 3.5 5.5 mA
= 20 kΩ; C
= 100 kΩ; C
=1 nF 12 µs
PUL
=1 nF 60 µs
PUL
Over current detection e protection
I
sover
R
OPDR
I
OH
t
OCD(ON)
t
OCD(OFF)
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin V
4. See Figure 4.
Supply overcurrent protection threshold
-25 °C<Tj <125 °C 4.0 5.6 7.1 A
Open drain ON resistance I = 4 mA 40 60 Ω
OCD high level leakage current V
OCD turn-on delay time
OCD turn-off delay time
(4)
(4)
= 5 V 1 µA
DIAG
I = 4 mA; CEN < 100 pF 200 ns
I = 4 mA; CEN < 100 pF 100 ns
REF
500 ns
1µs
10 µA
.
Doc ID 018997 Rev 2 7/33
Electrical characteristics L6235Q

Figure 3. Switching characteristic definition

EN
V
th(ON)
V
th(OFF)
t
I
OUT
90%
10%
D01IN1316
t
D(OFF)EN
t
FAL L
t
D(ON)EN
t
t
RISE
AM02557v1

Figure 4. Overcurrent detection timing definition

I
OUT
I
SOVER
ON
BRIDGE
OFF
V
DIAG
90%
10%
t
OCD(ON)
t
OCD(OFF)
AM02558v1
8/33 Doc ID 018997 Rev 2
L6235Q Circuit description

4 Circuit description

4.1 Power stages and charge pump

The L6235Q integrates a 3-phase bridge, which consists of 6 power MOSFETs connected as shown in Figure 1, each power MOSFET has an R with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM current controller and the Hall effect sensor decoding logic (Chapter 4.3 on page 11). Cross conduction protection is implemented by using a dead time (t internal timing circuit between the turn-off and turn-on of two power MOSFETs in one leg of a bridge.
= 0.3 Ω (typical value @ 25 °C)
DS(ON)
= 1 µs typical value) set by
DT
Pins VS
and VSB must be connected together to the supply voltage (VS).
A
Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply (V
) is obtained
BOOT
through an internal oscillator and a few external components to realize a charge pump circuit, as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Tab le 5 .

Table 5. Charge pump external component values

Component Value
C
BOOT
C
P
R
P
220 nF
10 nF
100 Ω
D1 1N4148
D2 1N4148

Figure 5. Charge pump circuit

V
S
D1
R
C
VCP VBOOT VS
C
D2
P
P
BOOT
VS
A
B
AM02559v1
Doc ID 018997 Rev 2 9/33
Circuit description L6235Q

4.2 Logic inputs

Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and µC compatible logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off thresholds are respectively V
Pin EN (enable) may be used to implement overcurrent and thermal protection by connecting it to the open collector DIAG output. If the protection and an external disable function are both desired, the appropriate connection must be implemented. When the external signal is from an open collector output, the circuit in Figure 7 may be used. For external circuits that are push-pull outputs the circuit in Figure 8 may be used. The resistor R
should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN
EN
and C
are respectively 100 kΩ and 5.6 nF. More information for selecting the values can
EN
be found in Section 4.7.

Figure 6. Logic inputs internal structure

=1.8 V and V
thon
PROTECTION
ESD
thoff
= 1.3 V.
5V

Figure 7. EN pins open collector driving

DIAG
OPEN
COLLECTOR
OUTPUT
5V
R
EN
C
EN

Figure 8. EN pins push-pull driving

R
PUSH-PULL
OUTPUT
EN
C
EN
AM02560v1
5V
EN
ESD
PROTECTION
AM02561v1
DIAG
5V
EN
ESD
PROTECTION
10/33 Doc ID 018997 Rev 2
AM02562v1
L6235Q Circuit description

4.3 PWM current control

The L6235Q includes a constant OFF time PWM current controller. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power MOSFET transistors and ground, as shown in Figure 9. As the current in the motor increases, the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin V triggers the monostable switching the bridge off. The power MOSFET remains off for the time set by the monostable and the motor current recirculates around the upper half of the bridge in slow decay mode, as described in Section 4.4. When the monostable times out, the bridge again turns on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn-on of the power MOSFET, the effective OFF time t of the monostable time plus the dead time.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the pin RC voltage and the status of the bridge. More details regarding the synchronous rectification and the output stage configuration are included in
Section 4.4.
Immediately after the power MOSFET turns on, a high peak current flows through the sense resistor due to the reverse recovery of the freewheeling diodes. The L6235 provides a 1µs blanking time t
that inhibits the comparator output so that the current spike cannot
BLANK
prematurely re-trigger the monostable.
, the sense comparator
REF
is the sum
OFF

Figure 9. PWM current controller simplified schematic

VS
B
S
R
BLANKING TIME
MONOSTABLE
1μs
MONOSTABLE
SET
COMPARATOR
BLANKER
SENSE
FROM THE
LOW-SIDE
GATE DRIVERS
DRIVERS
+
DEAD TIME
+
-
VREF
R
DRIVERS
DEAD TIME
SENSE
SENSE
TO GATE
LOGIC
5mA
(0) (1)
5V
C
OFF
RCOFF
R
Q
-
+
2.5V
OFF
VS
A
+
B
SENSE
DRIVERS
+
DEAD TIME
A
VS
OUT
OUT
OUT
2
3
1
Doc ID 018997 Rev 2 11/33
Circuit description L6235Q

Figure 10. Output current regulation waveforms

I
OUT
V
REF
R
SENSE
t
OFF
V
SENSE
V
REF
0
V
RC
5V
2.5V
ON
SYNCHRONOUS RECTIFICATION
OFF
D02IN1351
1μs t
BLANK
Slow Decay Slow Decay
t
RCRISE
t
RCFALL
1μs t
DT
BC
Figure 11 shows the magnitude of the OFF time t
OFF
t
ON
versus C
t
OFF
1μs t
BLANK
t
RCRISE
t
RCFALL
1μs t
DT
BC
and R
OFF
be approximately calculated from the equations:
t
RCFALL
t
OFF
where R
= 0.6 · R
= t
RCFALL
and C
OFF
· C
OFF
+ tDT = 0.6 · R
OFF
OFF
OFF
· C
OFF
+ t
DT
are the external component values and t
is the internally generated
DT
dead time with:
20 kΩ ≤ R
0.47 nF ≤ C
t
= 1 µs (typical value)
DT
OFF
OFF
≤ 100 kΩ
≤ 100 nF
therefore:
t
OFF(MIN)
t
OFF(MAX)
These values allow a sufficient range of t
The capacitor value chosen for C pin R
COFF
= 6.6 µs
= 6 ms
. The rise time t
RCRISE
to implement the drive circuit for most motors.
OFF
also affects the rise time t
OFF
is only an issue if the capacitor is not completely charged
RCRISE
of the voltage at the
before the next time the monostable is triggered. Therefore, the ON time t depends on motors and supply parameters, must be bigger than t current regulation by the PWM stage. Furthermore, the ON time t the minimum ON time t
ON(MIN)
.
RCRISE
can not be smaller than
ON
DDA
values. It can
OFF
, which
ON
to allow a good
12/33 Doc ID 018997 Rev 2
L6235Q Circuit description
⎧
t
>
⎪
ONtON MIN()
⎨
t
⎪
ONtRCRISEtDT
⎩
t
RCRISE
–>
600 C
⋅=
1.5μstyp()=
OFF
Figure 12 shows the lower limit for the ON time tON for having a good PWM current
regulation capacity. It should be mentioned that t the device imposes this condition, but it can be smaller than t the device continues to work but the OFF time t
Therefore, a small C
value gives more flexibility to the applications (allows smaller ON
OFF
time and, therefore, higher switching frequency), but, the smaller the value for C
is always bigger than t
ON
is not more constant.
OFF
RCRISE
ON(MIN)
because
- tDT. In this last case
, the
OFF
more influential the noises on the circuit performance.
Figure 11. t
OFF
vs. C
1.10
1.10
100
toff [μs]
and R
OFF
4
3
10
1
0.1 1 10 100
OFF
R
= 100k Ω
R
off
= 47kΩ
R
off
= 20k
Ω
off
Coff [nF]
Doc ID 018997 Rev 2 13/33
Circuit description L6235Q

Figure 12. Area where tON can vary maintaining the PWM regulation

100
10
ton(min) [μs]
1.5μs (typ. value)
1
Coff [nF]
0010111.0
14/33 Doc ID 018997 Rev 2
L6235Q Circuit description

4.4 Slow decay mode

Figure 13 shows the operation of the bridge in slow decay mode during the OFF time. At any
time only two legs of the 3-phase bridge are active, therefore, only the two active legs of the bridge are shown in the figure and the third leg is off. At the start of the OFF time, the lower power MOSFET is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly.
After the dead time the upper power MOSFET is operated in the synchronous rectification mode reducing the impedance of the freewheeling diode and the related conducting losses. When the monostable times out, the upper power MOSFET that was operating the synchronous mode turns off and the lower power MOSFET is turned on again after some delay set by the dead time to prevent cross conduction.

Figure 13. Slow decay mode output stage configurations

D01IN1336

4.5 Decoding logic

The decoding logic section is a combinatory logic that provides the appropriate driving of the 3-phase bridge outputs according to the signals coming from the three Hall sensors that detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a universal IC without dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions 1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are used in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phasing (3b and 6b).
The decoder can drive motors with different sensor configurations simply by following
Ta bl e 2 . For any input configuration (H1, H2 and H3) there is one output configuration
(OUT
, OUT2 and OUT3). The output configuration 3a is the same as 3b and analogously
1
output configuration 6a is the same as 6b.
1 )BEMIT NO )A μs DEAD TIME C) SYNCHRONOUS
RECTIFICATION
D) 1μs DEAD TIME
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive the motor with all four conventions by changing the direction set.
Doc ID 018997 Rev 2 15/33
Circuit description L6235Q

Table 6. 60 and 120 electrical degree decoding logic in forward direction

Hall 120° 1 2 3a - 4 5 6a -
Hall 60° 1 2 - 3b 4 5 - 6b
H1 H H L H L L H L
H2 L H H H H L L L
H3 L L L H H H H L
OUT1 Vs High Z GND GND GND High Z Vs Vs
OUT2 High Z Vs Vs Vs High Z GND GND GND
OUT3 GND GND High Z High Z Vs Vs High Z High Z
Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2
Figure 14. 120° Hall sensor sequence
H
3
Figure 15. 60° Hall sensor sequence

4.6 Tacho

The tachometer function consists of a monostable, with constant OFF time (t input is one Hall effect signal (H an external op amp, as shown in Figure 17. For component values refer to Section 5.
H
1
H
2
H
1
H
3
H
2
H
1
H
3
H
2
H
1
H
3
H
2
H
1
H
3
H
2
1 2 3a 4 5 6a
= H
= L
H
1
H
H
2
3
H
1
H
H
2
3
H
1
H
H
2
3
H
1
H
H
2
3
H
1
H
H
2
3
1 2 3b 4 5 6b
= H
= L
). It allows to develop an easy speed control loop by using
1
H
3
H
1
H
3
PULSE
H
2
H
1
H
2
), whose
The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall effect sensors H1, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time t set using the external RC network (R gives the relation between t
t
= 0.6 · R
PULSE
16/33 Doc ID 018997 Rev 2
PUL
· C
PULSE
PUL
PUL
and C
(see Figure 16). The OFF time t
PULSE
, C
) connected to the pin RCPULSE. Figure 18
PUL
, R
PUL
PUL
. It is approximately:
PULSE
can be
L6235Q Circuit description
where C
should be chosen in the range 1 nF … 100 nF and R
PUL
in the range 20 kΩ …
PUL
100 kΩ.
By connecting the tachometer pin to an external pull-up resistor, the output signal average value VM is proportional to the frequency of the Hall effect signal and, therefore, to the motor speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an integrator, filters the signal and compares it with a reference voltage V
, which sets
REF
the speed of the motor.
t
PULSE
------------------
V
M
⋅=
V
T
DD

Figure 16. Tacho operation waveforms

H
1
H
2
H
3
V
TACHO
V
M
t
PULSE
V
DD
T

Figure 17. Tachometer speed control loop

V
DD
R
PUL
R
R
3
C
R
V
REF
C
REF2
DD
1
4
R
1
R
H
1
RCPULSE
C
PUL
TACHO
VREF
C
2
REF1
TACHO
MONOSTABLE
Doc ID 018997 Rev 2 17/33
Circuit description L6235Q
Figure 18. t
PULSE
vs. C
1.10
1.10
tpulse [μs]
100
and R
PUL
4
3
10
R
PUL
PUL
= 20k
Ω
= 100k
R
PUL
Ω
= 47k
R
PUL
Ω
Cpul [nF]
001011

4.7 Non-dissipative overcurrent detection and protection

The L6235Q integrates an overcurrent detection circuit (OCD) for full protection. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic of the overcurrent detection circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high-side power MOSFET. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I output current reaches the detection threshold (typically I
= 5.6 A), the OCD
SOVER
. When the
REF
comparator signals a fault condition. When a fault condition is detected, an internal open drain MOSFET with a pull-down capability of 4 mA connected to pin DIAG is turned on.
Pin DIAG can be used to signal the fault condition to a µC or to shut down the 3-phase bridge simply by connecting it to pin EN and adding an external R-C (see R
EN
, CEN).
18/33 Doc ID 018997 Rev 2
L6235Q Circuit description

Figure 19. Overcurrent protection simplified schematic

OUT
HIGH SIDE DMOS
I
1
n cells
I1/ n
OVER TEMPERATURE
μC or LOGIC
V
DD
POWER SENSE
LOGIC
R
DS(ON)
1 cell
INTERNAL
OPEN-DRAIN
TO GATE
R
EN
EN
C
EN
DIAG
40Ω TYP.
POWER DMOS
OCD
COMPARATOR
Figure 20 shows the overcurrent detection operation. The disable time t
1
I1+I2 / n
I
REF
I
REF
OUT
VS
2
A
I
2
POWER SENSE
+
POWER DMOS
n cells
I2/ n
I3/ n
1 cell
OUT3VS
I
3
POWER DMOS
DISABLE
B
n cells
before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected by both C reported in Figure 21. The delay time t
before turning off the bridge, when an
DELAY
overcurrent has been detected, depends only on the C
and REN values and its magnitude is
EN
value. Its magnitude is reported in
EN
Figure 22.
C
is also used for providing immunity to pin EN against fast transient noises. Therefore
EN
the value of C delay time and the R
The resistor R values for R
should be chosen as big as possible according to the maximum tolerable
EN
EN
and CEN are respectively 100 kΩ and 5.6 nF which allow to obtain 200 µs
EN
value should be chosen according to the desired disable time.
EN
should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
disable time.
SOMD EDIS HGIHSOMD EDIS HGIH
POWER SENSE
1 cell
AM02563v1
Doc ID 018997 Rev 2 19/33
Circuit description L6235Q

Figure 20. Overcurrent protection waveforms

I
OUT
I
SOVER
VEN=V
DIAG
V
DD
V
th(ON)
V
th(OFF)
ON
OCD
OFF
ON
BRIDGE
OFF
t
DELAY
V
EN(LOW)
t
DISABLE
t
OCD(ON)
t
EN(FALL)
t
D(OFF)EN
t
OCD(OFF)
t
EN(RISE)
t
D(ON)EN
AM02564v1
20/33 Doc ID 018997 Rev 2
L6235Q Circuit description
Figure 21. t
3
3
1.10
1.10
100
100
[µs]
[µs]
DISABLE
DISABLE
t
t
10
10
1
1
DISABLE
1 10 100
1 10 100
vs. CEN and REN (VDD = 5 V)
Ω
EN
EN
Ω
[n F ]
[n F ]
REN= 220 k
REN= 220 k
C
C
REN= 100 k
REN= 100 k
Ω
Ω
R
R
R
R
R
R
EN
EN
EN
EN
EN
EN
= 47 k
= 47 k
= 33 k
= 33 k
= 10 k
= 10 k
Ω
Ω Ω
Ω
Ω
Ω
Figure 22. t
s]
μ
tdelay [
vs. CEN (VDD = 5 V)
DELAY
10
1
0.1 1 10 100
Cen [nF]
Doc ID 018997 Rev 2 21/33
Circuit description L6235Q

4.8 Thermal protection

In addition to the overcurrent detection, the L6235Q integrates a thermal protection to prevent device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensitive element integrated in the die. The device switches off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).
22/33 Doc ID 018997 Rev 2
L6235Q Application information

5 Application information

A typical application using L6235Q is shown in Figure 23. Typical component values for the application are shown in Tab le 7 . A high quality ceramic capacitor (C 200 nF should be placed between the power pins (VS
and VSB) and ground near the
A
L6235Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors (C EN input to ground sets the shutdown time when an overcurrent is detected (see
Section 4.7). The two current sensing inputs (SENSE
to the sensing resistors R
with a trace length as short as possible in the layout. The
SENSE
and SENSEB) should be connected
A
sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see Section 2). It is recommended to keep power ground and signal ground separated on the PCB.

Table 7. Component values for typical application

Component Value
) in the range of 100 to
2
) connected from the
EN
C
1
C
2
C
3
C
BOOT
C
OFF
C
PUL
C
REF1
C
REF2
C
EN
10 nF
C
P
D
1N4148
1
1N4148
D
2
5K6Ω
R
1
R
1K8Ω
2
R
3
R
4
R
DD
R
EN
100 Ω
R
P
R
SENSE
R
OFF
R
PUL
R
H1, RH2, RH3
100 uF
100 nF
220 nF
220 nF
1 nF
10 nF
33 nF
100 nF
5.6 nF
4K7Ω
1 MΩ
1 KΩ
100 kΩ
0.3 Ω
33 kΩ
47 kΩ
10 kΩ
Doc ID 018997 Rev 2 23/33
Application information L6235Q

Figure 23. Typical application

8-52V
+
V
S
DC
POWER
GROUND
-
GROUND
SIGNAL
+5V
C1C
THREE-PHASE MOTOR
R
H1
R
H2
R
H3
2
HALL
SENSOR
C
BOOT
D
1
R
SENSE
M
VS
A
34, 35
VS
B
26, 27
C
P
R
P
VCP
VBOOT
OUT
OUT
OUT
GND
40
21
A
45, 46
B
15, 16
1
2, 3
2
38, 39
3
22, 23
H
1
43
H
2
41
H
3
42
6, 31
D
2
SENSE
SENSE
19
44
18
20
12
48
13
C
REF1
DIAG
EN
FWD/REV
BRAKE
TAC H O
RCOFF
RCPULSE
R
1
R
2
R
EN
C
EN
C
OFF
R
OFF
C
PUL
R
PUL
C
3
R
4
ENABLE
FWD/REV17
BRAKE
+FERV
-
V
C
REF2
R
3
R
DD
5V
AM02566v1
Note: To reduce the IC thermal resistance, therefore improving the dissipation path, the NC pins
can be connected to GND.
REF
24/33 Doc ID 018997 Rev 2
L6235Q Output current capability and IC power dissipation

6 Output current capability and IC power dissipation

Figure 24 shows the approximate relation between the output current and the IC power
dissipation using PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large the onboard copper dissipating area must be to guarantee a safe operating junction temperature (125 °C maximum).

Figure 24. IC power dissipation vs. output power

I
P
[W]
D
10
1
I
8
6
2
I
3
4
I
OUT
I
OUT
I
OUT
2
0
00.511.522.5 3
[A]
I
OUT
Test Condition s: Supply Voltage = 24 V
No PWM
fSW = 30 kHz (slow decay)
AM02570v1
Doc ID 018997 Rev 2 25/33
Thermal management L6235Q

7 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking configuration for the application is required to maintain the IC within the allowed operating temperature range for the application.
26/33 Doc ID 018997 Rev 2
L6235Q Electrical characteristics curves

8 Electrical characteristics curves

Figure 25. Typical quiescent current vs.
Iq [m A ]
5.6
5.4
5.2
5.0
4.8
4.6 0 102030405060
supply voltage
fsw = 1kHz Tj = 25°C
[V]
V
S
Tj = 85°C
Tj = 125°C
AM02572v1
Figure 27. Normalized typical quiescent
Iq / (Iq @ 1 k Hz)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
current vs. switching frequency
020406080100
f
[kHz]
SW
AM02574v1
Figure 26. Typical high-side R
DS(on)
voltage
R
[Ω]
DS(ON)
0.380
0.376
0.372
0.368
Tj = 25°C
0.364
0.360
0.356
0.352
0.348
0.344
0.340
0.336
0 5 10 15 20 25 30
[V]
V
S
Figure 28. Normalized R
vs. junction
DS(on)
temperature (typical value)
R
/ (R
DS(ON)
@ 25 °C)
Tj [°C]
DS(ON)
1.8
1.6
1.4
1.2
1.0
0.8 0 20406080100120140
vs. supply
AM02573v1
AM02575v1
Doc ID 018997 Rev 2 27/33
Electrical characteristics curves L6235Q
Figure 29. Typical low-side R
R
DS(ON)
voltage
[Ω]
DS(on)
vs. supply
0.300
0.296
0.292
Tj = 25°C
0.288
0.284
0.280
0.276 0 5 10 15 20 25 30
V
[V]
S
AM02576v1
Figure 30. Typical drain-source diode forward
ON characteristic
ISD[A]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
700 800 900 1000 1100 1200 1300
Tj = 25°C
V
[mV]
SD
AM02577v1
28/33 Doc ID 018997 Rev 2
L6235Q Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Table 8. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data

(mm)
Dim.
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.02 0.05
A2 0.65 1.00
A3 0.25
b 0.18 0.23 0.30
D 6.85 7.00 7.15
D2 4.95 5.10 5.25
E 6.85 7.00 7.15
E2 4.95 5.10 5.25
e 0.45 0.50 0.55
L 0.30 0.40 0.50
ddd 0.08
Doc ID 018997 Rev 2 29/33
Package mechanical data L6235Q

Figure 31. VFQFPN48 (7 x 7 x 1.0 mm) package outline

30/33 Doc ID 018997 Rev 2
L6235Q Order codes

10 Order codes

Table 9. Ordering information

Order codes Package Packaging
L6235Q
QFN48 7 x 7 x 1.0 mm
L6235QTR Tape and reel
Tr ay
Doc ID 018997 Rev 2 31/33
Revision history L6235Q

11 Revision history

Table 10. Document revision history

Date Revision Changes
30-Jul-2011 1 First release
28-Nov-2011 2 Document moved from preliminary to final datasheet
32/33 Doc ID 018997 Rev 2
L6235Q
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Doc ID 018997 Rev 2 33/33
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