THREE-PHASE BRUSHLESS DC MOTOR
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■ 5.6A OUTPUT PEAK CURRENT (2.8A DC)
■ R
■ OPERATING FREQUENCY UP TO 100KHz
■ NON DISSIPATIVE OVERCURRENT
DETECTION AND PROTECTION
■ DIAGNOSTIC OUTPUT
■
CONSTAN T t
■ SLOW DECAY SYNCHR. RECTIFICATION
■ 60° & 120° HALL EFFECT DECODING LOGIC
■ BRAKE FUNCTION
■ TACHO OUTPUT FOR SPEED LOOP
■ CROSS CONDUCTION PROTECTION
■ THERMAL SHUTDOWN
■ UNDERVOLTAGE LOCKOUT
■ INTEGRATED FAS T FREEWEELING DIO DES
DESCRIPTION
The L6235 is a DMOS Fully Integrated Three-Phase
Motor Driver with Overcurrent Protection.
Realized in MultiPower-BCD technology, the device
0.3Ω TYP. VA LUE @ Tj = 25 °C
DS(ON)
PWM CURRENT CONTROLLER
OFF
L6235
DMOS DRIVER FOR
PowerDIP24
(20+2+2)
L6235N L6235PD L6235D
combines isolated DMOS Power Transistors with
CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to drive a
three-phase BLDC motor including: a three-phase
DMOS Bridge, a constant off time PWM Current Controller and the decoding logic for single ended hall
sensors that generates the required s equence for the
power stage.
Available in PowerDIP24 (20+2+2), PowerSO36 and
SO24 (20+2+2) packages, the L6235 features a nondissipative overcurrent protection on the high side
Power MOSFETs and thermal shutdown.
PowerSO36
ORDERING NUMBERS:
SO24
(20+2+2)
BLOCK DIAGRAM
September 2003
VBOOT V
VCP
DIAG
EN
BRAKE
FWD/REV
H
3
H
2
H
1
RCPULSE
TACHO
BOOT
CHARGE
PUMP
TACHO
MONOSTABLE
10V 5V
VOLTAGE
REGULATOR
PROTECTION
OCD
HALL-EFFECT
SENSORS
DECODING
LOGIC
THERMAL
OCD1
OCD2
OCD
OCD3
ONE SHOT
MONOSTABLE
GATE
LOGIC
PWM
MASKING
TIME
V
BOOT
OCD1
10V
V
BOOT
OCD2
10V
V
BOOT
OCD3
10V
COMPARATOR
SENSE
VS
A
OUT
1
OUT
2
SENSE
A
VS
B
OUT
3
SENSE
B
+
-
VREF
RCOFF
D99IN1095B
1/25
L6235
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Test conditions Value Unit
V
V
OD
V
BOOT
VIN, V
V
REF
V
RCOFF
V
RCPULSE
V
SENSE
I
S(peak)
I
S
, T
T
stg
Supply Voltage VSA = VSB = V
S
Differential Voltage between:
, OUT1, OUT2, SENSEA
VS
A
and VSB, OUT3, SENSE
B
VSA = VSB = VS = 60V;
V
SENSEA
Bootstrap Peak Voltage VSA = VSB = V
Logic Inputs Voltage Range -0.3 to 7 V
EN
= V
S
SENSEB
S
= GND
60 V
60 V
VS + 10 V
Voltage Range at pin VREF -0.3 to 7 V
Voltage Range at pin RCOFF -0.3 to 7 V
Voltage Range at pin RCPULSE -0.3 to 7 V
Voltage Range at pins SENSEA
and SENSE
B
Pulsed Supply Current (for each
and VSB pin)
VS
A
DC Supply Current (for each
and VSB pin)
VS
A
Storage and Operating
OP
V
= VSB = VS; T
SA
V
= VSB = V
SA
S
< 1ms 7.1 A
PULSE
-1 to 4 V
2.8 A
-40 to 150 °C
Temperature Range
RECOMMENDED OPERATING CONDITION
Symbol Parameter Test Conditions MIN MAX Unit
V
V
V
V
SENSE
I
OUT
T
f
SW
OD
REF
Supply Voltage VSA = VSB = V
S
Differential Voltage between:
, OUT1, OUT2, SENSEA and
VS
A
VS
, OUT3, SENSE
B
B
VSA = VSB = VS;
V
SENSEA
= V
SENSEB
S
12 52 V
Voltage Range at pin VREF -0.1 5 V
Voltage Range at pins SENSEA
and SENSE
B
DC Output Current VSA = VSB = V
Operating Junction Temperature -25 125 °C
J
(pulsed tW < trr)
(DC)
-6
-1
S
Switching Frequency 100 KHz
52 V
6
1
2.8 A
V
V
2/25
THERMA L D ATA
Symbol Description PDIP24 SO24
PowerSO36
L6235
Unit
R
th(j-pins)
R
th(j-case)
R
th(j-amb)1
R
th(j-amb)1
R
th(j-amb)1
R
th(j-amb)2
Maximum Thermal Resistance Junction-Pins 18 14 °C/W
Maximum Thermal Resistance Junction-Case 1 °C/W
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
(1)
(2)
(3)
(4)
43 51 - °C/W
--35°C/W
--15°C/W
58 77 62 °C/W
(1) Mount ed on a multi-l ayer FR4 PCB wi t h a di ssipating copper sur face on the bottom side of 6 c m2 (with a thickness of 35 µm) .
(2) Mount ed on a multi-l ayer FR4 PCB wi t h a di ssipating copper sur face on the top side of 6 cm2 (with a thi ck ness of 35 µm) .
(3) Mounted on a multi-layer F R4 PCB with a di ssipating copper sur face on the top s id e of 6 cm2 (with a thi ck ness of 35 µm),
16 via holes and a ground layer.
(4) Mounted on a mult i- l ayer FR4 PCB wi t h out any heat-sinking surface on the board.
PIN CONNECTIONS (Top view)
H
DIAG
SENSE
RCOFF
OUT
GND
GND
TACHO
RCPULSE
SENSE
FWD/REV
EN
1
1
2
3
A
4
5
1
6
7
8
9
10
B
11
12
D01IN1194A
PowerDIP24/SO24
GND
N.C.
H
24
3
H
23
2
VCP
22
OUT
21
20
VS
2
A
N.C.
VS
OUT
N.C.
VCP
GND19
GND
18
17
VS
16
15
14
13
B
OUT
3
VBOOT
BRAKE
VREF
DIAG
SENSE
RCOFF
N.C.
OUT
N.C.
N.C.
GND
2
3
4
A
5
2
7
H
8
2
H
3
H
10
1
11
12
A
13
14
15
1
16
17
18
D01IN1195A
PowerSO36
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
(5)
GND1
N.C.
N.C.
VS
B
OUT
3
N.C.6
VBOOT
BRAKE
VREF9
EN
FWD/REV
SENSE
B
RCPULSE
N.C.
TACHO
N.C.
N.C.
GND
(5) The slug is internal l y connected to pins 1, 18, 19 and 36 (GND pi ns).
3/25
L6235
PIN DESCRIPTION
P ACKAGE
SO24/
PowerDIP24
PowerSO36
PIN # PIN #
110H
2 11 DIAG Open Drain
3 12 SENSE
4 13 RCOFF RC Pin RC Network Pin. A parallel RC network connected
5 15 OUT
6, 7,
18, 19
1, 18,
19, 36
8 22 TACHO Open Drain
9 24 RCPULSE RC Pin RC Network Pin. A parallel RC network connected
10 25 SENSE
11 26 FWD/REV Logic Input Selects the direction of the rotation . HIGH logic level
12 27 EN Lo gic Input Chip Enable. LOW log ic level switches OFF a ll Power
13 28 VREF Logic Input Current Controller Reference Voltage.
14 29 BRAKE Logic Input Brake Input pin. LOW logic level switches ON all High
15 30 VBOOT Supply Voltage Bootstrap Voltage needed for driving the u pper Power
16 32 OUT
17 33 VS
Name Type Function
1
Sensor Input Single Ended Hall Effect Sensor Input 1.
Overcurrent Detect ion an d The r mal P rotec tion p in. An
Output
internal open drain transistor pulls to GND when an
overcurrent on one of the High Side MOSFETs is
detected or during Thermal Protection.
Power Supply Half Bridge 1 and Half Bridge 2 Source Pin. This pin
A
must be connected together with pin SENSE
Power Ground through a sensing power resistor.
between this pin and ground sets the Current
Controller OFF-Time.
Power Output Output 1
1
GND GND Ground terminals. On PowerDIP24 and SO24
packages, these pins are also used for heat
dissipation toward the PCB. On PowerSO36 package
the slug is connected on these pins.
Frequency-to-Voltage open drain output. E very pulse
Output
from pin H
is shaped as a fixed and adjustable length
1
pulse.
between this p in and ground sets th e duration of the
Monostable Pulse used for the Frequency-to-Voltage
converter.
Power Supply Half Bridge 3 S ource Pin. This pin mu st be conn ected
B
together with p in SEN SE
to Power Ground through a
A
sensing power resistor. At this pin also the Inverting
Input of the Sense Comparator is connected.
sets Forward Operation, whereas LOW logic level sets
Reverse Operation.
If not used, it has to be connected to GND or +5V..
MOSFETs.
If not used, it has to be connected to +5V.
Do not leave this pin open or connect to GND.
Side Power MOSFETs, implementing the Brake
Function.
If not used, it has to be connected to +5V.
MOSFETs.
Power Output Output 3.
3
Power Supply Half Bridge 3 Power Supply Voltage. It must be
B
connected to the supply voltage together with pin VS
B
to
.
A
4/25
L6235
PIN DESCRIPTION
(continued)
PACKAGE
SO24/
PowerDIP24
PowerSO36
Name Type Function
PIN # PIN #
20 4 VS
Power Supply Half Bridge 1 and Half Bridge 2 Power Supply Voltage.
A
It must be connected to the supply voltage together
.
B
21 5 OUT
Power Output Output 2.
2
with pin VS
22 7 VCP Output Charge Pump Oscillator Output.
23 8 H
24 9 H
2
3
Sensor Input Single Ended Hall Effect Sensor Input 2.
Sensor Input Single Ended Hall Effect Sensor Input 3.
ELECTRICAL CHARACTERISTICS
(VS = 48V , T
Symbol Parameter Test Conditions Min Typ Max Unit
V
Sth(ON)
V
Sth(OFF)
I
S
T
J(OFF)
Output DMOS Transistors
R
DS(ON)
I
DSS
Source Drain Diodes
V
SD
t
rr
t
fr
Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE)
V
IL
V
IH
I
IL
I
IH
V
th(ON)
V
th(OFF)
V
thHYS
= 25 °C , unless otherwise specified)
amb
Turn ON threshold 6.6 7 7.4 V
Turn OFF threshold 5.6 6 6.4 V
Quiescent Supply Current All Bridges OFF;
Tj = -25 to 125°C
(6)
510mA
Thermal Shutdown Temperature 165 °C
High-Side Switch ON Resistance Tj = 25 °C 0.34 0.4 Ω
(6)
(6)
Low-Side Switch ON Resistance T
=125 °C
T
j
= 25 °C 0.28 0.34 Ω
j
=125 °C
T
j
Leakage Current EN = Low; OUT = V
CC
0.53 0.59 Ω
0.47 0.53 Ω
2mA
EN = Low; OUT = GND -0.15 mA
Forward ON Voltage ISD = 2.8A, EN = LOW 1.15 1.3 V
Reverse Recovery Time If = 2.8A 300 ns
Forward Recovery Time 200 ns
Low level logic input voltage -0.3 0.8 V
High level logic input voltage 2 7 V
Low level logic input current GND Logic Input Voltage -10 µA
High level logic input current 7V Logic Input Voltage 10 µA
Turn-ON Input Threshold 1.8 2.0 V
Turn-OFF Input Threshold 0.8 1.3 V
Input Thresholds Hysteresy s 0.25 0.5 V
5/25
L6235
ELECTRICAL CHARACTERISTICS
(V
= 48V , T
S
= 25 °C , unless otherwise specified)
amb
(continued)
Symbol Parameter Test Conditions Min Typ Max Unit
Switching Characteristics
(7)
I
t
D(on)EN
t
D(off)EN
t
D(on)IN
Enable to out turn-ON delay time
Enable to out turn-OFF delay time
Other Logic Inputs to Output Turn-
(7
)
= 2.8 A, Resistive Load 110 250 400 ns
LOAD
I
= 2.8 A, Resistive Load 300 550 800 ns
LOAD
I
= 2.8 A, Resistive Load 2 µs
LOAD
ON delay Time
t
D(off)IN
Other Logic Inputs to out Turn-OFF
I
= 2.8 A, Resistive Load 2 µs
LOAD
delay Time
(7)
(7)
I
= 2.8 A, Resistive Load 40 250 ns
LOAD
I
= 2.8 A, Resistive Load 40 250 ns
LOAD
Tj = -25 to 125°C
(6)
0.6 1 MHz
t
RISE
t
FALL
t
DT
f
CP
Output Rise Time
Output Fall Time
Dead Time 0.5 1 µs
Charge Pump Frequency
PWM Comparator and Monostable
I
RCOFF
V
OFFSET
Source current at pin RC
Offset Voltage on Sense
V
OFF
V
= 2.5 V 3.5 5.5 mA
RCOFF
= 0.5 V ±5 mV
ref
Comparator
t
prop
t
blank
Turn OFF Propagation delay
Internal Blanking Time on Sense
(8)
V
= 0.5 V 500 ns
ref
1µs
Comparator
t
ON(min)
t
I
BIAS
Minimum on Time
PWM Recirculatio nTim e R
OFF
OFF
R
OFF
= 20kΩ ; C
= 100kΩ ; C
OFF
OFF
=1nF
=1nF
1.5 2 µs
13
61
Input Bias Current at pin VREF 10 µA
Tacho Monostable
I
RCPULSE
t
PULSE
R
TACHO
Source Current at pin RCPULSE V
Monostable of Time R
RCPULSE
PUL
R
PUL
Open Drain ON Resistance 40 60 Ω
= 2.5V 3.5 5.5 mA
= 20kΩ ; C
= 100kΩ ; C
PUL
PUL
=1nF
=1nF
12
60
Over Current Detection & Protection
I
SOVER
R
OPDR
t
OCD(ON)
t
OCD(OFF)
(6) Teste d at 2 5°C in a restricted range and guaranteed by ch aracterization.
(7) See Fig. 1.
(8) Measured applying a voltage of 1V to pin SEN S E and a voltage drop from 2V t o 0V to pin VREF.
(9) See Fig. 2.
Supply Overcurrent Protection
Threshold
Open Drain ON Resistance I
OCD high level leakage current V
I
OH
OCD Turn-ON Delay Time
OCD Turn-OFF Delay Time
(9)
(9)
= -25 to 125°C
T
J
= 4mA 40 60 Ω
DIAG
= 5V 1 µA
DIAG
I
= 4mA; C
DIAG
I
= 4mA; C
DIAG
(6)
< 100pF 200 ns
DIAG
< 100pF 100 ns
DIAG
4.0 5.6 7.1 A
µs
µs
µs
µs
6/25
Figure 1. Switching Characteristic Definition
EN
V
th(ON)
V
th(OFF)
I
OUT
90%
10%
D01IN1316
t
D(OFF)EN
t
FALL
Figure 2. Ove rcurrent Detect i on Timi ng Definition
I
OUT
I
SOVER
t
D(ON)EN
t
RISE
L6235
t
t
ON
BRIDGE
OFF
V
DIAG
90%
10%
t
OCD(ON)
t
OCD(OFF)
D02IN1387
7/25
L6235
8
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6235 integrates a Three-Phase Bridge, which
consists of 6 Power MOSFETs connected as shown
on the Block Diagram. Each Power MOS has an
R
= 0.3Ω (typical value @25°C) with intrinsic
DS(ON)
fast freewheeling diode. Switching patterns are generated by the PWM Current Controller and the Hall
Effect Sensor Decoding Logic (see relative paragraphs). Cross conduc tion protec tion is impl emented
by using a dead time (t
= 1µs typical value) set by
DT
internal timing circuit between the turn off and turn on
of two Power MOSFETs in one leg of a bridge.
Pins VS
the supply voltage (V
and VSB MUST be connected together to
A
).
S
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped Supply
(V
) is obtained through an internal osci llator and
BOOT
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output (pin
VCP) is a squar e wave at 600K Hz (typi cally) wi th 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
LOGIC INPUTS
Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/
CMOS and µC compatible logic inputs. The internal
structure is shown in Figure 4. Typical value for turnON and turn-OFF thresholds are respectively V
= 1.8V and V
th(OFF)
= 1.3V.
th(ON )
Pin EN (enable) may be used to implement Overc urrent
and Thermal protection by connect ing it to t he open collector DIAG output If the protecti on and an exter nal disable function are both desired, the appropriate
connection must be implemented. When the external
signal is from an open col lect or output, the circui t in Figure 5 can be used . For external circuits that are push
pull outp uts t he circui t in Figur e 6 coul d be us ed. The resistor R
180K
spectively 100K
should be chosen in the rang e from 2.2KΩ to
EN
Ω
. Recommended values for REN and CEN are re-
Ω
and 5.6nF. More information for selecting the values can be found in the Overcurrent
Protection section.
Figure 4. Logi c Inp ut Int ernal Structu re
5V
Table 1. Charge Pump External Component
Values.
C
C
R
D
D
BOOT
P
P
1
2
220nF
10nF
100Ω
1N4148
1N4148
Figure 3. Char ge Pump Circu it
V
S
D1
D2
R
P
C
P
VCP VBOOT VS
C
BOOT
VS
B
D01IN1328
A
ESD
PROTECTION
D01IN1329
Figure 5. Pin EN Open Collector Driving
DIAG
5V
EN
EN
ESD
PROTECTION
OPEN
COLLECTOR
OUTPUT
5V
R
EN
C
Figure 6. Pin EN Push-Pull Driving
DIAG
5V
R
PUSH-PULL
OUTPUT
EN
C
EN
EN
ESD
PROTECTION
D02IN137
D02IN1379
8/25
L6235
PWM CURRENT CONTROL
The L6235 includes a constant off time PWM Current Controller. The current control circuit senses the bridge
current by sensing the voltage drop across an external sense resistor connected between the source of the
three lower power MOS transistors and ground, as show n in Figure 7. As the c urrent i n the motor increas es the
voltage across the sense resistor increas es proportionally. When the voltage drop across the sense resis tor becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable
switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current
recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section. When the
monostable times o ut, the brid ge wi ll aga in turn on. Si nce the internal dead time, used to prevent cross c onduction in the bridge, delays the turn on of the power MOS, the effective Off Time t
time plus the dead time.
Figure 8 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the pin RC vol tage and the status of the bridge. More d etails regarding the S ynchronous Rectificati on and
the output stage configuration are included in the next section.
Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the reverse recovery of the freewheeling diodes. The L6235 provides a 1µs Blanking Time t
comparator output so that the current spike cannot prematurely retrigger the monostable.
Figure 7. PWM Current Controller Simplified Schematic
is the sum of the monostable
OFF
that inhibits the
BLANK
VS
OUT
OUT
OUT
2
3
1
DRIVERS
+
DEAD TIME
A
D02IN1380
VS
A
VS
B
TO GATE
LOGIC
5mA
S
(0) (1)
5V
RCOFF
C
OFF
R
Q
R
-
+
2.5V
OFF
BLANKING TIME
MONOST ABLE
1µs
MONOST ABLE
SET
COMP ARAT OR
BLANKER
SENSE
FROM THE
LOW-SIDE
GATE DRIVERS
DRIVERS
+
DEAD TIME
+
-
VREF
R
SENSE
SENSE
DRIVERS
+
DEAD TIME
B
SENSE
9/25
L6235
Figure 8. Output Current Regulation Waveforms
I
OUT
V
REF
R
SENSE
V
SENSE
V
REF
0
V
RC
5V
2.5V
ON
SYNCHRONOUS RECTIFICATION
OFF
D02IN1351
Figure 9 shows the magnitude of the Off Time t
BC
OFF
culated from the equations:
t
t
where R
20K
0.47nF ≤ C
t
= 0.6 · R
RCFALL
= t
OFF
RCFALL
and C
OFF
Ω ≤
= 1µs (typical value)
DT
R
OFF
OFF
OFF
· C
OFF
+ tDT = 0.6 · R
OFF
· C
OFF
+ t
OFF
are the external component values and tDT is the internally generated Dead Time with:
≤ 100K
Ω
≤ 100nF
Therefore:
t
OFF(MIN)
t
OFF(MAX)
These values allow a sufficient range of t
The capacitor value chosen for C
Rise Ti me t
= 6.6µs
= 6ms
to implement the drive circuit for most motors.
OFF
also affects the Rise Time t
will only be an issue if the capacitor is not completely charged before the next time the
RCRISE
OFF
monostable is triggered. Therefore, the On Time t
be bigger than t
can not be smaller than the minimum on time t
for allowing a good current regulation by the P WM stage. Further more, the On Time t
RCRISE
ON(MIN)
t
OFF
1µs t
BLANK
Slow Decay Slow Decay
t
RCRISE
t
RCFALL
1µs t
DT
versus C
DT
, which depends by motors and supply parameters, has to
ON
t
ON
DDA
and R
OFF
OFF
of the voltage at the pin RCOFF. The
RCRISE
t
OFF
1µs t
BLANK
t
RCRISE
t
RCFALL
1µs t
DT
BC
values. It can be approximately cal-
.
ON
10/25
t
> 1.5µs (typ. value)=
ONtON MIN()
t
ONtRCRISEtDT
RCRISE
= 600 · C
t
–>
OFF
L6235
Figure 10 shows the lower limit for the On Time tON for having a good PWM current regulation capacity. It has
to be said that t
than t
RCRISE
So, small C
switching frequency), but, the smaller is the value for C
performance.
is always bigger than t
ON
ON(MIN)
- tDT. In this last case the device continues to work but the Off Time t
value gives more flexibility for the applications (allows smaller On Time and, therefore, higher
OFF
because the device imposes this condition, but it can be smaller
is not more constant.
OFF
, the more influential will be the noises on the circuit
OFF
Figure 9. t
versus C
OFF
and R
OFF
4
1.10
3
1.10
100
toff [µs]
10
1
0.1 1 10 100
OFF
.
= 100k
R
off
Ω
= 47k
R
off
Ω
= 20k
R
off
Coff [nF]
Ω
Figure 10. Area where tON can vary maintaining the PWM regulation.
100
s]
µ
10
ton(min) [
1.5µs (typ. value)
1
0.1 1 10 100
Coff [nF]
11/25
L6235
SLOW DECAY MODE
Figure 11 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two
legs of the three-phas e br idge are acti ve, therefor e only the two acti ve l egs of the br idge are s hown in the figure
and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current
recirculates around the upper half of the bridge. Sinc e the voltage across the coil is low, th e current decays slowly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the
impendence of the freewheeling diode and the related conducting losses. When the monostable times out, upper MOS that was operating the sync hronous mode turns off and the lower power MOS is turned o n again after
some delay set by the Dead Time to prevent cross conduction.
Figure 11. Slow Decay Mode Output Stage Configurations
A) ON TIME B) 1µs DEAD TIME C) SYNCHRONOUS
D01IN1336
RECTIFICATION
D) 1µs DEAD TIME
DECODING LOGIC
The Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase
bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3phase BLDC motor. This novel combinatory logic disc riminates between the actual sensor positi ons for sensors
spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a universal IC without dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 12, positions 1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical degrees phasing (see Figure 14, positions 1, 2, 3b, 4, 5
and 6b). Four of them ar e in c ommon (1, 2, 4 a nd 5) w hereas ther e are tw o combi nations used on ly i n 120 electrical degrees sensor phasing (3 a and 6a) and two combinations us ed only in 60 electrical degrees sensor phasing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the Table 2. For any input
configuration (H
, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configura-
1
tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electr ica l degrees phas ing is the rever se of 60 a nd the sequenc e of the
Hall codes for 240 phasing is the r everse of 120. So, by decoding t he 60 and the 120 codes it is pos sible to drive
the motor with all the four conventions by changing the direction set.
12/25
Table 2. 60 and 120 Electrical Degree Decoding Logic in Forward Direction.
Hall 120° 1 2 3a - 4 5 6a -
Hall 60° 1 2 - 3b 4 5 - 6b
L6235
H
1
H
2
H
3
OUT
1
OUT
2
OUT
3
HH L H L LHL
LH H H H LLL
LL L HHHHL
Vs High Z GND GND GND High Z Vs Vs
High Z Vs Vs Vs High Z GND GND GND
GND GND High Z High Z Vs Vs High Z High Z
Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2
Figure 12. 120° Hall Sensor Sequence.
H1
H3 H2
H1
H2 H2 H2 H2 H2 H3 H3 H3 H3 H3
H1 H1 H1 H1
1 2 3a 4 5 6a
= H
= L
Figure 13. 60° Hall Sensor Sequence.
H1 H1
H2 H2 H2 H2 H2
H3
H2
H3 H3 H3 H3 H3
1 2 3b 4 5 6b
= H
= L
H1 H1 H1 H1
13/25
L6235
TACHO
A tachometer function consists of a monostable, with constant off time (t
signal (H
). It allows developing an easy speed control loop by using an external op amp, as shown in Figure
1
14. For component values refer to Application Information section.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall Effect Sensors
, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time
H
1
t
(see Figure 15). The off time t
PULSE
to the pin RCPULSE. Figure 16 gives the relation between t
t
PULSE
where C
= 0.6 · R
should be chosen in the range 1nF … 100nF and R
PUL
PUL
· C
PUL
can be set using the external RC network (R
PULSE
PULSE
and C
in the range 20KΩ … 100KΩ.
PUL
By connecting the tachometer pin to an external pull-up resistor, the output signal average value V
tional to the frequency of the Hall Effect signal and, therefore, to the motor speed. This realizes a simple Frequency-to-Voltage Converter. An op amp, configured as an integrator, filters the signal and compares it with a
reference voltage V
t
PULSE
----------------- -
V
M
, which sets the speed of the motor.
REF
V
⋅=
T
DD
Figure 14. Tacho Operation Waveforms.
), whose input is one Hall Effect
PULSE
, C
PUL
PUL
PUL
, R
. We have approximately:
PUL
) connected
is propor-
M
V
H1
H
H
TACHO
VM
2
3
t
PULSE
VDD
T
14/25
Figure 15. Tachometer Speed Control Loop.
L6235
H
1
Figure 16. t
PULSE
V
REF
vers u s C
PUL
1.10
C
REF2
and R
4
RCPULSE
V
DD
C
R
PUL
R
1
4
PUL
DD
R
1
R
2
.
R
3
C
R
PUL
TACHO
VREF
C
REF1
R
PUL
= 100k
MONOSTABLE
Ω
TACHO
Ω
= 47k
R
3
1.10
= 20k
R
PUL
tpulse [µs]
100
10
1 10 100
PUL
Ω
Cpul [nF]
15/25
L6235
NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTION
The L6235 integrates an Ov ercurrent Detec tion Cir cuit (OCD) for full pr otection. This cir cuit pr ovides Output-toOutput and Output-to-Ground short c ircuit pro tection as well. Wi th this internal over cur rent detec tion, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 17 shows
a simplified schematic for the overcurrent detection circuit.
To implement the over current detection, a sensing element that deli ver s a small but precise fraction of the output current is implemented with each High Side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference current I
ator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a
by connecting it to pin EN and adding an external R-C (see R
Figure 17. Overcurrent Protection Simplified Schematic
. When the output current reaches the detection threshold (typically I
REF
µ
C or to shut down the Three-Phase Bridge simply
, CEN).
EN
OUT
VS
OUT
1
2
A
= 5.6A) the OCD compar-
SOVER
OUT3VS
B
HIGH SIDE DMOS
I
1
µC or LOGIC
V
DD
POWER SENSE
DS(ON)
1 cell
INTERNAL
OPEN-DRAIN
TO GATE
LOGIC
R
C
EN
EN
EN
DIAG
R
40Ω TYP.
POWER DMOS
OCD
COMPARATOR
n cells
I1 / n
I1+I2 / n
I
REF
OVER TEMPERATURE
I
REF
Figure 18 shows the Overcurrent Detetection operation. The Disable Time t
HIGH SIDE DMOS HIGH SIDE DMOS
+
I
2
POWER DMOS
n cells
I2/ n
POWER SENSE
1 cell
I3/ n
D02IN1381
DISABLE
I
POWER DMOS
before recovering normal
3
POWER SENSE
n cells
1 cell
operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected
whether by C
ing off the bridge when an overcurr ent has been detected depends o nly b y C
and REN values and its magni tude is reporte d in Figure 19 . The Del ay Time t
EN
value. Its magni tude is reported
EN
DELAY
before turn-
in Figure 20.
C
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
EN
should be chosen as big as possi ble acc or ding to the maximum tolerable D elay Time and th e REN value should
be chosen according to the desired Disable Time.
The resistor R
should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and C
EN
EN
are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time.
16/25
Figure 18. Overcurrent Protection Wavefo rms
I
OUT
I
SOVER
VEN=V
DIAG
V
DD
V
th(ON)
V
th(OFF)
ON
OCD
OFF
ON
t
BRIDGE
OFF
t
OCD(ON)
DELAY
t
EN(FALL)
t
D(OFF)EN
t
OCD(OFF)
V
EN(LOW)
t
DISABLE
t
EN(RISE)
t
D(ON)EN
L6235
D02IN1383
Figure 19. t
Figure 20. t
DISABLE
versus CEN.
DELAY
versus CEN and REN.
3
3
1.10
1.10
100
100
[µs]
[µs]
DISABLE
DISABLE
t
t
10
10
1
1
1 10 100
1 10 100
10
1
tdelay [µs]
REN= 220 k
REN= 220 k
CEN[nF ]
CEN[nF]
Ω
Ω
REN= 100 k
REN= 100 k
Ω
Ω
R
R
R
R
R
R
EN
EN
EN
EN
EN
EN
= 47 k
= 47 k
= 33 k
= 33 k
= 10 k
= 10 k
Ω
Ω
Ω
Ω
Ω
Ω
0.1
1 10 100
Cen [nF]
17/25
L6235
APPLICATION INFORMATION
A typical application us ing L6235 is show n in Figure 21. Typical co mponent values for the applic ation are shown
in Table 3. A high quality ceramic capacitor (C
power pins VS
and VSB and ground near the L6235 to impr ove the high frequency fi ltering on the power suppl y
A
and reduce high frequency transients generated by the switching. The capacitor (C
input to ground sets the shut down time when an over current is detected ( see Overcurrent Protecti on). The tw o
current sensing inputs ( SENSE
and SENSEB) should be connected to the s ensing resistor R
A
length as short as possible i n the layout. The se nse r esistor s hould be non-inducti ve r esis tor to minimiz e the di/
dt transients across the res istor. To increase noi se immuni ty, unused logi c pins ar e best conn ected to 5V (High
Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and
Signal Ground separated on PCB.
Table 3. Component Values for Typical Application.
C
C
C
C
C
C
1
C
2
C
3
BOOT
OFF
PUL
REF1
REF2
C
EN
C
P
D
1
D
2
100µF R
100nF R
220nF R
220nF R
1nF R
10nF R
33nF R
100nF R
5.6nF R
10nF R
1N4148 RH1, RH2, R
1N4148
) in the range of 100nF to 200nF should be placed between the
2
) connected from the EN
EN
with a trace
SENSE
1
2
3
4
DD
EN
P
SENSE
OFF
PUL
H3
5K6Ω
1K8Ω
4K7Ω
1MΩ
1KΩ
100KΩ
100Ω
0.3Ω
33KΩ
47KΩ
10KΩ
Figure 21. Typical Application
+
V
S
C
C
1
8-52V
DC
POWER
GROUND
-
SIGNAL
GROUND
+5V
2
THREE-PHASE MOTOR
SENSOR
R
H1
R
H2
R
H3
HALL
C
BOOT
D
1
R
SENSE
M
VS
A
20
VS
B
17
C
P
R
VCP
P
D
2
VBOOT
SENSE
SENSE
OUT
OUT
OUT
GND
22
15
A
3
B
10
1
5
2
21
3
16
H
1
1
H
2
23
H
3
24
18
19
6
7
D02IN1357
VREF +
13
C
REF1 R
DIAG
2
EN
12
FWD/REV
14
BRAKE
8
TACHO
RCOFF
4
RCPULSE
9
R
1
2
R
EN
C
EN
C
OFF
R
OFF
C
PUL
R
PUL
C
3
R
4
ENABLE
FWD/REV11
BRAKE
-
V
REF
C
REF2
R
3
R
DD
5V
18/25
L6235
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Figure 22 is shown the approximate relation between the output current and the IC power dissipation using
PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which
package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum).
Figure 22. IC Power Dissipation versus Output Power.
I1
I
OUT
10
I
8
P
[W]
D
6
4
2
2
I
3
Test Conditions:
I
OUT
I
OUT
Supply Voltage = 24 V
I
OUT
[A]
No PWM
fSW = 30 kHz (slow decay)
0
0 0.5 1 1.5 2 2.5 3
THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the devi ce in a safe operating condition. S electing th e appropriate pack age and heatsi nking configuration for the application is required to maintain the IC within the allowed operating temperature range for
the application. Figures 23, 24 and 25 show the Junction-to-Ambient Thermal Resistance values for the
PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
with 6c m
2
dissipating footprint (copper thickness of 35µm), the R
th(j-amb)
is about 35°C/W. Figure 26 shows
mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance
can be reduced down to 15°C/W.
Figure 23. PowerSO36 Junction -Am bient thermal resi stance versus on-bo ard co pper area.
ºC / W
43
38
33
28
23
18
13
12345678910111213
Without Ground Layer
With Ground Layer
With Ground Layer+16 via
Holes
sq. cm
On-Board Copper Area
19/25
L6235
Figure 24. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
49
48
47
46
45
44
43
42
41
40
39
1 2 3 4 5 6 7 8 9 101112
Copper Area is on Bottom
Side
Copper Area is on To p Side
sq. cm
On-Board Copper Area
Figure 25. SO24 Junction-Ambient thermal resi stance versus on-bo ard copp er area.
ºC / W
68
66
64
62
60
58
56
54
52
50
48
123456789101112
Copper Area is on Top Side
sq. cm
On-Board Copper Area
Figure 26. Mounting the PowerSO Packag e.
Slug soldered
20/25
to PCB with
dissipating area
dissipating area
plus ground layer
Slug soldered
to PCB with
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
L6235
Figure 27. Typical Quiescent Current vs.
Supply Voltage
Iq [mA ]
5.6
5.4
fsw = 1kHz Tj = 25°C
Tj = 85°C
Tj = 125°C
5.2
5.0
4.8
4.6
0 102030405060
[V]
V
S
Figure 28. Normalized Typical Quiescen t
Current vs. Switching Frequency
Iq / (Iq @ 1 kHz)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0 20406080100
[kHz]
f
SW
Figure 30. Ty pi c al Hi gh-Side R
DS(ON)
vs.
Supply Voltage
R
[Ω]
DS(ON)
0.380
0.376
0.372
0.368
0.364
0.360
0.356
0.352
0.348
0.344
0.340
0.336
0 5 10 15 20 25 30
Figure 31. Nor m ali ze d R
Tj = 25°C
[V]
V
S
DS(ON)
vs.Junction
Temperature (typical value)
/ (R
R
DS(ON)
1.8
1.6
1.4
1.2
1.0
0.8
0 20406080100120140
DS(ON)
@ 25 °C)
Tj [°C]
Figure 29. Typical Low-Side R
DS(ON)
Voltage
[Ω]
R
DS(ON)
0.300
0.296
Tj = 25°C
0.292
0.288
0.284
0.280
0.276
0 5 10 15 20 25 30
V
[V]
S
vs. Supply
Figure 32. Typical Drain-Source Diode Forward
ON Characteristic
I
[A]
SD
3.0
2.5
2.0
1.5
1.0
0.5
0.0
700 800 900 1000 1100 1200 1300
Tj = 25°C
[mV]
V
SD
21/25
L6235
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A 3.60 0.141
a1 0.10 0.30 0.004 0.012
a2 3.30 0.130
a3 0 0.10 0 0.004
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D (1) 15.80 16.00 0.622 0.630
D1 9.40 9.80 0.370 0.385
E 13.90 14.50 0.547 0.570
e 0.65 0.0256
e3 11.05 0.435
E1 (1) 10.90 11.10 0.429 0.437
E2 2.90 0.114
E3 5.80 6.20 0.228 0.244
E4 2.90 3.20 0.114 0.126
G 0 0.10 0 0.004
H 15.50 15.90 0.610 0.626
h 1.10 0.043
L 0.80 1.10 0.031 0.043
N10°(max.)
S8°(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
OUTLINE AND
MECHANICAL DATA
PowerSO36
NN
a2
A
1936
0.12 AB
⊕
e
M
E1
DETAIL B
lead
a3
B
Gage Plane
PSO36MEC
BOTTOM VIEW
DETAIL B
0.35
S
E
DETAIL A
L
(COPLANARITY)
E2
h x 45˚
DETAIL A
118
A
e3
H
D
b
c
a1
slug
E3
D1
- C -
SEATING PLANE
GC
22/25
L6235
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.320 0.170
A1 0.380 0.015
A2 3.300 0.130
B 0.410 0.460 0.510 0.016 0.018 0.020
B1 1.400 1.520 1.650 0.055 0.060 0.065
c 0.200 0.250 0.300 0.008 0.010 0.012
D 31.62 31.75 31.88 1.245 1.250 1.255
E 7.620 8.260 0.300 0.325
e 2.54 0.100
E1 6.350 6.600 6.860 0.250 0.260 0.270
e1 7.620
L 3.180 3.430 0.125 0.135
M 0˚ min, 15˚ max.
mm inch
0.300
OUTLINE AND
MECHANICAL DATA
Powerdip 24
E1
A2
A
13
12
A1
SDIP24L
e1
c
M
L
B eB1
D
24
1
23/25
L6235
DIM.
MIN. TYP. MAX . MIN. TY P. MAX.
A 2 .35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0 .33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
(1)
15.20 15.60 0.598 0.614
D
E 7 .40 7.60 0.291 0.299
e 1.2 7 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0;75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “ D” dime nsion d o es not i n c l u de mold flash, prot u s ions or gate
burrs. Mo ld f las h, p rotus ion s or g at e bur rs sh all not exce ed
0.15mm per side.
mm inch
OUTLINE AND
MECHANICAL DA TA
Weight: 0.60gr
SO24
24/25
0070769 C
L6235
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwis e under any patent or patent r ights of S T M i croelectronics. Specifications me ntioned in this pub lication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authoriz ed for use as cri tical comp onents in life support devices or sy st em s without express written appr oval of STMic roelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMi croelectronics - All ri ghts reser ved
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25/25
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