ST L6229Q User Manual

DMOS driver for three-phase brushless DC motor

Features

■ Operating supply voltage from 8 to 52 V

■ 2.8 A output peak current (1.4 A RMS)

■ R

■ Operating frequency up to 100 kHz

■ Non dissipative overcurrent detection and

protection

■ Diagnostic output

■ Constant t

■ Slow decay synchronous rectification

■ 60° and 120° hall effect decoding logic

■ Brake function

■ Cross conduction protection

■ Thermal shutdown

■ Under voltage lockout

■ Integrated fast free wheeling diodes

0.73 Ω typ. value @ TJ = 25 °C

DS(on)

PWM current controller

OFF

L6229Q

VFQFPN32 5 mm x 5 mm

Description

The L6229Q is a DMOS fully integrated three­phase motor driver with overcurrent protection.

Realized in BCDmultipower technology, the
device combines isolated DMOS power
transistors with CMOS and bipolar circuits on the
same chip.

The device includes all the circuitry needed to
drive a three-phase BLDC motor including: a
three-phase DMOS bridge, a constant off time
PWM current controller and the decoding logic for
single ended hall sensors that generates the
required sequence for the power stage.

Available in VFQFPN-32 5 x 5 package, the
L6229Q features a non-dissipative overcurrent
protection on the high side power MOSFETs and
thermal shutdown.

Table 1. Device summary

Order codes Package Packaging

L6229Q

VFQFPN32 5x5x1.0 mm

L6229QTR Tape and reel

August 2010 Doc ID 15209 Rev 3 1/28

Tube

www.st.com

28

Contents L6229Q

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.6 Tacho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 20

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1 Output current capability and ic power dissipation . . . . . . . . . . . . . . . . . . 23

6.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/28 Doc ID 15209 Rev 3

L6229Q Block diagram

1 Block diagram

Figure 1. Block diagram

VBOOT V

VCP

DIAG

EN

BRAKE

FWD/REV

H

3

H

2

H

1

BOOT

CHARGE

PUMP

PROTECTION

OCD

HALL-EFFECT

SENSORS

DECODING

LOGIC

THERMAL

OCD1

OCD2

OCD

OCD3

GATE

LOGIC

OCD1

OCD2

V

BOOT

10V

V

BOOT

10V

V

BOOT

VS

A

OUT

OUT

SENSE

VS

B

1

2

A

RCPULSE

TACHO

TACHO

MONOSTABLE

10V

VOLTAGE

REGULATOR

OCD3

10V

5V

ONE SHOT

MONOSTABLE

PWM

MASKING

TIME

SENSE

COMPARATOR

+

-

D99IN1095B

OUT

SENSE

VREF

RCOFF

3

B

Doc ID 15209 Rev 3 3/28

Electrical data L6229Q

2 Electrical data

2.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Parameter Value Unit

V

V

OD

V

BOOT

, V

V

IN

V

REF

V

RCOFF

V

RCPULSE

V

SENSE

I

S(peak)

I

S

T

, T

stg

S

Supply voltage VSA = VSB = V

Differential voltage between:
VSA, OUT1, OUT2, SENSEA and
VSB, OUT3, SENSE

B

VSA = VSB = VS = 60 V;
V

SENSEA

GND

Bootstrap peak voltage VSA = VSB = V

Logic inputs voltage range -0.3 to +7 V

EN

= V

S

SENSEB

S

Voltage range at pin VREF -0.3 to +7 V

Voltage range at pin RCOFF -0.3 to +7 V

Voltage range at pin RCPULSE -0.3 to +7 V

Voltage range at pins SENSEA and
SENSE

Pulsed supply current (for each VS
pin)

RMS supply current (for each VS pin) VSA = VSB = V

Storage and operating temperature

OP

range

B

= VSB = VS;

V

SA

< 1 ms

T

PULSE

S

2.2 Recommended operating conditions

=

60 V

60 V

VS + 10 V

-1 to +4 V

3.55 A

1.4 A

-40 to 150 °C

Table 3. Recommended operating conditions

Symbol Parameter Parameter Min Max Unit

V

S

V

OD

, V

V

REFA

V

SENSEA,

V

SENSEB

I

OUT

T

J

f

sw

4/28 Doc ID 15209 Rev 3

Supply voltage

Differential voltage between

, OUT1A, OUT2A, SENSEA and

VS

A

, OUT1B, OUT2B, SENSE

VS

B

Voltage range at pins V

REFB

V

REFB

Voltage range at pins SENSEA and
SENSE

B

REFA

B

and

VSA =

VSB = V

VSA =

VSB = VS;

V

SENSEA

= V

SENSEB

(pulsed tW < trr)
(DC)

S

852V

-0.1 5 V

-6

-1

RMS output current 1.4 A

Operating junction temperature -25 +125 °C

Switching frequency 100 kHz

52 V

6
1

V
V

L6229Q Electrical data

2.3 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

th(JA)

1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).

Thermal resistance junction-ambient max.

(1)

42 °C/W

Doc ID 15209 Rev 3 5/28

Pin connection L6229Q

T

3 Pin connection

Figure 2. Pin connection (top view)

NC

OUT1

RCOFF

32 31 30 29 28 27 26 25

124

GND VCP

NC

2

NC

3

NC

4

NC

5

NC

6

SENSEA

DIAG

H1

H3

H2

23

OUT2

22

VSA

21

GND

20

VSB

19

OUT3

NC

7

NC

8

9 10111213141516

NC

TACHO

RCPULSE

Note: 1 The pins 2 to 8 are connected to die PAD.

2 The die PAD must be connected to GND pin.

SENSEB

18

NC

17

VBOO

EN

VREF

FW/REW

BRAKE

6/28 Doc ID 15209 Rev 3

L6229Q Pin connection

Table 5. Pin description

N° Pin Type Function

1, 21 GND GND Ground terminals.

9TACHO

Open drain

output

Frequency-to-voltage open drain output. Every pulse from pin H1 is shaped
as a fixed and adjustable length pulse.

RC network pin. A parallel RC network connected between this pin and

11 RCPULSE RC pin

ground sets the duration of the monostable pulse used for the frequency-to­voltage converter.

Half bridge 3 source Pin. This pin must be connected together with pin

12 SENSE

Power supply

B

SENSEA to power ground through a sensing power resistor. At this pin also
the Inverting Input of the sense comparator is connected.

Selects the direction of the rotation. HIGH logic level sets forward operation,

13 FWD/REV Logic input

whereas LOW logic level sets reverse operation.
If not used, it has to be connected to GND or +5 V.

14 EN Logic input

15 VREF Logic input

Chip enable. LOW logic level switches OFF all power MOSFETs.
If not used, it has to be connected to +5 V.

Current controller reference voltage.
Do not leave this pin open or connect to GND.

Brake input pin. LOW logic level switches ON all high side power MOSFETs,

16 BRAKE Logic input

implementing the brake function.
If not used, it has to be connected to +5 V.

17 VBOOT

19 OUT

20 VS

22 VS

23 OUT

3

B

A

2

Supply
voltage

Bootstrap voltage needed for driving the upper power MOSFETs.

Power output Output half bridge 3.

Power supply

Power supply

Half bridge 3 power supply voltage. It must be connected to the supply
voltage together with pin VS

Half bridge 1 and half bridge 2 power supply voltage. It must be connected to
the supply voltage together with pin VS

Power output Output half bridge 2.

A

24 VCP Output Charge pump oscillator output.

25 H

26 H

27 H

28 DIAG

29 SENSE

30 RCOFF RC pin

Sensor input Single ended hall effect sensor input 2.

2

Sensor input Single ended hall effect sensor input 3.

3

Sensor input Single ended hall effect sensor input 1.

1

Open drain

Power supply

A

output

Overcurrent detection and thermal protection pin. An internal open drain
transistor pulls to GND when an overcurrent on one of the high side
MOSFETs is detected or during thermal protection.

Half bridge 1 and half bridge 2 source pin. This pin must be connected
together with pin SENSE

RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-Time.

to power ground through a sensing power resistor.

B

.

.

B

31 OUT

Power output Output half bridge 1.

1

Doc ID 15209 Rev 3 7/28

Electrical characteristics L6229Q

4 Electrical characteristics

Table 6. Electrical characteristics

(V

= 48 V, TA = 25 °C, unless otherwise specified)

S

Symbol Parameter Test condition Min Typ Max Unit

V

Sth(ON)

V

Sth(OFF)

I

T

j(OFF)

S

Turn-on threshold 5.8 6.3 6.8 V

Turn-off threshold 5 5.5 6 V

Quiescent supply current

All bridges OFF;

= -25 °C to 125 °C

T

J

(1)

510mA

Thermal shutdown temperature 165 °C

Output DMOS transistors

= 25 °C 1.47 1.69 Ω

T

R

DS(on)

I

DSS

High-side + low-side switch ON
resistance

Leakage current

J

T

=125 °C

J

EN = Low; OUT = V

(1)

2.35 2.70 Ω

S

2mA

EN = Low; OUT = GND -0.3 mA

Source drain diodes

V

SD

t

rr

t

fr

Forward ON voltage ISD = 1.4 A, EN = LOW 1.15 1.3 V

Reverse recovery time If = 1.4 A 300 ns

Forward recovery time 200 ns

Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)

V

V

I

V

th(ON)

V

th(OFF)

V

th(HYS)

IH

I

IL

IH

Low level logic input voltage -0.3 0.8 V

IL

High level logic input voltage 2 7 V

Low level logic input current GND logic input voltage -10 µA

High level logic input current 7 V logic input voltage 10 µA

Turn-on input threshold 1.8 2.0 V

Turn-off input threshold 0.8 1.3 V

Input threshold hysteresis 0.25 0.5 V

Switching characteristics

t

D(ON)EN

t

D(OFF)EN

t

D(on)IN

t

D(off)IN

t

RISE

t

FAL L

t

DT

Enable to output turn-on delay

(2)

time

Enable to output turn-off delay time

Other logic inputs to OUT turn-ON delay
time

Other logic inputs to OUT turn-OFF
delay time

Output rise time

Output fall time

Dead time 0.5 1 µs

(2)

(2)

(2)

I

= 1.4 A, resistive load

LOAD

500 650 800 ns

500 1000 ns

1.6 µs

800 ns

40 250 ns

40 250 ns

8/28 Doc ID 15209 Rev 3

L6229Q Electrical characteristics

Table 6. Electrical characteristics (continued)

(V

= 48 V, TA = 25 °C, unless otherwise specified)

S

Symbol Parameter Test condition Min Typ Max Unit

f

CP

Charge pump frequency

PWM comparator and monostable

TJ = -25 °C to 125 °C

(1)

0.6 1 MHz

I

RCOFF

V

OFFSET

t

prop

t

blank

t

ON(min)

t

OFF

I

BIAS

Source current at pin RCOFF V

Offset voltage on sense comparator

Turn OFF propagation delay

(4)

(3)

V

V

= 2.5 V 3.5 5.5 mA

RCOFF

= 0.5 V ±5 mV

ref

= 0.5 V 500 ns

ref

Internal blanking time on sense
comparator

Minimum on time 2.5 3 µs

PWM recirculation time

R

OFF

OFF

= 20 kΩ; C

= 100 kΩ; C

= 1 nF 13 μs

OFF

= 1 nF 61 μs

OFF

R

Input bias current at pin VREF 10 µA

Tacho monostable

I

RCPULSE

t

PULSE

R

TAC H O

Source current at pin RCPULSE V

Monostable of time

RCPULSE

R

PUL

R

PUL

= 2.5 V 3.5 5.5 mA

= 20 kΩ; C

= 100 kΩ; C

= 1 nF 12 μs

PUL

= 1 nF 60 μs

PUL

Open drain ON resistance 40 60 W

Over current detection and protection

I

SOVER

R

OPDR

I

OH

t

OCD(ON)

t

OCD(OFF)

1. Tested at 25 °C in a restricted range and guaranteed by characterization

2. See Figure 3.

3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.

4. See Figure 4.

Supply overcurrent protection threshold TJ = -25 to 125 °C

Open drain ON resistance I

OCD high level leakage current V

OCD turn-ON delay time

OCD turn-OFF delay time

(4)

(4)

= 4 mA 40 60 W

DIAG

= 5 V 1 µA

DIAG

I

= 4 mA; C

DIAG

I

= 4 mA; C

DIAG

(2)

< 100 pF 200 ns

DIAG

< 100 pF 100 ns

DIAG

1µs

2 2.8 3.55 A

Doc ID 15209 Rev 3 9/28

Electrical characteristics L6229Q

Figure 3. Switching characteristic definition

EN

V

th(ON)

V

th(OFF)

t

I

OUT

90%

10%

D01IN1316

t

D(OFF)EN

t

FALL

t

D(ON)EN

t

RISE

t

Figure 4. Overcurrent detection timing definition

I

OUT

I

SOVER

ON

BRIDGE

OFF

V

DIAG

90%

10%

t

OCD(ON)

t

OCD(OFF)

D02IN1387

10/28 Doc ID 15209 Rev 3

L6229Q Circuit description

8

5 Circuit description

5.1 Power stages and charge pump

The L6229Q integrates a three-phase bridge, which consists of 6 power MOSFETs
connected as shown on the block diagram (see Figure 1). each power MOS has an
R
patterns are generated by the PWM current controller and the hall effect sensor decoding
logic (see relative paragraph 3.3 and 3.5). Cross conduction protection is implemented by
using a dead time (t
and turn on of two power MOSFETs in one leg of a bridge.

= 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Switching

DS(ON)

= 1 µs typical value) set by internal timing circuit between the turn off

DT

Pins VS

and VSB must be connected together to the supply voltage (VS).

A

Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (V

) is obtained

BOOT

through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically)
with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are
shown in Ta bl e 7 .

Table 7. Charge pump external component values

Component Value

C

BOOT

C

P

D1 1N4148

D2 1N4148

220 nF

10 nF

Figure 5. Charge pump circuit

V

S

D1

D2

C

BOOT

C

P

VCP VBOOT VS

Doc ID 15209 Rev 3 11/28

VS

A

B

D01IN132

Circuit description L6229Q

8

9

5.2 Logic inputs

Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and microcontroller compatible
logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off
thresholds are respectively V

Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor R

Figure 10. If the driver is a standard Push-Pull structure the resistor R

C

are connected as shown in Figure 11. The resistor REN should be chosen in the range

EN

from 2.2 kΩ to 180 kΩ. Recommended values for R

5.6 nF. More information on selecting the values is found in the overcurrent protection

section.

Figure 6. Logic inputs internal structure

= 1.8 V and V

th(ON)

= 1.3 V.

th(OFF)

and a capacitor CEN are connected as shown in

EN

and CEN are respectively 10 kΩ and

EN

5V

and the capacitor

EN

ESD

PROTECTION

Figure 7. Pin EN open collector driving

5V

R

EN

OPEN

COLLECTOR

OUTPUT

C

EN

Figure 8. Pin EN push-pull driving

R

PUSH-PULL

OUTPUT

EN

C

EN

D01IN1329

DIAG

5V

EN

ESD

PROTECTION

D02IN137

DIAG

5V

EN

ESD

PROTECTION

D02IN137

12/28 Doc ID 15209 Rev 3

L6229Q Circuit description

5.3 PWM current control

The L6229Q includes a constant off time PWM current controller. The current control circuit
senses the bridge current by sensing the voltage drop across an external sense resistor
connected between the source of the three lower power MOS transistors and ground, as
shown in Figure 9. As the current in the motor increases the voltage across the sense
resistor increases proportionally. When the voltage drop across the sense resistor becomes
greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates around the upper half of the bridge in slow
decay mode as described in the next section. When the monostable times out, the bridge
will again turn on. Since the internal dead time, used to prevent cross conduction in the
bridge, delays the turn on of the power MOS, the effective off time t
monostable time plus the dead time.

Figure 10 shows the typical operating waveforms of the output current, the voltage drop

across the sensing resistor, the pin RC voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
the next section.

Immediately after the power MOS turn on, a high peak current flows through the sense
resistor due to the reverse recovery of the freewheeling diodes. The L6229Q provides a 1 µs
blanking time t

that inhibits the comparator output so that the current spike cannot

BLANK

prematurely re trigger the monostable.

is the sum of the

OFF

Figure 9. PWM current controller simplified schematic

VS

B

S

R

BLANKING TIME

MONOSTABLE

1μs

MONOSTABLE

SET

COMPARATOR

BLANKER

SENSE

FROM THE

LOW-SIDE

GATE DRIVERS

DRIVERS

+

DEAD TIME

+

-

VREF

R

SENSE

SENSE

DRIVERS

DEAD TIME

B

TO GATE

LOGIC

5mA

RCOFF

R

OFF

Q

-

+

2.5V

(0) (1)

5V

C

OFF

VS

A

+

SENSE

DRIVERS

+

DEAD TIME

A

D02IN1380

VS

OUT

OUT

OUT

2

3

1

Doc ID 15209 Rev 3 13/28

Circuit description L6229Q

Figure 10. Output current regulation waveforms

I

OUT

V

REF

R

SENSE

t

OFF

V

SENSE

V

REF

0

V

RC

5V

2.5V

ON

SYNCHRONOUS RECTIFICATION

OFF

D02IN1351

1μs t

BLANK

Slow Decay Slow Decay

t

RCRISE

t

RCFALL

1μs t

BC

Figure 11 shows the magnitude of the Off Time t

DT

OFF

t

ON

DDA

versus C

OFF

t

OFF

1μs t

BLANK

t

RCRISE

t

RCFALL

1μs t

DT

BC

and R

values. It can be

OFF

approximately calculated from the equations:

t

RCFALL

t

OFF

where R

= t

OFF

= 0.6 · R

RCFALL

and C

OFF

· C

OFF

+ tDT = 0.6 · R

OFF

OFF

· C

OFF

+ t

DT

are the external component values and tDT is the internally generated

Dead Time with:

20 kΩ ≤ R

0.47 nF ≤ C

t

= 1 µs (typical value)

DT

≤ 100 kΩ

OFF

OFF

≤ 100 nF

Therefore:

t

OFF(MIN)

t

OFF(MAX)

These values allow a sufficient range of t

The capacitor value chosen for C
pin RCOFF. The rise time t

= 6.6 µs

= 6 ms

to implement the drive circuit for most motors.

OFF

also affects the Rise Time t

OFF

will only be an issue if the capacitor is not completely

RCRISE

of the voltage at the

RCRISE

charged before the next time the monostable is triggered. Therefore, the on time t
depends by motors and supply parameters, has to be bigger than t
good current regulation by the PWM stage. Furthermore, the on time t
than the minimum on time t

ON(MIN)

.

for allowing a

RCRISE

can not be smaller

ON

, which

ON

14/28 Doc ID 15209 Rev 3

L6229Q Circuit description

t

> 2.5μs=

⎧⎫

ONtON MIN()

⎨⎬

t

⎩⎭

ONtRCRISEtDT

–>

(typ. value)

t

RCRISE

= 600 · C

OFF

Figure 12 shows the lower limit for the on time tON for having a good PWM current regulation

capacity. It has to be said that t
this condition, but it can be smaller than t
to work but the off time t

So, small C

value gives more flexibility for the applications (allows smaller on time and,

OFF

OFF

therefore, higher switching frequency), but, the smaller is the value for C

is always bigger than t

ON

RCRISE

is not more constant.

ON(MIN)

because the device imposes

- tDT. In this last case the device continues

, the more

OFF

influential will be the noises on the circuit performance.

Figure 11. t

versus C

OFF

toff [μs]

1.10

1.10

100

and R

OFF

4

3

10

R

OFF

off

= 20k

= 100kΩ

R

off

= 47k

R

Ω

Ω

off

1

0.1 1 10 100
Coff [nF]

Figure 12. Area where tON can vary maintaining the PWM regulation

100

10

ton(min) [us]

1

0.1 1 10 100

2.5μs (typ. value)

Coff [nF]

Doc ID 15209 Rev 3 15/28

Circuit description L6229Q

5.4 Slow decay mode

Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At

any time only two legs of the three-phase bridge are active, therefore only the two active
legs of the bridge are shown in the figure and the third leg will be off. At the start of the Off
Time, the lower power MOS is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After
the dead time the upper power MOS is operated in the synchronous rectification mode
reducing the impedance of the freewheeling diode and the related conducting losses. When
the monostable times out, upper MOS that was operating the synchronous mode turns off
and the lower power MOS is turned on again after some delay set by the dead time to
prevent cross conduction.

Figure 13. Slow decay mode output stage configurations

A) ON TIME B) 1μs DEAD TIME C) SYNCHRONOUS

D01IN1336

5.5 Decoding logic

The decoding logic section is a combinatory logic that provides the appropriate driving of the
three-phase bridge outputs according to the signals coming from the three hall sensors that
detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates
between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical
degrees. This decoding method allows the implementation of a universal IC without
dedicating pins to select the sensor configuration.

There are eight possible input combinations for three sensor inputs. Six combinations are
valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions
1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical
degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in
common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical
degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical
degrees sensor phasing (3b and 6b).

The decoder can drive motors with different sensor configuration simply by following the

Ta bl e 8 . For any input configuration (H

OUT

and OUT3). The output configuration 3a is the same than 3b and analogously output

2

configuration 6a is the same than 6b.

RECTIFICATION

, H2 and H3) there is one output configuration (OUT1,

1

D) 1μs DEAD TIME

The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and
the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60

16/28 Doc ID 15209 Rev 3

L6229Q Circuit description

and the 120 codes it is possible to drive the motor with all the four conventions by changing
the direction set.

Table 8. 60 and 120 electrical degree decoding logic in forward direction

Hall 120° 1 2 3a - 4 5 6a -

Hall 60° 12 - 3b4 5-6b

H

H

H

OUT

OUT

OUT

1

2

3

1

2

3

HH L H L LHL

LH H HH LLL

LL L HHHHL

Vs High Z GND GND GND High Z Vs Vs

High Z Vs Vs Vs High Z GND GND GND

GND GND High Z High Z Vs Vs High Z High Z

Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2

Figure 14. 120° hall sensor sequence

H1

H3 H2

H1

H2 H2 H2 H2 H2 H3 H3 H3 H3 H3

H1 H1 H1 H1

1 2 3a 4 5 6a

= H

= L

Figure 15. 60° hall sensor sequence

H1 H1

H2

H3

H2 H2 H2 H2 H2

H3 H3 H3 H3 H3

1 2 3b 4 5 6b

= H

= L

Doc ID 15209 Rev 3 17/28

H1 H1 H1 H1

Circuit description L6229Q

5.6 Tacho

A tachometer function consists of a monostable, with constant off time (t
is one hall effect signal (H

). It allows developing an easy speed control loop by using an

1

), whose input

PULSE

external op amp, as shown in Figure 17. For component values refer to Application
Information section.

The monostable output drives an open drain output pin (TACHO). At each rising edge of the
hall effect sensors H
TACHO is turned off for a constant time t
set using the external RC network (R
gives the relation between t

t

= 0.6 · R

PULSE

where C

should be chosen in the range 1 nF … 100 nF and R

PUL

, the monostable is triggered and the MOSFET connected to pin

PUL

1

· C

PUL

PULSE

PUL

and C

(see Figure 16). The off time t

PULSE

, C

) connected to the pin RCPULSE. Figure 18

PUL

, R

PUL

. We have approximately:

PUL

PUL

in the range

PULSE

can be

20 kΩ … 100 kΩ.

By connecting the tachometer pin to an external pull-up resistor, the output signal average
value V

is proportional to the frequency of the hall effect signal and, therefore, to the motor

M

speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an
integrator, filters the signal and compares it with a reference voltage V

, which sets the

REF

speed of the motor.

t

PULSE

------------------

V

M

V

⋅=

T

DD

Figure 16. Tacho operation waveforms

H1

H

2

H

3

V

TACHO

VM

t

PULSE

VDD

T

18/28 Doc ID 15209 Rev 3

L6229Q Circuit description

Figure 17. Tachometer speed control loop

H

1

Figure 18. t

V

REF

PULSE

versus C

1.10

RCPULSE

V

DD

R

C

PUL

R

1

4

and R

DD

R

1

R

2

PUL

R

3

C

R

C

REF2

PUL

4

PUL

TACHO

VREF

C

REF1

R

PUL

= 100k

MONOSTABLE

Ω

TACHO

= 47k

PUL

Cpul [nF]

Ω

= 20k

R

Ω

3

1.10

s]

μ

tpulse [

100

10

1 10 100

R

PUL

Doc ID 15209 Rev 3 19/28

Circuit description L6229Q

5.7 Non-dissipative overcurrent detection and protection

The L6229Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit
provides output-to-output and output-to-ground short circuit protection as well. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 19 shows a simplified schematic for the
overcurrent detection circuit.

To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I
output current reaches the detection threshold (typically I

= 2.8 A) the OCD

SOVER

comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.

The pin DIAG can be used to signal the fault condition to a μC or to shut down the three­phase bridge simply by connecting it to pin EN and adding an external R-C (see R

Figure 19. Overcurrent protection simplified schematic

. When the

REF

, CEN).

EN

OUT

HIGH SIDE DMOS

I

1

POWER DMOS

n cells

I1 / n

OVER TEMPERATURE

μC or LOGIC

V

DD

POWER SENSE

LOGIC

R

DS(ON)

1 cell

COMPARATOR

INTERNAL

OPEN-DRAIN

OCD

TO GATE

R

EN

EN

C

EN

DIAG

40Ω TYP.

Figure 20 shows the overcurrent detection operation. The disable time t

1

I1+I2 / n

I

REF

I

REF

OUT

VS

2

A

HIGH SIDE DMOS HIGH SIDE DMOS

I

2

POWER SENSE

D02IN1381

+

POWER DMOS

n cells

I2/ n

OUT3VS

1 cell

I3/ n

B

I

3

POWER DMOS

n cells

DISABLE

before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by C
magnitude is reported in Figure 21. The delay time t

DELAY

an overcurrent has been detected depends only by C

and REN values and its

EN

before turning off the bridge when

value. Its magnitude is reported in

EN

Figure 22

POWER SENSE

1 cell

C

is also used for providing immunity to pin EN against fast transient noises. Therefore

EN

the value of C
delay time and the R

The resistor R
values for R

should be chosen as big as possible according to the maximum tolerable

EN

EN

and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs

EN

value should be chosen according to the desired disable time.

EN

should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended

disable time.

20/28 Doc ID 15209 Rev 3

L6229Q Circuit description

Figure 20. Overcurrent protection waveforms

I

OUT

I

SOVER

VEN=V

DIAG

V

DD

V

th(ON)

V

th(OFF)

ON

OCD

OFF

ON

BRIDGE

OFF

t

OCD(ON)

t

DELAY

t

EN(FALL)

t

D(OFF)EN

t

OCD(OFF)

V

EN(LOW)

t

DISABLE

t

EN(RISE)

t

D(ON)EN

D02IN1383

Figure 21. t

Figure 22. t

DISABLE

versus CEN.

DELAY

versus CEN and R

3

3

1.10

1.10

100

100

[µs]

[µs]

DISABLE

DISABLE

t

t

10

10

1

1

1 10 100

1 10 100

10

s]

μ

1

tdelay [

EN

REN= 220 k

REN= 220 k

CEN[nF ]

CEN[nF ]

Ω

Ω

REN= 100 k

REN= 100 k

Ω

Ω

R

R

R

R

R

R

EN

EN

EN

EN

EN

EN

= 47 k

= 47 k

= 33 k

= 33 k

= 10 k

= 10 k

Ω

Ω
Ω

Ω

Ω

Ω

0.1
110100

Cen [nF]

Doc ID 15209 Rev 3 21/28

Application information L6229Q

6 Application information

A typical application using L6229Q is shown in Figure 23. Typical component values for the
application are shown in Tab le 9 . A high quality ceramic capacitor (C
100 nF to 200 nF should be placed between the power pins VS
the L6229Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitor (C
EN input to ground sets the shut down time when an over current is detected (see
overcurrent protection). The two current sensing inputs (SENSE
connected to the sensing resistor R

with a trace length as short as possible in the

SENSE

layout. The sense resistor should be non-inductive resistor to minimize the dI/dt transients
across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V
(high logic level) or GND (low logic level) (see pin description). It is recommended to keep
power ground and signal ground separated on PCB.

Table 9. Component values for typical application

Component Value

) in the range of

2

and VSB and ground near

A

) connected from the

EN

and SENSEB) should be

A

R

H1

C

1

C

2

C

3

C

BOOT

C

OFF

C

PUL

C

REF1

C

REF2

C

EN

C

P

D

1

D

2

R

1

R

2

R

3

R

4

R

DD

R

EN

R

SENSE

R

OFF

R

PUL

, RH2, R

H3

100 µF

100 nF

220 nF

220 nF

1 nF

10 nF

33 nF

100 nF

5.6 nF

10 nF

1N4148

1N4148

5 k6Ω

1 k8Ω

4 k7Ω

1 MΩ

1 kΩ

100 kΩ

0.6 Ω

33 kΩ

47 kΩ

10 kΩ

22/28 Doc ID 15209 Rev 3

L6229Q Application information

Figure 23. Typical application

to SENSEB

to EN

H1 H2H3

COFF

ROFF

32 31 30 29 28 27 26 25

NC

OUT1

1

GND

2

NC

3

THREE-PHASE MOTOR

HALL

SENSOR

+5V

RH1

RH2

RH3

H1 H2 H3

M

NC

4

NC

5

NC

6

NC

7

NC

8

NC

RCOFF

TACHONCRCPULSE

9 10111213141516

CPUL

RPUL

DIAG

SENSEA

FW/REWENVREF

SENSEB

RSENSE

H1H3H2

FWD/REW

OUT2

GND

OUT3

VBOOT

BRAKE

VCP

VSA

VSB

NC

BRAKE

Cp

24

23

22

21

20

19

18

17

D1 D2

Cboot

CREF1

CEN

+

Vs

SIGNAL

GROUND

C3

R4

R3 RDD

8 ÷ 52 VDC

_

VREF

CREF1

+5V

C1 C2

POWER

GROUND

R1

R2

REN

ENABLE

6.1 Output current capability and ic power dissipation

In Figure 24 is shown the approximate relation between the output current and the IC power
dissipation using PWM current control.

For a given output current the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper
dissipating area to guarantee a safe operating junction temperature (125 °C maximum).

Figure 24. IC power dissipation versus output power

I1

I

10

8

P

[W]

D

6

I

I

4

2

Test Conditions:
Supply Voltage = 24 V

I

OUT

[A]

0

0 0.25 0.5 0.75 1 1.25 1.5

OUT

2

3

I

OUT

No PWM

fSW = 30 kHz (slow decay)

I

OUT

Doc ID 15209 Rev 3 23/28

Application information L6229Q

6.2 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition.
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.

Therefore, it has to

For instance, using a VFQFPN32L 5 x 5 package the typical R

is about 42 °C/W when

th(JA)

mounted on a double-layer FR4 PCB with a dissipating copper area of 0.5 cm
side plus 6 cm

2

ground layer connected through 18 via holes (9 below the IC).

2

on the top

24/28 Doc ID 15209 Rev 3

L6229Q Package mechanical data

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Table 10. VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50

Databook (mm)

Dim.

Min Typ Max

A 0.80 0.85 0.95

b 0.18 0.25 0.30

b1 0.165 0.175 0.185

D 4.85 5.00 5.15

D2 3.00 3.10 3.20

D3 1.10 1.20 1.30

E 4.85 5.00 5.15

E2 4.20 4.30 4.40

E3 0.60 0.70 0.80

e0.50

L 0.30 0.40 0.50

ddd 0.08

Note: VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no

lead. Very thin profile: 0.80 < A < 1.00 mm.

Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.

Doc ID 15209 Rev 3 25/28

Package mechanical data L6229Q

Figure 25. Package dimensions

26/28 Doc ID 15209 Rev 3

L6229Q Revision history

8 Revision history

Table 11. Document revision history

Date Revision Changes

25-Nov-2008 1 First release

26-Feb-2009 2 Updated Table 4 on page 5

30-Aug-2010 3 Updated Table 1 on page 1

Doc ID 15209 Rev 3 27/28

L6229Q

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28/28 Doc ID 15209 Rev 3