ST L6228Q User Manual
DMOS driver for bipolar stepper motor
Features
■ Operating supply voltage from 8 to 52 V
■ 2.8 A output peak current (1.4 A RMS)
■ R
■ Operating frequency up to 100 kHz
■ Non dissipative overcurrent protection
■ Dual independent constant t
current controllers
■ Fast/slow decay mode selection
■ Fast decay quasi-synchronous rectification
■ Decoding logic for stepper motor full and half
step drive
■ Cross conduction protection
■ Thermal shutdown
■ Undervoltage lockout
■ Integrated fast free wheeling diodes
Applications
■ Bipolar stepper motor
Figure 1. Block diagram
0.73 Ω typ. value @ TJ = 25 °C
DS(on)
OFF
PWM
L6228Q
VFQFPN32 5 mm x 5 mm
Description
The L6228Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in BCDmultipower technology,
which combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to
drive a two-phase bipolar stepper motor including:
a dual DMOS full bridge, the constant off time
PWM current controller that performs the
chopping regulation and the phase sequence
generator, that generates the stepping sequence.
Available in VFQFPN32 5 mm x 5 mm package,
the L6228Q features a non-dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.
VCP
V
BOOT
CHARGE
PUMP
THERMAL
EN
PROTECTION
STEPPING
SEQUENCE
GENERATION
VOLTAGE
REGULATOR
5V10V
OCD
OCD
A
B
OVER
CURRENT
DETECTION
GATE
LOGIC
OVER
CURRENT
DETECTION
GATE
LOGIC
V
BOOT
10V 10V
ONE SHOT
MONOSTABLE
MASKING
PWM
TIME
V
BOOT
SENSE
COMPARATOR
BRIDGE A
BRIDGE B
+
-
D01IN1225
VS
A
OUT1
OUT2
SENSE
VREF
RC
A
VS
B
OUT1
OUT2
SENSE
VREF
RC
B
A
A
A
A
B
B
B
B
VBOOT
CONTROL
HALF/FULL
CLOCK
RESET
CW/CCW
August 2010 Doc ID 14321 Rev 4 1/32
www.st.com
32
Contents L6228Q
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18
4.8 Wave drive mode (full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18
4.9 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 25
7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32 Doc ID 14321 Rev 4
L6228Q Electrical data
1 Electrical data
1.1 Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol Parameter Parameter Value Unit
V
V
V
BOOT
V
IN,VEN
V
REFA
V
RCA, VRCB
V
SENSEA,
V
SENSEB
I
S(peak)
T
stg
OD
, V
I
, T
S
S
Supply voltage
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
, OUT1B, OUT2B, SENSE
VS
B
B
Bootstrap peak voltage
Input and enable voltage range -0.3 to +7 V
Voltage range at pins V
REFB
V
REFB
REFA
and
Voltage range at pins RCA and RC
Voltage range at pins SENSEA and
SENSE
B
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
RMS supply current (for each VS pin)
Storage and operating temperature
OP
range
B
VSA =
VSB = V
VSA =
VSB = VS = 60 V;
V
SENSEA
= V
GND
VSA =
VSB = V
VSA =
VSB = VS;
< 1 ms
t
PULSE
VSA =
VSB = V
S
SENSEB
S
S
1.2 Recommended operating conditions
60 V
=
60 V
VS + 10 V
-0.3 to +7 V
-0.3 to +7 V
-1 to +4 V
3.55 A
1.4 A
-40 to 150 °C
Table 2. Recommended operating conditions
Symbol Parameter Parameter Min Max Unit
V
REFA
V
V
V
S
V
OD
, V
SENSEA,
SENSEB
I
OUT
T
j
f
sw
Supply voltage
Differential voltage between
, OUT1A, OUT2A, SENSEA and
VS
A
VSB, OUT1B, OUT2B, SENSE
Voltage range at pins V
REFB
V
REFB
Voltage range at pins SENSEA and
SENSE
B
REFA
B
and
VSA =
VSB = V
VSA =
VSB = VS;
V
SENSEA
= V
SENSEB
(pulsed tW < trr)
(DC)
S
852V
-0.1 5 V
-6
-1
RMS output current 1.4 A
Operating junction temperature -25 +125 °C
Switching frequency 100 kHz
Doc ID 14321 Rev 4 3/32
52 V
6
1
V
V
Electrical data L6228Q
1.3 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
th(JA)
1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
Thermal resistance junction-ambient max
(1)
.
42 °C/W
4/32 Doc ID 14321 Rev 4
L6228Q Pin connection
2 Pin connection
Figure 2. Pin connection (top view)
Note: 1 The pins 2 to 8 are connected to die PAD.
2 The die PAD must be connected to GND pin.
Doc ID 14321 Rev 4 5/32
Pin connection L6228Q
Table 4. Pin description
N° Pin Type Function
1, 21 GND GND Ground terminals.
9OUT1BPower output Bridge B output 1.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge B.
Bridge B source pin. This pin must be connected to power ground through a
sensing power resistor.
Bridge B current controller reference voltage.
Do not leave this pin open or connected to GND.
Step mode selector. HIGH logic level sets HALF STEP mode, LOW logic level
sets FULL STEP mode.
If not used, it has to be connected to GND or +5 V.
Decay mode selector. HIGH logic level sets SLOW DECAY mode. LOW logic
level sets FAST DECAY mode.
If not used, it has to be connected to GND or +5 V.
Chip enable. LOW logic level switches OFF all power MOSFETs of both
bridge A and bridge B. This pin is also connected to the collector of the
(1)
overcurrent and thermal protection to implement over current protection.
If not used, it has to be connected to +5 V through a resistor.
Bootstrap voltage needed for driving the upper power MOSFETs of both
bridge A and bridge B.
Bridge B power supply voltage. It must be connected to the supply voltage
together with pin VS
A
Bridge A power supply voltage. It must be connected to the supply voltage
together with pin VS
B
Reset pin. LOW logic level restores the home state (state 1) on the phase
sequence generator state machine.
If not used, it has to be connected to +5 V.
Bridge A current controller reference voltage.
Do not leave this pin open or connected to GND.
Selects the direction of the rotation. HIGH logic level sets clockwise direction,
whereas LOW logic level sets counterclockwise direction.
If not used, it has to be connected to GND or +5 V.
Bridge A source pin. This pin must be connected to power ground through a
sensing power resistor.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge A.
Power supply
B
Analog input
Logic input
RC pin
11 RC
B
12 SENSE
13 VREF
HALF/FULL
14
B
15 CONTROL Logic input
16 EN Logic input
17 VBOOT
19 OUT2
20 VS
22 VS
B
A
B
Supply
voltage
Power output Bridge B output 2.
Power supply
Power supply
23 OUT2APower output Bridge A output 2.
24 VCP Output Charge pump oscillator output.
25 RESET Logic input
26 VREF
Analog Input
A
27 CLOCK Logic input Step clock input. The state machine makes one step on each rising edge.
28 CW/CCW Logic input
29 SENSE
30 RC
31 OUT1
1. Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven
putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ
Power supply
A
A
A
RC pin
Power output Bridge A output 1.
6/32 Doc ID 14321 Rev 4
L6228Q Electrical characteristics
3 Electrical characteristics
Table 5. Electrical characteristics (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
V
Sth(ON)
V
Sth(OFF)
I
T
j(OFF)
S
Turn-on threshold 5.8 6.3 6.8 V
Turn-off threshold 5 5.5 6 V
Quiescent supply current
All bridges OFF;
TJ = -25 °C to 125 °C
Thermal shutdown temperature 165 °C
Output DMOS transistors
= 25 °C 1.47 1.69 Ω
T
R
DS(on)
High-side + low-side switch ON
resistance
J
=125 °C
T
J
(1)
EN = Low; OUT = V
I
DSS
Leakage current
EN = Low; OUT = GND -0.3 mA
Source drain diodes
V
SD
t
rr
t
fr
Forward ON voltage ISD = 1.4 A, EN = LOW 1.15 1.3 V
Reverse recovery time If = 1.4 A 300 ns
Forward recovery time 200 ns
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
V
V
I
I
V
th(ON)
V
th(OFF)
V
th(HYS)
IH
IL
IH
Low level logic input voltage -0.3 0.8 V
IL
High level logic input voltage 2 7 V
Low level logic input current GND logic input voltage -10 µA
High level logic input current 7 V logic input voltage 10 µA
Turn-on input threshold 1.8 2.0 V
Turn-off input threshold 0.8 1.3 V
Input threshold hysteresis 0.25 0.5 V
Switching characteristics
(1)
510mA
2.35 2.70 Ω
S
2mA
t
D(ON)EN
t
D(OFF)EN
t
RISE
t
FAL L
t
DCLK
t
CLK(min)L
t
CLK(min)H
Enable to output turn-on delay
(2)
time
Enable to output turn-off delay time
Output rise time
Output fall time
Clock to output delay time
Minimum clock time
Minimum clock time
(2)
(2)
(3)
(4)
(4)
Doc ID 14321 Rev 4 7/32
(2)
I
=1.4 A, resistive load
LOAD
500 650 800 ns
500 800 1000 ns
40 250 ns
40 250 ns
2µs
1µs
1µs
Electrical characteristics L6228Q
Table 5. Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
f
CLK
t
S(MIN)
t
H(MIN)
t
R(MIN)
t
RCLK(MIN)
t
DT
f
CP
Clock frequency 100 kHz
Minimum set-up time
Minimum hold time
Minimum reset time
(5)
(5)
(5)
Minimum reset to clock delay time
Dead time protection 0.5 1 µs
Charge pump frequency
PWM comparator and monostable
I
RCA, IRCB
V
offset
t
PROP
t
BLANK
t
ON(MIN)
t
OFF
I
BIAS
Source current at pins RCA and RC
Offset voltage on sense comparator V
Turn OFF propagation delay
Internal blanking time on SENSE pins 1 µs
Minimum on time 2.5 3 µs
PWM recirculation time
Input bias current at pins VREFA and
VREF
B
Over current protection
1µs
1µs
1µs
(5)
(6)
TJ = -25 °C to 125 °C
V
B
= V
RCA
REFA, VREFB
R
= 20 kΩ; C
OFF
= 100 kΩ; C
R
OFF
= 2.5 V 3.5 5.5 mA
RCB
= 0.5 V ±5 mV
(1)
0.6 1 MHz
500 ns
= 1 nF 13 µs
OFF
= 1 nF 61 µs
OFF
1µs
10 µA
I
SOVER
R
OPDR
t
OCD(ON)
t
OCD(OFF)
1. Tested at 25 °C in a restricted range and guaranteed by characterization
2. See Figure 3.
3. See Figure 4.
4. See Figure 5.
5. See Figure 6.
6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
7. See Figure 7.
Input supply overcurrent protection
threshold
Open drain ON resistance I = 4 mA 40 60 W
OCD turn-on delay time
OCD turn-off delay time
(7)
(7)
T
= -25 °C to 125 °C
j
I = 4 mA; CEN < 100 pF 200 ns
I = 4 mA; CEN < 100 pF 100 ns
(1)
2.8 A
8/32 Doc ID 14321 Rev 4
L6228Q Electrical characteristics
Figure 3. Switching characteristic definition
EN
V
th(ON)
V
th(OFF)
t
I
OUT
90%
10%
D01IN1316
t
D(OFF)EN
t
FALL
t
D(ON)EN
t
t
RISE
Figure 4. Clock to output delay time
CLOCK
V
th(ON)
I
OUT
D01IN1317
Figure 5. Minimum timing definition; clock input
CLOCK
t
DCLK
t
t
V
th(OFF)
V
th(ON)
t
CLK(MIN)L
V
th(OFF)
t
CLK(MIN)H
D01IN1318
Doc ID 14321 Rev 4 9/32
Electrical characteristics L6228Q
Figure 6. Minimum timing definition; logic inputs
CLOCK
V
th(ON)
LOGIC INPUTS
t
S(MIN)
RESET
V
th(OFF)
V
th(ON)
t
R(MIN)
t
RCLK(MIN)
Figure 7. Overcurrent detection timing definition
I
OUT
I
SOVER
t
H(MIN)
D01IN1319
ON
BRIDGE
OFF
V
EN
90%
10%
t
OCD(ON)
t
OCD(OFF)
D02IN1399
10/32 Doc ID 14321 Rev 4
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