ST L6208Q User Manual
DMOS driver for bipolar stepper motor
Features
■ Operating supply voltage from 8 to 52 V
■ 5.6 A output peak current
■ R
■ Operating frequency up to 100 kHz
■ Non-dissipative overcurrent protection
■ Dual independent constant t
controllers
■ Fast/slow decay synchronous rectification
■ Fast decay quasi-synchronous rectification
■ Decoding logic for stepper motor full and half
step drive
■ Cross conduction protection
■ Thermal shutdown
■ Undervoltage lockout
■ Integrated fast freewheeling diodes
Application
■ Bipolar stepper motor
Figure 1. Block diagram
0.3 Ω typ. value @ TJ = 25 °C
DS(on)
PWM current
OFF
L6208Q
QFN-48
(7 x 7 mm)
Description
The L6208Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in BCDmultipower technology,
which combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to
drive a two-phase bipolar stepper motor including:
a dual DMOS full bridge, the constant OFF time
PWM current controller that performs the
chopping regulation, and the phase sequence
generator that generates the stepping sequence.
Available in QFN48 7x7 package, the L6208Q
features a non-dissipative overcurrent protection
on the high-side Power MOSFETs and thermal
shutdown.
VBOOT
CONTROL
HALF/FULL
CLOCK
RESET
CW/CCW
VCP
V
BOOT
CHARGE
PUMP
THERMAL
EN
PROTECTION
STEPPING
SEQUENCE
GENERATION
VOLTAGE
REGULATOR
5V10V
OCD
OCD
A
B
OVER
CURRENT
DETECTION
GATE
LOGIC
OVER
CURRENT
DETECTION
GATE
LOGIC
V
ONE SHOT
MONOSTABLE
BOOT
PWM
MASKING
TIME
V
BOOT
SENSE
COMPARATOR
BRIDGE A
BRIDGE B
V01V01
+
-
VS
A
OUT1
OUT2
SENSE
VREF
RC
A
VS
B
OUT1
OUT2
SENSE
VREF
RC
B
A
A
A
A
B
B
B
B
AM02555v1
November 2011 Doc ID 018710 Rev 2 1/33
www.st.com
33
Contents L6208Q
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Normal drive mode (full step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Wave drive mode (full step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 18
4.10 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 24
7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/33 Doc ID 018710 Rev 2
L6208Q Electrical data
1 Electrical data
1.1 Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol Parameter Parameter Value Unit
V
Supply voltage VSA = VSB = VS 60 V
S
V
V
BOOT
V
IN,VEN
V
REFA
V
REFB
V
RCA
V
RCB
V
SENSEA
V
SENSEB
I
S(peak)
I
T
stg
Differential voltage between
OD
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSE
B
Bootstrap peak voltage VSA = VSB = VS V
Input and enable voltage range -0.3 to +7 V
,
Voltage range at pins V
,
Voltage range at pins RC
,
Voltage range at pins SENSEA and
SENSE
B
REFA
A
and V
and RC
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
S
, TOP
RMS supply current (for each VS pin) VSA = VSB = VS 2.5 A
Storage and operating temperature
range
VSA = VSB = VS = 60 V;
VSENSE
A
GND
REFB
B
= VSB = VS;
V
SA
t
< 1 ms
PULSE
= VSENSEB =
60 V
+ 10 V
S
-0.3 to +7 V
-0.3 to +7 V
-1 to +4 V
7.1 A
-40 to 150 °C
1.2 Recommended operating conditions
Table 2. Recommended operating conditions
Symbol Parameter Parameter Min. Max. Unit
V
Supply voltage VSA = VSB = VS 8 52 V
S
Differential voltage between
V
OD
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
V
,
REFA
V
REFB
V
SENSEA
V
SENSEB
I
OUT
T
f
sw
Voltage range at pins V
,
Voltage range at pins SENSEA and
REFA
and V
REFB
SENSEB
RMS output current 2.5 A
Operating junction temperature -25 +125 °C
j
Switching frequency 100 kHz
Doc ID 018710 Rev 2 3/33
= VSB = VS;
VS
A
V
SENSEA
-0.1 5 V
Pulsed t
DC -1 1 V
= V
W
< t
SENSEB
rr
52 V
-6 6 V
Pin connection L6208Q
2 Pin connection
Figure 2. Pin connection (top view)
RCA
NC
SENSEA
SENSEA
CW/CCW
CLOCK
48 47 46 45 44 43 42 41 40 39 38 37
1
NC
EPAD
2
OUT1A
3
OUT1A
4
NC
5
NC
6
GND
7
NC
8
NC
9
NC
10
OUT1B
11
OUT1B
12
NC
13 14 15 16 17 18 19 20 21 22 23 24
NC
RCB
SENSEB
SENSEB
VREFB
HALF/FULL
Note: The exposed PAD must be connected to GND pin.
Table 3. Pin description
VREFA
CONTROL
RESET
VCP
OUT2A
OUT2A
NC
36
NC
35
VSA
34
VSA
33
NC
32
NC
31
GND
30
NC
29
NC
28
NC
27
VSB
26
VSB
25
NC
EN
VBOOT
OUT2B
NC
OUT2B
AM02556v1
Pin Name Type Function
43 CLOCK Logic input
Step clock input. The state machine makes one step on each rising
edge.
Selects the direction of the rotation. HIGH logic level sets clockwise
44 CW/CCW Logic input
direction, whereas low logic level sets counterclockwise direction. If
not used, it must be connected to GND or +5 V.
45, 46 SENSE
48 RC
A
Power supply
A
RC pin
Bridge A source pin. This pin must be connected to power ground
through a sensing power resistor.
RC network pin. A parallel RC network connected between this pin
and ground sets the current controller OFF time of bridge A.
2, 3 OUT1A Power output Bridge A output 1.
Ground terminals. In PowerDIP24 and SO24 packages, these pins
6, 31 GND GND
are also used for heat dissipation towards the PCB. On PowerSO36
package the slug is connected to these pins.
10, 11 OUT1
13 RCB RC pin
Power output Bridge B output 1.
B
RC network pin. A parallel RC network connected between this pin
and ground sets the current controller OFF time of bridge B.
4/33 Doc ID 018710 Rev 2
L6208Q Pin connection
Table 3. Pin description (continued)
Pin Name Type Function
15, 16 SENSE
17 VREF
Power supply
B
Analog input
B
Bridge B source pin. This pin must be connected to power ground
through a sensing power resistor.
Bridge B current controller reference voltage. Do not leave this pin
open or connected to GND.
Step mode selector. High logic level sets half step mode, low logic
18 HALF/FULL Logic input
level sets full step mode. If not used, it must be connected to GND or
+5 V.
Decay mode selector. High logic level sets slow decay mode. Low
19 CONTROL Logic input
logic level sets fast decay mode. If not used, it must be connected to
GND or +5 V.
Chip enable. Low logic level switches off all power MOSFETs of both
bridge A and bridge B. This pin is also connected to the collector of
20 EN Logic input
(1)
the overcurrent and thermal protection to implement overcurrent
protection. If not used, it must be connected to +5 V through a
resistor.
21 VBOOT Supply voltage
22, 23 OUT2
34, 35 VS
26, 27 VS
38, 39 OUT2
Power output Bridge B output 2.
B
A
B
Power supply
Power supply
Power Output Bridge A output 2.
A
Bootstrap voltage needed for driving the upper power MOSFETs of
both bridge A and bridge B.
Bridge A power supply voltage. It must be connected to the supply
voltage together with pin VSB.
Bridge B power supply voltage. It must be connected to the supply
voltage together with pin VS
40 VCP Output Charge pump oscillator output.
A
Reset pin. Low logic level restores the home state (state 1) on the
41 RESET Logic Input
phase sequence generator state machine. If not used, it must be
connected to +5 V.
42 VREF
1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it must be driven putting
in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ.
Analog Input
A
Bridge A current controller reference voltage. Do not leave this pin
open or connected to GND.
Doc ID 018710 Rev 2 5/33
Electrical characteristics L6208Q
3 Electrical characteristics
VS = 48 V, TA = 25 °C, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
V
Sth(ON)
V
Sth(OFF)
IS Quiescent supply current
T
j(OFF)
Turn-on threshold 6.6 7 7.4 V
Turn-off threshold 5.6 6 6.4 V
All bridges OFF; Tj = -25 °C to
125 °C
(1)
Thermal shutdown temperature 165 °C
Output DMOS transistors
Tj = 25 °C 0.34 0.4
R
DS(ON)
High-side switch ON resistance
Tj =125 °C
Tj = 25 °C 0.28 0.34
Low-side switch ON resistance
Tj =125 °C
(1)
(1)
EN = low; OUT = V
I
DSS
Leakage current
EN = low; OUT = GND -0.15 mA
Source drain diodes
V
Forward ON voltage ISD = 2.5 A, EN = low 1.15 1.3 V
SD
t
rr
t
fr
Reverse recovery time If = 2.5 A 300 ns
Forward recovery time 200 ns
Logic input (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
510mA
0.53 0.59
Ω
0.47 0.53
2mA
S
V
V
I
I
V
th(ON)
V
th(OFF)
V
th(HYS)
IH
IL
IH
Low level logic input voltage -0.3 0.8 V
IL
High level logic input voltage 2 7 V
Low level logic input current GND logic input voltage -10 µA
High level logic input current 7 V logic input voltage 10 µA
Turn-on input threshold 1.8 2.0 V
Turn-off input threshold 0.8 1.3 V
Input threshold hysteresis 0.25 0.5 V
Switching characteristics
t
t
Enable to out turn ON delay time
D(on)EN
D(off)EN
t
RISE
t
FAL L
t
DCLK
Enable to out turn OFF delay time
Output rise time
Output fall time
Clock to output delay time
(2)
(2)
I
(2)
I
LOAD
(2)
I
LOAD
I
LOAD
LOAD
(3)
I
LOAD
=2.5 A, resistive load 100 250 400 ns
=2.5 A, resistive load 300 550 800 ns
=2.5 A, resistive load 40 250 ns
=2.5 A, resistive load 40 250 ns
=2.5 A, resistive load 2 µs
6/33 Doc ID 018710 Rev 2
L6208Q Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
CLK(min)L
t
CLK(min) H
t
t
t
t
RCLK(MIN )
Minimum clock time
Minimum clock time
f
CLK
S(MIN)
H(MIN)
R(MIN)
Clock frequency 100 kHz
Minimum setup time
Minimum hold time
Minimum reset time
Minimum reset to clock delay time
t
Dead time protection 0.5 1 µs
DT
Charge pump frequency Tj = -25 °C to 125 °C (7) 0.6 1 MHz
f
CP
t
dt
f
CP
Dead time protection 0.5 1 µs
Charge pump frequency -25 °C<Tj <125 °C 0.6 1 MHz
PWM comparator and monostable
(4)
1µs
(4)
1µs
(5)
1µs
(5)
1µs
(5)
1µs
(5)
1µs
I
RCA
V
t
PROP
t
BLANK
t
ON(MIN)
t
I
, I
offset
OFF
BIAS
Source current at pins RCA and
RCB
RCB
Offset voltage on sense comparator V
Turn OFF propagation delay
Internal blanking time on SENSE
pins
(6)
V
RCA
REFA
= V
, V
= 2.5 V 3.5 5.5 mA
RCB
= 0.5 V ±5 mV
REFB
500 ns
1µs
Minimum ON time 1.5 2 µs
R
PWM recirculation time
Input bias current at pins VREF
VREF
B
and
A
OFF
= 100 kΩ; C
R
OFF
= 20 kΩ; C
= 1 nF 13 µs
OFF
= 1 nF 61 µs
OFF
10 µA
Overcurrent detection
I
sover
threshold
-25 °C<Tj <125 °C 4 5.6 7.1 A
Input supply overcurrent detection
ROPDR Open drain ON resistance I = 4 mA 40 60 Ω
t
OCD(ON)
t
OCD(OFF)
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3.
3. See Figure 4.
4. See Figure 5.
5. See Figure 6.
6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin V
7. See Figure 7.
OCD turn-on delay time
OCD turn-off delay time
(7)
(7)
I = 4 mA; CEN < 100 pF 200 ns
I = 4 mA; CEN < 100 pF 100 ns
.
REF
Doc ID 018710 Rev 2 7/33
Electrical characteristics L6208Q
Figure 3. Switching characteristic definition
EN
V
th(ON)
V
th(OFF)
t
I
OUT
90%
10%
D01IN1316
t
D(OFF)EN
t
FAL L
t
D(ON)EN
t
t
RISE
AM02557v1
Figure 4. Clock to output delay time
CLOCK
V
th(ON)
I
OUT
D01IN1317
Figure 5. Minimum timing definition; clock input
CLOCK
V
V
th(OFF)
th(ON)
t
CLK(MIN)L
V
th(OFF)
t
CLK(MIN)H
t
DCLK
t
t
D01IN1318
8/33 Doc ID 018710 Rev 2
L6208Q Electrical characteristics
Figure 6. Minimum timing definition; logic inputs
CLOCK
V
th(ON)
LOGIC INPUTS
t
S(MIN)
RESET
V
th(OFF)
V
th(ON)
t
R(MIN)
t
RCLK(MIN)
Figure 7. Overcurrent detection timing definition
I
OUT
I
SOVER
t
H(MIN)
D01IN1319
ON
BRIDGE
OFF
V
EN
90%
10%
t
OCD(ON)
t
OCD(OFF)
AM02558v1
Doc ID 018710 Rev 2 9/33
Circuit description L6208Q
4 Circuit description
4.1 Power stages and charge pump
The L6208Q integrates two independent power MOSFET full bridges, each power MOSFET
has an R
conduction protection is implemented by using a dead time (t
internal timing circuit between the turn-off and turn-on of two power MOSFETs in one leg of
a bridge.
= 0.3 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross
DS(ON)
= 1 µs typical value) set by
DT
Pins VS
and VSB must be connected together to the supply voltage (VS).
A
Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate
drive voltage above the power supply voltage. The bootstrapped supply (V
) is obtained
BOOT
through an internal oscillator and a few external components to realize a charge pump
circuit, as shown in Figure 8. The oscillator output (pin VCP) is a square wave at 600 kHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Tab le 5 .
Table 5. Charge pump external component values
Component Value
C
BOOT
C
P
R
P
220 nF
10 nF
100 Ω
D1 1N4148
D2 1N4148
Figure 8. Charge pump circuit
V
S
D1
R
C
VCP VBOOT VS
C
D2
P
P
BOOT
VS
A
B
AM02559v1
10/33 Doc ID 018710 Rev 2
Loading...