ST L6208Q User Manual

DMOS driver for bipolar stepper motor

Features

■ Operating supply voltage from 8 to 52 V

■ 5.6 A output peak current

■ R

■ Operating frequency up to 100 kHz

■ Non-dissipative overcurrent protection

■ Dual independent constant t

controllers

■ Fast/slow decay synchronous rectification

■ Fast decay quasi-synchronous rectification

■ Decoding logic for stepper motor full and half

step drive

■ Cross conduction protection

■ Thermal shutdown

■ Undervoltage lockout

■ Integrated fast freewheeling diodes

Application

■ Bipolar stepper motor

Figure 1. Block diagram

0.3 Ω typ. value @ TJ = 25 °C

DS(on)

PWM current

OFF

L6208Q

QFN-48

(7 x 7 mm)

Description

The L6208Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in BCDmultipower technology,
which combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to
drive a two-phase bipolar stepper motor including:
a dual DMOS full bridge, the constant OFF time
PWM current controller that performs the
chopping regulation, and the phase sequence
generator that generates the stepping sequence.
Available in QFN48 7x7 package, the L6208Q
features a non-dissipative overcurrent protection
on the high-side Power MOSFETs and thermal
shutdown.

VBOOT

CONTROL

HALF/FULL

CLOCK

RESET

CW/CCW

VCP

V

BOOT

CHARGE

PUMP

THERMAL

EN

PROTECTION

STEPPING

SEQUENCE

GENERATION

VOLTAGE

REGULATOR

5V10V

OCD

OCD

A

B

OVER

CURRENT

DETECTION

GATE

LOGIC

OVER

CURRENT

DETECTION

GATE

LOGIC

V

ONE SHOT

MONOSTABLE

BOOT

PWM

MASKING

TIME

V

BOOT

SENSE

COMPARATOR

BRIDGE A

BRIDGE B

V01V01

+

-

VS

A

OUT1

OUT2

SENSE

VREF

RC

A

VS

B

OUT1

OUT2

SENSE

VREF

RC

B

A

A

A

A

B

B

B

B

AM02555v1

November 2011 Doc ID 018710 Rev 2 1/33

www.st.com

33

Contents L6208Q

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 Decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.5 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.6 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.7 Normal drive mode (full step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 17

4.8 Wave drive mode (full step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . . 17

4.9 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 18

4.10 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 24

7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/33 Doc ID 018710 Rev 2

L6208Q Electrical data

1 Electrical data

1.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Parameter Value Unit

V

Supply voltage VSA = VSB = VS 60 V

S

V

V

BOOT

V

IN,VEN

V

REFA

V

REFB

V

RCA

V

RCB

V

SENSEA

V

SENSEB

I

S(peak)

I

T

stg

Differential voltage between

OD

VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSE

B

Bootstrap peak voltage VSA = VSB = VS V

Input and enable voltage range -0.3 to +7 V

,

Voltage range at pins V

,

Voltage range at pins RC

,

Voltage range at pins SENSEA and
SENSE

B

REFA

A

and V

and RC

Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection

S

, TOP

RMS supply current (for each VS pin) VSA = VSB = VS 2.5 A

Storage and operating temperature
range

VSA = VSB = VS = 60 V;
VSENSE

A

GND

REFB

B

= VSB = VS;

V

SA

t

< 1 ms

PULSE

= VSENSEB =

60 V

+ 10 V

S

-0.3 to +7 V

-0.3 to +7 V

-1 to +4 V

7.1 A

-40 to 150 °C

1.2 Recommended operating conditions

Table 2. Recommended operating conditions

Symbol Parameter Parameter Min. Max. Unit

V

Supply voltage VSA = VSB = VS 8 52 V

S

Differential voltage between

V

OD

VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB

V

,

REFA

V

REFB

V

SENSEA

V

SENSEB

I

OUT

T

f

sw

Voltage range at pins V

,

Voltage range at pins SENSEA and

REFA

and V

REFB

SENSEB

RMS output current 2.5 A

Operating junction temperature -25 +125 °C

j

Switching frequency 100 kHz

Doc ID 018710 Rev 2 3/33

= VSB = VS;

VS

A

V

SENSEA

-0.1 5 V

Pulsed t

DC -1 1 V

= V

W

< t

SENSEB

rr

52 V

-6 6 V

Pin connection L6208Q

2 Pin connection

Figure 2. Pin connection (top view)

RCA

NC

SENSEA

SENSEA

CW/CCW

CLOCK

48 47 46 45 44 43 42 41 40 39 38 37

1

NC

EPAD

2

OUT1A

3

OUT1A

4

NC

5

NC

6

GND

7

NC

8

NC

9

NC

10

OUT1B

11

OUT1B

12

NC

13 14 15 16 17 18 19 20 21 22 23 24

NC

RCB

SENSEB

SENSEB

VREFB

HALF/FULL

Note: The exposed PAD must be connected to GND pin.

Table 3. Pin description

VREFA

CONTROL

RESET

VCP

OUT2A

OUT2A

NC

36

NC

35

VSA

34

VSA

33

NC

32

NC

31

GND

30

NC

29

NC

28

NC

27

VSB

26

VSB

25

NC

EN

VBOOT

OUT2B

NC

OUT2B

AM02556v1

Pin Name Type Function

43 CLOCK Logic input

Step clock input. The state machine makes one step on each rising
edge.

Selects the direction of the rotation. HIGH logic level sets clockwise

44 CW/CCW Logic input

direction, whereas low logic level sets counterclockwise direction. If
not used, it must be connected to GND or +5 V.

45, 46 SENSE

48 RC

A

Power supply

A

RC pin

Bridge A source pin. This pin must be connected to power ground
through a sensing power resistor.

RC network pin. A parallel RC network connected between this pin
and ground sets the current controller OFF time of bridge A.

2, 3 OUT1A Power output Bridge A output 1.

Ground terminals. In PowerDIP24 and SO24 packages, these pins

6, 31 GND GND

are also used for heat dissipation towards the PCB. On PowerSO36
package the slug is connected to these pins.

10, 11 OUT1

13 RCB RC pin

Power output Bridge B output 1.

B

RC network pin. A parallel RC network connected between this pin
and ground sets the current controller OFF time of bridge B.

4/33 Doc ID 018710 Rev 2

L6208Q Pin connection

Table 3. Pin description (continued)

Pin Name Type Function

15, 16 SENSE

17 VREF

Power supply

B

Analog input

B

Bridge B source pin. This pin must be connected to power ground
through a sensing power resistor.

Bridge B current controller reference voltage. Do not leave this pin
open or connected to GND.

Step mode selector. High logic level sets half step mode, low logic

18 HALF/FULL Logic input

level sets full step mode. If not used, it must be connected to GND or
+5 V.

Decay mode selector. High logic level sets slow decay mode. Low

19 CONTROL Logic input

logic level sets fast decay mode. If not used, it must be connected to
GND or +5 V.

Chip enable. Low logic level switches off all power MOSFETs of both
bridge A and bridge B. This pin is also connected to the collector of

20 EN Logic input

(1)

the overcurrent and thermal protection to implement overcurrent
protection. If not used, it must be connected to +5 V through a
resistor.

21 VBOOT Supply voltage

22, 23 OUT2

34, 35 VS

26, 27 VS

38, 39 OUT2

Power output Bridge B output 2.

B

A

B

Power supply

Power supply

Power Output Bridge A output 2.

A

Bootstrap voltage needed for driving the upper power MOSFETs of
both bridge A and bridge B.

Bridge A power supply voltage. It must be connected to the supply
voltage together with pin VSB.

Bridge B power supply voltage. It must be connected to the supply
voltage together with pin VS

40 VCP Output Charge pump oscillator output.

A

Reset pin. Low logic level restores the home state (state 1) on the

41 RESET Logic Input

phase sequence generator state machine. If not used, it must be
connected to +5 V.

42 VREF

1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it must be driven putting

in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ.

Analog Input

A

Bridge A current controller reference voltage. Do not leave this pin
open or connected to GND.

Doc ID 018710 Rev 2 5/33

Electrical characteristics L6208Q

3 Electrical characteristics

VS = 48 V, TA = 25 °C, unless otherwise specified.

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

Sth(ON)

V

Sth(OFF)

IS Quiescent supply current

T

j(OFF)

Turn-on threshold 6.6 7 7.4 V

Turn-off threshold 5.6 6 6.4 V

All bridges OFF; Tj = -25 °C to
125 °C

(1)

Thermal shutdown temperature 165 °C

Output DMOS transistors

Tj = 25 °C 0.34 0.4

R

DS(ON)

High-side switch ON resistance

Tj =125 °C

Tj = 25 °C 0.28 0.34

Low-side switch ON resistance

Tj =125 °C

(1)

(1)

EN = low; OUT = V

I

DSS

Leakage current

EN = low; OUT = GND -0.15 mA

Source drain diodes

V

Forward ON voltage ISD = 2.5 A, EN = low 1.15 1.3 V

SD

t

rr

t

fr

Reverse recovery time If = 2.5 A 300 ns

Forward recovery time 200 ns

Logic input (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)

510mA

0.53 0.59

Ω

0.47 0.53

2mA

S

V

V

I

I

V

th(ON)

V

th(OFF)

V

th(HYS)

IH

IL

IH

Low level logic input voltage -0.3 0.8 V

IL

High level logic input voltage 2 7 V

Low level logic input current GND logic input voltage -10 µA

High level logic input current 7 V logic input voltage 10 µA

Turn-on input threshold 1.8 2.0 V

Turn-off input threshold 0.8 1.3 V

Input threshold hysteresis 0.25 0.5 V

Switching characteristics

t

t

Enable to out turn ON delay time

D(on)EN

D(off)EN

t

RISE

t

FAL L

t

DCLK

Enable to out turn OFF delay time

Output rise time

Output fall time

Clock to output delay time

(2)

(2)

I

(2)

I

LOAD

(2)

I

LOAD

I

LOAD

LOAD

(3)

I

LOAD

=2.5 A, resistive load 100 250 400 ns

=2.5 A, resistive load 300 550 800 ns

=2.5 A, resistive load 40 250 ns

=2.5 A, resistive load 40 250 ns

=2.5 A, resistive load 2 µs

6/33 Doc ID 018710 Rev 2

L6208Q Electrical characteristics

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

t

CLK(min)L

t

CLK(min) H

t

t

t

t

RCLK(MIN )

Minimum clock time

Minimum clock time

f

CLK

S(MIN)

H(MIN)

R(MIN)

Clock frequency 100 kHz

Minimum setup time

Minimum hold time

Minimum reset time

Minimum reset to clock delay time

t

Dead time protection 0.5 1 µs

DT

Charge pump frequency Tj = -25 °C to 125 °C (7) 0.6 1 MHz

f

CP

t

dt

f

CP

Dead time protection 0.5 1 µs

Charge pump frequency -25 °C<Tj <125 °C 0.6 1 MHz

PWM comparator and monostable

(4)

1µs

(4)

1µs

(5)

1µs

(5)

1µs

(5)

1µs

(5)

1µs

I

RCA

V

t

PROP

t

BLANK

t

ON(MIN)

t

I

, I

offset

OFF

BIAS

Source current at pins RCA and

RCB

RCB

Offset voltage on sense comparator V

Turn OFF propagation delay

Internal blanking time on SENSE
pins

(6)

V

RCA

REFA

= V

, V

= 2.5 V 3.5 5.5 mA

RCB

= 0.5 V ±5 mV

REFB

500 ns

1µs

Minimum ON time 1.5 2 µs

R

PWM recirculation time

Input bias current at pins VREF
VREF

B

and

A

OFF

= 100 kΩ; C

R

OFF

= 20 kΩ; C

= 1 nF 13 µs

OFF

= 1 nF 61 µs

OFF

10 µA

Overcurrent detection

I

sover

threshold

-25 °C<Tj <125 °C 4 5.6 7.1 A

Input supply overcurrent detection

ROPDR Open drain ON resistance I = 4 mA 40 60 Ω

t

OCD(ON)

t

OCD(OFF)

1. Tested at 25 °C in a restricted range and guaranteed by characterization.

2. See Figure 3.

3. See Figure 4.

4. See Figure 5.

5. See Figure 6.

6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin V

7. See Figure 7.

OCD turn-on delay time

OCD turn-off delay time

(7)

(7)

I = 4 mA; CEN < 100 pF 200 ns

I = 4 mA; CEN < 100 pF 100 ns

.

REF

Doc ID 018710 Rev 2 7/33

Electrical characteristics L6208Q

Figure 3. Switching characteristic definition

EN

V

th(ON)

V

th(OFF)

t

I

OUT

90%

10%

D01IN1316

t

D(OFF)EN

t

FAL L

t

D(ON)EN

t

t

RISE

AM02557v1

Figure 4. Clock to output delay time

CLOCK

V

th(ON)

I

OUT

D01IN1317

Figure 5. Minimum timing definition; clock input

CLOCK

V

V

th(OFF)

th(ON)

t

CLK(MIN)L

V

th(OFF)

t

CLK(MIN)H

t

DCLK

t

t

D01IN1318

8/33 Doc ID 018710 Rev 2

L6208Q Electrical characteristics

Figure 6. Minimum timing definition; logic inputs

CLOCK

V

th(ON)

LOGIC INPUTS

t

S(MIN)

RESET

V

th(OFF)

V

th(ON)

t

R(MIN)

t

RCLK(MIN)

Figure 7. Overcurrent detection timing definition

I

OUT

I

SOVER

t

H(MIN)

D01IN1319

ON

BRIDGE

OFF

V

EN

90%

10%

t

OCD(ON)

t

OCD(OFF)

AM02558v1

Doc ID 018710 Rev 2 9/33

Circuit description L6208Q

4 Circuit description

4.1 Power stages and charge pump

The L6208Q integrates two independent power MOSFET full bridges, each power MOSFET
has an R
conduction protection is implemented by using a dead time (t
internal timing circuit between the turn-off and turn-on of two power MOSFETs in one leg of
a bridge.

= 0.3 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross

DS(ON)

= 1 µs typical value) set by

DT

Pins VS

and VSB must be connected together to the supply voltage (VS).

A

Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate
drive voltage above the power supply voltage. The bootstrapped supply (V

) is obtained

BOOT

through an internal oscillator and a few external components to realize a charge pump
circuit, as shown in Figure 8. The oscillator output (pin VCP) is a square wave at 600 kHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Tab le 5 .

Table 5. Charge pump external component values

Component Value

C

BOOT

C

P

R

P

220 nF

10 nF

100 Ω

D1 1N4148

D2 1N4148

Figure 8. Charge pump circuit

V

S

D1

R

C

VCP VBOOT VS

C

D2

P

P

BOOT

VS

A

B

AM02559v1

10/33 Doc ID 018710 Rev 2

L6208Q Circuit description

4.2 Logic inputs

Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and µC
compatible logic inputs. The internal structure is shown in Figure 9. Typical values for turn­on and turn-off thresholds are respectively V

Pin EN (Enable) has identical input structure with the exception that the drain of the
overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection, some care must be taken in driving this pin. The EN input may be driven in one
of two configurations, as shown in Figure 10 or 11. If driven by an open drain (collector)
structure, a pull-up resistor R

and a capacitor CEN are connected, as shown in Figure 10.

EN

If the driver is a standard push-pull structure, the resistor R
connected, as shown in Figure 11. The resistor R
kΩ to 180 kΩ. Recommended values for R
More information on selecting the values is found in Section 4.9.

Figure 9. Logic inputs internal structure

=1.8 V and V

thon

should be chosen in the range from 2.2

EN

and CEN are respectively 100 kΩ and 5.6 nF.

EN

5V

=1.3 V.

thoff

and the capacitor CEN are

EN

ESD

PROTECTION

Figure 10. EN pins open collector driving

5V

R

EN

OPEN

COLLECTOR

OUTPUT

C

EN

EN

PROTECTION

Figure 11. EN pins push-pull driving

R

PUSH-PULL

OUTPUT

EN

C

EN

EN

PROTECTION

AM02560v1

5V

ESD

AM02561v1

5V

ESD

AM02562v1

Doc ID 018710 Rev 2 11/33

Circuit description L6208Q

4.3 PWM current control

The L6208Q includes a constant OFF time PWM current controller for each of the two
bridges. The current control circuit senses the bridge current by sensing the voltage drop
across an external sense resistor connected between the source of the two lower power
MOSFET transistors and ground, as shown in Figure 12. As the current in the load builds
up, the voltage across the sense resistor increases proportionally. When the voltage drop
across the sense resistor becomes greater than the voltage at the reference input (VREF
or VREF

), the sense comparator triggers the monostable switching the low-side MOSFET

B

off. The low-side MOSFET remains off for the time set by the monostable and the motor
current recirculates in the upper path. When the monostable times out, the bridge again
turns on. As the internal dead time, used to prevent cross conduction in the bridge, delays
the turn-on of the power MOSFET, the effective OFF time is the sum of the monostable time
plus the dead time.

Figure 12. PWM current controller simplified schematic

VS

(or B)

A

S

R

BLANKING TIME

MONOSTABLE

MONOSTABLE

SET

1μs

BLANKER

COMPARATOR

COMPARATOR

OUTPUT

SENSE

GATE DRIVERS

DRIVERS

+

DEAD TIME

+

-

VREF

FROM THE

LOW-SIDE

A(or B)

2H 1H

DRIVERS

+

DEAD TIME

2L 1L

SENSE

R

SENSE

A(or B)

OUT2

OUT1

I

OUT

A(or B)

A(or B)

D01IN1332

STEPPER MOTOR

TO GATE LOGIC

5mA

(0) (1)

5V

C

OFF

Q

-

+

2.5V

RC

A(or B)

R

OFF

A

2 PHASE

Figure 13 shows the typical operating waveforms of the output current, the voltage drop

across the sensing resistor, the RC pin voltage and the status of the bridge. More details
regarding the Synchronous Rectification and the output stage configuration are included in

Section 4.4.

Immediately after the low-side Power MOSFET turns on, a high peak current flows through
the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6208Q
provides a 1 μs blanking time t

that inhibits the comparator output so that this current

BLANK

spike cannot prematurely re-trigger the monostable.

12/33 Doc ID 018710 Rev 2

L6208Q Circuit description

Figure 13. Output current regulation waveforms

I

OUT

V

REF

R

SENSE

t

OFF

V

SENSE

V

REF

0

V

RC

5V

2.5V

ON

SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION

OFF

D01IN1334

1μs t

BLANK

Slow Decay Slow Decay

Fast Decay

t

RCRISE

t

RCFALL

1μs t

DT

BC

Figure 14 shows the magnitude of the OFF time t

t

ON

versus COFF and ROFF values. It can be

OFF

t

OFF

1μs t

BLANK

Fast Decay

t

RCRISE

t

RCFALL

1μs t

DT

BC

approximately calculated from the equations:

t

RCFALL

t

OFF

where R

= 0.6 · R

= t

RCFALL

and C

OFF

· C

OFF

+ tDT = 0.6 · R

OFF

OFF

OFF

· C

OFF

+ t

DT

are the external component values and t

is the internally generated

DT

dead time with:

20 kΩ ≤ R

0.47 nF ≤ C

t

= 1 µs (typical value)

DT

OFF

OFF

≤ 100 kΩ

≤ 100 nF

therefore:

t

OFF(MIN)

t

OFF(MAX)

These values allow a sufficient range of t

The capacitor value chosen for C
pin R

COFF

= 6.6 µs

= 6 ms

. The rise time t

RCRISE

to implement the drive circuit for most motors.

OFF

also affects the rise time t

OFF

is only an issue if the capacitor is not completely charged

RCRISE

of the voltage at the

before the next time the monostable is triggered. Therefore, the ON time t
depends on motors and supply parameters, must be bigger than t
current regulation by the PWM stage. Furthermore, the ON time t
the minimum ON time t

ON(MIN)

.

RCRISE

can not be smaller than

ON

DDA

, which

ON

to allow a good

Doc ID 018710 Rev 2 13/33

Circuit description L6208Q

⎧

t

>

⎪

ONtON MIN()

⎨

t

⎪

ONtRCRISEtDT

⎩

t

RCRISE

–>

600 C

⋅=

1.5μstyp()=

OFF

Figure 15 shows the lower limit for the ON time tON for having a good PWM current

regulation capacity. It should be mentioned that t
the device imposes this condition, but it can be smaller than t
the device continues to work but the OFF time t

Therefore, a small C

value gives more flexibility to the applications (allows smaller ON

OFF

time and, therefore, higher switching frequency), but, the smaller the value for C

is always bigger than t

ON

is not more constant.

OFF

RCRISE

ON(MIN)

because

- tDT. In this last case

, the

OFF

more influential the noises on the circuit performance.

Figure 14. t

OFF

vs. C

1.10

1.10

100

toff [μs]

and R

OFF

4

3

10

1

0.1 1 10 100

OFF

R

= 100k Ω

R

off

= 47kΩ

R

off

= 20k

Ω

off

Coff [nF]

14/33 Doc ID 018710 Rev 2

L6208Q Circuit description

Figure 15. Area where tON can vary maintaining the PWM regulation

100

10

ton(min) [μs]

1.5μs (typ. value)

1

Coff [nF]

0010111.0

Doc ID 018710 Rev 2 15/33

Circuit description L6208Q

4.4 Decay mode

The CONTROL input is used to select the behavior of the bridge during the OFF time. When
the CONTROL pin is low, the Fast Decay mode is selected and both transistors in the bridge
are switched off during the OFF time. When the CONTROL pin is high, the Slow Decay
mode is selected and only the low-side transistor of the bridge is switched off during the
OFF time. Figure 16 shows the operation of the bridge in fast decay mode. At the start of the
OFF time, both of the power MOSFETs are switched off and the current recirculates through
the two opposite freewheeling diodes. The current decays with a high di/dt since the voltage
across the coil is essentially the power supply voltage. After the dead time, the lower power
MOSFET in parallel with the conducting diode is turned on in synchronous rectification
mode. In applications where the motor current is low, it is possible that the current may
decay completely to zero during the OFF time. At this point, if both of the power MOSFETs
were operating in the synchronous rectification mode, it would then be possible for the
current to build in the opposite direction. To prevent this only the lower power MOSFET is
operated in synchronous rectification mode. This operation is called Quasi-Synchronous
Rectification Mode. When the monostable times out, the power MOSFETs are turned on
again after some delay set by the dead time to prevent cross conduction.

Figure 17 shows the operation of the bridge in slow decay mode. At the start of the OFF

time, the lower power MOSFET is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After
the dead time the upper power MOSFET is operated in the synchronous rectification mode.
When the monostable times out, the lower power MOSFET is turned on again after some
delay set by the dead time to prevent cross conduction.

Figure 16. Fast decay mode output stage configurations

1 )BEMIT NO )A μs DEAD TIME C) QUASI-SYNCHRONOUS

D01IN1335

RECTIFICATION

Figure 17. Slow decay mode output stage configurations

D) 1μs SLOW DECAY

1 )BEMIT NO )A μs DEAD TIME C) SYNCHRONOUS

D01IN1336

16/33 Doc ID 018710 Rev 2

RECTIFICATION

D) 1μs DEAD TIME

L6208Q Circuit description

4.5 Stepping sequence generation

The phase sequence generator is a state machine that provides the phase and enable
inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step
modes are possible, the normal drive mode where both phases are energized at each step
and the wave drive mode where only one phase is energized at a time. The drive mode is
selected by the HALF/FULL input and the current state of the sequence generator, as
described below. A rising edge of the CLOCK input advances the state machine to the next
state. The direction of rotation is set by the CW/CCW input. The RESET input resets the
state machine to state.

4.6 Half step mode

A HIGH logic level on the HALF/FULL input selects half step mode. Figure 18 shows the
motor current waveforms and the state diagram for the phase sequencer generator. At
startup or after a RESET the phase sequencer is at state 1. After each clock pulse the state
changes following the sequence 1,2,3,4,5,6,7,8,… if CW/CCW is high (clockwise
movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (counterclockwise movement).

4.7 Normal drive mode (full step two-phase-on)

A low level on the HALF/FULL input selects the full step mode. When the low level is
applied, when the state machine is at an ODD numbered state, normal drive mode is
selected. Figure 19 shows the motor current waveform state diagram for the state machine
of the phase sequencer generator. Normal drive mode can easily be selected by holding the
HALF/FULL input low and applying a RESET. At startup or after a RESET the state machine
is in state 1. While, when the HALF/FULL input is kept low, the state changes following the
sequence 1,3,5,7,… if CW/CCW is high (clockwise movement) or 1,7,5,3,… if CW/CCW is
low (counterclockwise movement).

4.8 Wave drive mode (full step one-phase-on)

A low level on the pin HALF/FULL input selects the full step mode. When the low level is
applied, when the state machine is at an EVEN numbered state, the wave drive mode is
selected. Figure 20 shows the motor current waveform and the state diagram for the state
machine of the phase sequence generator. To enter wave drive mode the state machine
must be in an EVEN numbered state. The most direct method to select the wave drive mode
is to first apply a RESET, then while keeping the HALF/FULL input high, apply one pulse to
the clock input, then take the HALF/FULL input low. This sequence first forces the state
machine to state 1. The clock pulse, with the HALF/FULL input high, advances the state
machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting from
this point, each clock pulse (rising edge) advances the state machine following the
sequence 2,4,6,8,… if CW/CCW is high (clockwise movement) or 8,6,4,2,… if CW/ CCW is
low (counterclockwise movement).

Doc ID 018710 Rev 2 17/33

Circuit description L6208Q

Figure 18. Half step mode

I

OUTA

324 5

6

1 8 7

Start Up or Reset

Figure 19. Normal drive mode

4

35

2

17

Start Up or Reset

6

8

Figure 20. Wave drive mode

4

35

2

D01IN1320

D01IN1322

6

I

OUTB

CLOCK

I

OUTA

I

OUTB

CLOCK

I

OUTA

I

OUTB

2345678

1

3571357

1

8

17

Start Up or Reset

CLOCK

D01IN1321

4682468

2

4.9 Non-dissipative overcurrent detection and protection

The L6208 integrates an overcurrent detection circuit (OCD). With this internal overcurrent
detection, the external current sense resistor normally used and its associated power
dissipation are eliminated. Figure 21 shows a simplified schematic of the overcurrent
detection circuit.

To implement overcurrent detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high-side power MOSFET. Since this
current is a small fraction of the output current, there is very little additional power
dissipation. This current is compared with an internal reference current I
output current reaches the detection threshold (typically 5.6 A), the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn-off
threshold (1.3 V typical) by an internal open drain MOSFET with a pull-down capability of 4
mA. By using an external R-C on the EN pin, the OFF time before recovering normal
operation can be easily programmed by means of the accurate thresholds of the logic
inputs.

. When the

REF

18/33 Doc ID 018710 Rev 2

L6208Q Circuit description

Figure 21. Overcurrent protection simplified schematic

OUT1

A

VS

OUT2

A

A

POWER SENSE

1 cell

I1AI

2A

POWER DMOS

n cells

OVER TEMPERATURE

OCD

I1A/ n

(I1A+I2A) / n

I

REF

FROM THE

BRIDGE B

+

I2A/ n

μC or LOGIC

V

DD

R

.EN

EN

C

.

EN

TO GATE

R

DS(ON)

40Ω TYP.

LOGIC

OCD

COMPARATOR

INTERNAL

OPEN-DRAIN

COMPARATOR

Figure 22 shows the overcurrent detection operation. The disable time t

HIGH SIDE DMOSs OF

THE BRIDGE A

POWER DMOS

n cells

DISABLE

POWER SENSE

before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected by both C
reported in Figure 23. The delay time t

before turning off the bridge when an

DELAY

overcurrent has been detected depends only on C

and REN values and its magnitude is

EN

value. Its magnitude is reported in

EN

Figure 24.

1 cell

AM02563v1

C

is also used for providing immunity to pin EN against fast transient noises. Therefore

EN

the value of C
delay time and the R

The resistor R
values for R

should be chosen as big as possible according to the maximum tolerable

EN

EN

and CEN are respectively 100 kΩ and 5.6 nF which allow to obtain 200 µs

EN

value should be chosen according to the desired disable time.

EN

should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended

disable time.

Doc ID 018710 Rev 2 19/33

Circuit description L6208Q

Figure 22. Overcurrent protection waveforms

I

OUT

I

SOVER

V

EN

V

DD

V

th(ON)

V

th(OFF)

ON

OCD

OFF

ON

BRIDGE

t

DELAY

V

EN(LOW)

t

DISABLE

OFF

t

Figure 23. t

1.10

1.10

[µs]

[µs]

DISABLE

DISABLE

t

t

OCD(ON)

DISABLE

3

3

100

100

10

10

1

1

1 10 100

1 10 100

t

EN(FALL)

t

D(OFF)EN

vs. CEN and REN (VDD = 5 V)

REN= 220 k

REN= 220 k

t

OCD(OFF)

Ω

Ω

CEN[n F]

CEN[n F]

t

EN(RISE)

REN= 100 k

REN= 100 k

t

D(ON)EN

AM02564v1

Ω

Ω

R

R

= 47 k

= 47 k

EN

EN

R

R

= 33 k

= 33 k

EN

EN

= 10 k

= 10 k

R

R

EN

EN

Ω

Ω
Ω

Ω

Ω

Ω

20/33 Doc ID 018710 Rev 2

L6208Q Circuit description

Figure 24. t

vs. CEN (VDD = 5 V)

DELAY

10

s]

μ

1

tdelay [

0.1
110100

Cen [nF]

4.10 Thermal protection

In addition to the overcurrent detection, the L6208Q integrates a thermal protection to
prevent device destruction in the case of junction over temperature. It works sensing the die
temperature by means of a sensitive element integrated in the die. The device switches off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).

Doc ID 018710 Rev 2 21/33

Application information L6208Q

5 Application information

A typical application using L6208Q is shown in Figure 25. Typical component values for the
application are shown in Ta bl e 6. A high quality ceramic capacitor in the range of 100 to 200
nF should be placed between the power pins (VS
to improve the high frequency filtering on the power supply and reduce high frequency
transients generated by the switching. The capacitors connected from the EN input to
ground set the shutdown time when an overcurrent is detected (see Section 4.9). The two
current sensing inputs (SENSE

and SENSEB) should be connected to the sensing

A

resistors with a trace length as short as possible in the layout. The sense resistors should be
non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise
immunity, unused logic pins (except EN) are best connected to 5 V (high logic level) or GND
(low logic level) (see Section 2). It is recommended to keep power ground and signal ground
separate on the PCB.

Table 6. Component values for typical application

Component Value

C

100 uF

1

C

100 nF

2

1 nF

C

A

1 nF

C

B

C

BOOT

10 nF

C

P

C

ENB

C

REF

1N4148

D

1

1N4148

D

2

R

39 kΩ

A

39 kΩ

R

B

R

EN

R

100 Ω

P

R

R

0.3 Ω

SENSEA

0.3 Ω

SENSEB

and VSB) and ground near the L6208Q

A

220 nF

5.6 nF

68 nF

100 kΩ

22/33 Doc ID 018710 Rev 2

L6208Q Application information

K

0

F

S

Figure 25. Typical application

VS

A

V

8-52V

+

S

DC

POWER

GROUND

-

SIGNAL

GROUND

34, 35

C

P

VBOOT

SENSE

SENSE

OUT1

OUT2

VCP

B

26, 27

40

21

A

45, 46

B

15, 16

A

2, 3

A

38, 39

C

C

1

2

D

1

R

P

BOOT

D

R

SENSEA

R

SENSEB

2

C

M

OUT1

B

GND

10, 11

B

22, 23

6, 31

OUT2

42VS

17

41

20

19

18

43

48

13

VREF

A

VREF

B

RESET

R

EN

EN

C

EN

CONTROL

HALF/FULL

CLOCK

CW/CCW

RC

A

RC

B

V

REF

C

REF

RESET

ENABL

FAS T/

HALF/

CLOC

CW/CC44

C

A

R

A

C

B

R

B

=

Note: To reduce the IC thermal resistance, therefore improving the dissipation path, the NC pins

can be connected to GND.

Doc ID 018710 Rev 2 23/33

Output current capability and IC power dissipation L6208Q

6 Output current capability and IC power dissipation

Figure 26, 27, 28 and 29 show the approximate relation between the output current and the

IC power dissipation using PWM current control driving a two-phase stepper motor, for
different driving sequences:

● HALF STEP mode (Figure 26) in which, alternately, one phase / two phases are

energized.

● NORMAL DRIVE (FULL STEP TWO-PHASE-ON) mode (Figure 27) in which two

phases are energized during each step.

● WAVE DRIVE (FULL STEP ONE-PHASE-ON) mode (Figure 28) in which only one

phase is energized at each step.

● MICROSTEPPING mode (Figure 29), in which the current follows a sinewave profile,

provided through the Vref pins.

For a given output current and driving sequence the power dissipated by the IC can be
easily evaluated, in order to establish which package should be used and how large the
onboard copper dissipating area must be to guarantee a safe operating junction
temperature (125 °C maximum).

Figure 26. IC power dissipation vs. output current in half step mode

PD [W]

10

HALF STEP

8

6

4

2

0

0 0.5 1 1.5 2 2.5 3

I

OUT

[A]

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24V

No PWM
f

= 30 kHz (slow decay)

SW

AM02570v1

24/33 Doc ID 018710 Rev 2

L6208Q Output current capability and IC power dissipation

Figure 27. IC power dissipation vs. output current in normal mode (full step two-

phase-on)

NORM AL DRIVE

10

8

I

A

I

B

I

OUT

6

PD [W]

I

OUT

4

2

0

00.511.522.53

I

[A]

OUT

Test Conditions:
Supply Voltage = 24 V

No PWM

= 30 kHz (slow decay)

f

SW

Figure 28. IC power dissipation vs. output current in wave mode (full step one-

phase-on)

WAVE DRIVE

PD [W]

10

8

6

4

2

0

0 0.5 1 1.5 2 2.5 3

I

[A]

OUT

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24V

No PWM

f

= 30 kHz (slow decay)

SW

AM02571v1

Figure 29. IC power dissipation vs. output current in micro stepping mode

PD [W]

MICROSTEPPING

10

8

6

4

2

0

00.511.522.53

I

[A]

OUT

Doc ID 018710 Rev 2 25/33

I

A

I

B

Test Conditions:
Supply Voltage = 24V

fSW = 30 kHz (slow decay)
fSW = 50 kHz (slow decay)

I

OUT

I

OUT

Thermal management L6208Q

7 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it must
be considered very carefully. Besides the available space on the PCB, the right package
should be chosen considering the power dissipation. Heat sinking can be achieved using
copper on the PCB with proper area and thickness.

26/33 Doc ID 018710 Rev 2

L6208Q Electrical characteristic curves

8 Electrical characteristic curves

Figure 30. Typical quiescent current vs.

Iq [m A ]

5.6

5.4

5.2

5.0

4.8

4.6
0 102030405060

supply voltage

fsw = 1kHz Tj = 25°C

[V]

V

S

Tj = 85°C

Tj = 125°C

AM02572v1

Figure 32. Normalized typical quiescent

Iq / (Iq @ 1 k Hz)

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

current vs. switching frequency

020406080100

f

SW

[kHz]

AM02574v1

Figure 31. Typical high-side R

DS(on)

voltage

R

[Ω]

DS(ON)

0.380

0.376

0.372

0.368

Tj = 25°C

0.364

0.360

0.356

0.352

0.348

0.344

0.340

0.336

0 5 10 15 20 25 30

[V]

V

S

Figure 33. Normalized R

DS(on)

vs.junction

temperature (typical value)

R

/ (R

DS(ON)

@ 25 °C)

Tj [°C]

DS(ON)

1.8

1.6

1.4

1.2

1.0

0.8
0 20406080100120140

vs. supply

AM02573v1

AM02575v1

Doc ID 018710 Rev 2 27/33

Electrical characteristic curves L6208Q

Figure 34. Typical low-side R

R

DS(ON)

voltage

[Ω]

DS(on)

vs. supply

0.300

0.296

0.292

Tj = 25°C

0.288

0.284

0.280

0.276
0 5 10 15 20 25 30

V

[V]

S

AM02576v1

Figure 35. Typical drain-source diode forward

ON characteristic

ISD[A]

3.0

2.5

2.0

1.5

1.0

0.5

0.0

700 800 900 1000 1100 1200 1300

Tj = 25°C

V

[mV]

SD

AM02577v1

28/33 Doc ID 018710 Rev 2

L6208Q Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

Table 7. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data

(mm)

Dim.

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0.02 0.05

A2 0.65 1.00

A3 0.25

b 0.18 0.23 0.30

D 6.85 7.00 7.15

D2 4.95 5.10 5.25

E 6.85 7.00 7.15

E2 4.95 5.10 5.25

e 0.45 0.50 0.55

L 0.30 0.40 0.50

ddd 0.08

Doc ID 018710 Rev 2 29/33

Package mechanical data L6208Q

Figure 36. VFQFPN48 (7 x 7 x 1.0 mm) package outline

30/33 Doc ID 018710 Rev 2

L6208Q Order codes

10 Order codes

Table 8. Ordering information

Order codes Package Packaging

L6208Q

QFN48 7 x 7 x 1.0 mm

L6208QTR Tape and reel

Tr ay

Doc ID 018710 Rev 2 31/33

Revision history L6208Q

11 Revision history

Table 9. Document revision history

Date Revision Changes

29-Jul-2011 1 First release

28-Nov-2011 2 Document moved from preliminary to final datasheet

32/33 Doc ID 018710 Rev 2

L6208Q

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Doc ID 018710 Rev 2 33/33