Features
■ Operating supply voltage from 8 to 52 V
■ 5.6 A output peak current
■ R
0.3 Ω typ. value @ TJ = 25 °C
DS(on)
■ Operating frequency up to 100 kHz
■ Non-dissipative overcurrent protection
■ Dual independent constant t
PWM current
OFF
controllers
■ Slow decay synchronous rectification
■ Cross conduction protection
■ Thermal shutdown
■ Undervoltage lockout
■ Integrated fast freewheeling diodes
Applications
■ Bipolar stepper motor
■ Dual or quad DC motor
Figure 1. Block diagram
L6207Q
DMOS dual full bridge driver
QFN-48
(7 x 7 mm)
Description
The L6207Q is a DMOS dual full bridge designed
for motor control applications, realized in
BCDmultipower technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. The device also
includes two independent constant OFF time
PWM current controllers that perform the
chopping regulation. Available in QFN48 7x7
package, the L6207Q features thermal shutdown
and a non-dissipative overcurrent detection on the
high-side Power MOSFETs.
VBOOT
VCP
EN
IN1
IN2
EN
IN1
IN2
V
BOOT
CHARGE
PUMP
OCD
A
THERMAL
PROTECTION
A
A
A
VOLTAGE
REGULATOR
5V10V
OCD
B
B
B
B
OVER
CURRENT
DETECTION
GATE
LOGIC
OVER
CURRENT
DETECTION
GATE
LOGIC
V
ONE SHOT
MONOSTABLE
BOOT
PWM
MASKING
TIME
V
BOOT
SENSE
COMPARATOR
BRIDGE A
BRIDGE B
V01V01
+
-
VS
A
OUT1
OUT2
SENSE
VREF
RC
A
V
S
B
OUT1
OUT2
SENSE
VREF
RC
B
A
A
A
A
B
B
B
B
AM02555v1
November 2011 Doc ID 018993 Rev 2 1/28
www.st.com
28
Contents L6207Q
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 15
4.6 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 20
7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28 Doc ID 018993 Rev 2
L6207Q Electrical data
1 Electrical data
1.1 Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol Parameter Parameter Value Unit
V
Supply voltage VSA = VSB = VS 60 V
S
Differential voltage between VS
V
OD
V
BOOT
V
IN,VEN
V
REFA
V
REFB
V
RCA,VRCB
V
SENSEA
V
SENSEB
Input and enable voltage range -0.3 to +7 V
,
,
, OUT2A, SENSEA and VSB,
OUT1
A
OUT1B, OUT2B, SENSE
B
Bootstrap peak voltage VSA = VSB = VS V
Voltage range at pins V
REFA
Voltage range at pins RCA and RC
Voltage range at pins SENSEA and
SENSE
B
Pulsed supply current (for each VS
I
S(peak)
pin), internally limited by the
overcurrent protection
IS RMS supply current (for each VS pin) VSA = VSB = VS 2.5 A
T
stg
, TOP
Storage and operating temperature
range
A
and V
,
VSA = VSB = VS = 60 V;
VSENSE
A
GND
REFB
B
= VSB = VS;
V
SA
t
< 1 ms
PULSE
= VSENSEB =
60 V
+ 10 V
S
-0.3 to +7 V
-0.3 to +7 V
-1 to +4 V
7.1 A
-40 to 150 °C
1.2 Recommended operating conditions
Table 2. Recommended operating conditions
Symbol Parameter Parameter Min. Max. Unit
V
Supply voltage VSA = VSB = VS 8 52 V
S
Differential voltage between VS
V
OD
V
V
,
SENSEA
SENSEB
I
RMS output current 2.5 A
OUT
T
j
f
sw
, OUT2A, SENSEA and VSB,
OUT1
A
, OUT2B, SENSEB
OUT1
B
Voltage range at pins SENSEA and
SENSEB
Operating junction temperature -25 +125 °C
Switching frequency 100 kHz
Doc ID 018993 Rev 2 3/28
,
A
= VSB = VS;
VS
A
V
SENSEA
Pulsed t
DC -1 1 V
= V
W
< t
SENSEB
rr
52 V
-6 6 V
Pin connection L6207Q
2 Pin connection
Figure 2. Pin connection (top view)
NC
OUT1A
OUT1A
NC
NC
GND
NC
NC
NC
OUT1B
OUT1B
NC
RCA
48 47 46 45 44 43 42 41 40 39 38 37
1
EPAD
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
RCB
SENSEANCIN2A
NC
SENSEB
SENSEA
SENSEB
IN1B
IN1A
IN2B
Note: The exposed PAD must be connected to GND pin.
Table 3. Pin description
VREFA
VREFB
ENA
VCPNCOUT2A
ENB
VBOOT
OUT2A
OUT2B
OUT2B
36
NC
35
VSA
34
VSA
33
NC
32
NC
31
GND
30
NC
29
NC
28
NC
27
VSB
26
VSB
25
NC
NC
AM02556v1
Pin Name Type Function
43 IN1A Logic input Bridge A logic input 1.
44 IN2A Logic input Bridge A logic input 2.
45, 46 SENSEA Power supply
48 RCA RC pin
Bridge A source pin. This pin must be connected to power ground
through a sensing power resistor.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF time of bridge A.
2, 3 OUT1A Power output Bridge A output 1.
6, 31 GND GND
Signal ground terminals. These pins are also used for heat dissipation
toward the PCB.
10, 11 OUT1B Power output Bridge B output 1.
13 RCB RC pin
15, 16 SENSEB Power supply
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF time of bridge B.
Bridge B source pin. This pin must be connected to power ground
through a sensing power resistor.
17 IN1B Logic input Bridge B input 1
4/28 Doc ID 018993 Rev 2
L6207Q Pin connection
Table 3. Pin description (continued)
Pin Name Type Function
18 IN2B Logic input Bridge B input 2
19 VREFB Analog input
Bridge B current controller reference voltage. Do not leave this pin open
or connect to GND.
Bridge B enable. Low logic level switches off all power MOSFETs of
Bridge B. This pin is also connected to the collector of the overcurrent
20 ENB Logic input
(1)
and thermal protection transistor to implement overcurrent protection. If
not used, it must be connected to +5 V through a resistor.
21 VBOOT Supply voltage
Bootstrap voltage needed for driving the upper power MOSFETs of both
Bridge A and bridge B.
22, 23 OUT2B Power output Bridge B output 2.
26, 27 VSB Power supply
34, 35 VSA Power supply
Bridge B power supply voltage. It must be connected to the supply
voltage together with pin VSA.
Bridge A power supply voltage. It must be connected to the supply
voltage together with pin VSB.
38, 39 OUT2A Power output Bridge A output 2.
40 VCP Output Charge pump oscillator output.
Bridge A enable. Low logic level switches off all power MOSFETs of
bridge A. This pin is also connected to the collector of the overcurrent
(1)
41 ENA Logic input
and transistor to implement overcurrent protection. If not used, it must be
connected to +5 V through a resistor. Thermal protection
42 VREFA Analog input
1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it must be driven putting
in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ.
Bridge A current controller reference voltage. Do not leave this pin open
or connect to GND.
Doc ID 018993 Rev 2 5/28
Electrical characteristics L6207Q
3 Electrical characteristics
VS = 48 V, TA = 25 °C, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
V
Sth(ON)
V
Sth(OFF)
Turn-on threshold 6.6 7 7.4 V
Turn-off threshold 5.6 6 6.4 V
IS Quiescent supply current
Thermal shutdown temperature 165 °C
T
j(OFF)
Output DMOS transistors
High-side switch ON resistance
R
DS(ON)
Low-side switch ON resistance
I
DSS
Leakage current
Source drain diodes
V
Forward ON voltage ISD = 2.5 A, EN = low 1.15 1.3 V
SD
t
rr
t
fr
Reverse recovery time If = 2.5 A 300 ns
Forward recovery time 200 ns
Logic input
All bridges OFF; Tj = -25 °C to
125 °C
(1)
510mA
Tj = 25 °C 0.34 0.4
Tj =125 °C
(1)
0.53 0.59
Ω
Tj = 25 °C 0.28 0.34
Tj =125 °C
EN = low; OUT = V
(1)
0.47 0.53
2mA
S
EN = low; OUT = GND -0.15 mA
V
V
I
I
V
th(ON)
V
th(OFF)
V
th(HYS)
IH
IL
IH
Low level logic input voltage -0.3 0.8 V
IL
High level logic input voltage 2 7 V
Low level logic input current GND logic input voltage -10 µA
High level logic input current 7 V logic input voltage 10 µA
Turn-on input threshold 1.8 2 V
Turn-off input threshold 0.8 1.3 V
Input threshold hysteresis 0.25 0.5 V
Switching characteristics
t
t
Enable to out turn ON delay time
D(on)EN
t
D(on)IN
t
RISE
D(off)EN
t
D(off)IN
Input to out turn ON delay time
Output rise time
Enable to out turn OFF delay time
Input to out turn OFF delay time I
(2)
(2)
I
LOAD
I
LOAD
time included)
I
LOAD
(2)
I
LOAD
LOAD
=2.5 A, resistive load 100 250 400 ns
=2.5 A, resistive load (dead
=2.5 A, resistive load 40 250 ns
=2.5 A, resistive load 300 550 800 ns
=2.5 A, resistive load 600 ns
6/28 Doc ID 018993 Rev 2
1.6 µs
L6207Q Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
Output fall time
FAL L
t
dt
f
CP
Dead time protection 0.5 1 µs
Charge pump frequency -25 °C<Tj <125 °C 0.6 1 MHz
PWM comparator and monostable
(2)
I
=2.5 A, resistive load 40 250 ns
LOAD
I
RCA
V
t
PROP
t
BLANK
t
ON(MIN)
t
I
BIAS
, I
offset
OFF
Source current at pins RCA and
RCB
RCB
Offset voltage on sense comparator V
Turn OFF propagation delay
Internal blanking time on SENSE
pins
(3)
V
RCA
REFA
= V
, V
= 2.5 V 3.5 5.5 mA
RCB
= 0.5 V ±5 mV
REFB
Minimum ON time 1.5 2 µs
R
PWM recirculation time
Input bias current at pins VREF
VREF
B
and
A
OFF
= 100 kΩ; C
R
OFF
= 20 kΩ; C
= 1 nF 13 µs
OFF
= 1 nF 61 µs
OFF
Over current detection
Input supply overcurrent detection
I
sover
R
OPDR
t
OCD(ON)
t
OCD(OFF)
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin V
4. See Figure 4.
threshold
Open drain ON resistance I = 4 mA 40 60 Ω
OCD turn-on delay time
OCD turn-off delay time
(4)
I = 4 mA; CEN < 100 pF 200 ns
(4)
-25 °C<Tj <125 °C 4 5.6 7.1 A
I = 4 mA; CEN < 100 pF 100 ns
REF
500 ns
1µs
10 µA
.
Doc ID 018993 Rev 2 7/28
Electrical characteristics L6207Q
Figure 3. Switching characteristic definition
EN
V
th(ON)
V
th(OFF)
t
I
OUT
90%
10%
D01IN1316
t
D(OFF)EN
t
FAL L
t
D(ON)EN
t
RISE
t
AM02557v1
Figure 4. Overcurrent detection timing definition
I
OUT
I
SOVER
ON
BRIDGE
OFF
V
EN
90%
10%
t
OCD(ON)
t
OCD(OFF)
AM02558v1
8/28 Doc ID 018993 Rev 2
L6207Q Circuit description
4 Circuit description
4.1 Power stages and charge pump
The L6207Q integrates two independent power MOSFET full bridges, each power MOSFET
has an R
conduction protection is implemented by using a dead time (t
internal timing circuit between the turn-off and turn-on of two power MOSFETs in one leg of
a bridge.
= 0.3 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross
DS(ON)
= 1 µs typical value) set by
DT
Pins VS
and VSB must be connected together to the supply voltage (VS).
A
Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate
drive voltage above the power supply voltage. The bootstrapped supply (V
) is obtained
BOOT
through an internal oscillator and a few external components to realize a charge pump
circuit, as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Tab le 5 .
Table 5. Charge pump external component values
Component Value
C
BOOT
C
P
R
P
220 nF
10 nF
100 Ω
D1 1N4148
D2 1N4148
Figure 5. Charge pump circuit
V
S
D1
R
C
VCP VBOOT VS
C
D2
P
P
BOOT
VS
A
B
AM02559v1
Doc ID 018993 Rev 2 9/28
Circuit description L6207Q
4.2 Logic inputs
Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and µC compatible logic inputs. The internal
structure is shown in Figure 6. Typical values for turn-on and turn-off thresholds are
respectively V
Pins EN
and ENB have identical input structures with the exception that the drains of the
A
overcurrent and thermal protection MOSFETs (one for bridge A and one for bridge B) are
also connected to these pins. Due to these connections, some care must be taken in driving
these pins. Two configurations are shown in Figure 7 and 8. If driven by an open drain
(collector) structure, a pull-up resistor R
Figure 7. If the driver is a standard push-pull structure, the resistor R
C
are connected, as shown in Figure 8. The resistor REN should be chosen in the range
EN
from 2.2 kΩ to 180 kΩ. Recommended values for R
5.6 nF. More information on selecting the values is found in Section 4.5.
Figure 6. Logic inputs internal structure
=1.8 V and V
thon
thoff
=1.3 V.
and a capacitor CEN are connected, as shown in
EN
and CEN are respectively 100 kΩ and
EN
5V
and the capacitor
EN
Figure 7. EN
Figure 8. EN
ESD
PROTECTION
and ENB pins open collector driving
A
5V
R
EN
OPEN
COLLECTOR
OUTPUT
and ENB pins push-pull driving
A
PUSH-PULL
OUTPUT
ENA or EN
R
EN
ENA or EN
B
C
EN
B
C
EN
AM02560v1
5V
AM02561v1
5V
10/28 Doc ID 018993 Rev 2
AM02562v1
L6207Q Circuit description
Table 6. Truth table
Inputs Outputs
EN IN1 IN2 OUT1 OUT2
L X
H L L GND GND Brake mode (Lower path)
H H L Vs GND (Vs)
H L H GND (Vs) Vs Reverse
H H H Vs Vs Brake Mode (Upper path)
1. Valid only in case of load connected between OUT1 and OUT2.
2. X = don’t care.
3. High Z = High impedance output.
4. GND (VS) = GND during Ton, VS during Ton.
X = Do not care.
High Z = High impedance output.
(2)
X High Z
4.3 PWM current control
The L6207Q includes a constant OFF time PWM current controller for each of the two
bridges. The current control circuit senses the bridge current by sensing the voltage drop
across an external sense resistor connected between the source of the two lower power
MOSFET transistors and ground, as shown in Figure 9. As the current in the load builds up,
the voltage across the sense resistor increases proportionally. When the voltage drop
across the sense resistor becomes greater than the voltage at the reference input (VREF
or VREF
off. The low-side MOSFET remains off for the time set by the monostable and the motor
current recirculates in the upper path. When the monostable times out, the bridge again
turns on. As the internal dead time, used to prevent cross conduction in the bridge, delays
the turn-on of the power MOSFET, the effective OFF time is the sum of the monostable time
plus the dead time.
), the sense comparator triggers the monostable switching the low-side MOSFET
B
(3)
Description
High Z Disable
(4)
Forward
(1)
A
Doc ID 018993 Rev 2 11/28
Circuit description L6207Q
Figure 9. PWM current controller simplified schematic
VS
(or B)
A
5mA
5V
C
TO GATE LOGIC
(0) (1)
RC
R
Q
-
+
2.5V
A(or B)
S
R
BLANKING TIME
MONOSTABLE
MONOSTABLE
RESET
1μs
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
GATE DRIVERS
DRIVERS
+
DEAD TIME
+
-
VREF
FROM THE
LOW-SIDE
A(or B)
2H 1H
DRIVERS
+
DEAD TIME
2L 1L
SENSE
R
SENSE
A(or B)
OUT2
OUT1
I
OUT
A(or B)
A(or B)
D02IN1352
LOAD
(orB)
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately
after the low-side Power MOSFET turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6207Q provides a 1 μs
blanking time t
that inhibits the comparator output so that this current spike cannot
BLANK
prematurely re-trigger the monostable.
A
Figure 10. Output current regulation waveforms
I
OUT
V
REF
R
SENSE
t
OFF
V
SENSE
V
REF
0
V
RC
5V
2.5V
ON
SYNCHRONOUS RECTIFICATION
OFF
D02IN1351
1μs t
BLANK
Slow Decay Slow Decay
t
RCRISE
t
RCFALL
1μs t
DT
BC
t
ON
BC
t
OFF
1μs t
t
RCRISE
t
RCFALL
1μs t
BLANK
DT
DDA
12/28 Doc ID 018993 Rev 2
L6207Q Circuit description
Figure 11 shows the magnitude of the OFF time t
versus COFF and ROFF values. It can be
OFF
approximately calculated from the equations:
t
RCFALL
t
OFF
where R
= 0.6 · R
= t
RCFALL
and C
OFF
· C
OFF
+ tDT = 0.6 · R
OFF
OFF
OFF
· C
OFF
+ t
DT
are the external component values and t
is the internally generated
DT
dead time with:
20 kΩ ≤ R
0.47 nF ≤ C
t
= 1 µs (typical value)
DT
OFF
OFF
≤ 100 kΩ
≤ 100 nF
therefore:
t
OFF(MIN)
t
OFF(MAX)
These values allow a sufficient range of t
The capacitor value chosen for C
pin R
COFF
= 6.6 µs
= 6 ms
. The rise time t
RCRISE
to implement the drive circuit for most motors.
OFF
also affects the rise time t
OFF
is only an issue if the capacitor is not completely charged
RCRISE
of the voltage at the
before the next time the monostable is triggered. Therefore, the ON time t
depends on motors and supply parameters, must be bigger than t
current regulation by the PWM stage. Furthermore, the ON time t
the minimum ON time t
ON(MIN)
.
RCRISE
can not be smaller than
ON
, which
ON
to allow a good
⎧
t
>
⎪
ONtON MIN()
⎨
t
⎪
ONtRCRISEtDT
⎩
t
RCRISE
–>
Figure 12 shows the lower limit for the ON time t
regulation capacity. It should be mentioned that t
the device imposes this condition, but it can be smaller than t
the device continues to work but the OFF time t
Therefore, a small C
value gives more flexibility to the applications (allows smaller ON
OFF
1.5μstyp()=
600 C
⋅=
OFF
for having a good PWM current
ON
is always bigger than t
ON
is not more constant.
OFF
- tDT. In this last case
RCRISE
ON(MIN)
time and, therefore, higher switching frequency), but, the smaller the value for C
more influential the noises on the circuit performance.
because
, the
OFF
Doc ID 018993 Rev 2 13/28
Circuit description L6207Q
Figure 11. t
OFF
vs. C
1.10
1.10
100
toff [μs]
and R
OFF
4
3
10
1
0.1 1 10 100
OFF
R
= 100k Ω
R
off
= 47kΩ
R
off
= 20k
Ω
off
Coff [nF]
Figure 12. Area where tON can vary maintaining the PWM regulation
100
10
ton(min) [μs]
1.5μs (typ. value)
1
Coff [nF]
4.4 Slow decay mode
Figure 13 shows the operation of the bridge in slow decay mode. At the start of the OFF
time, the lower power MOSFET is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After
the dead time the upper power MOSFET is operated in the synchronous rectification mode.
When the monostable times out, the lower power MOSFET is turned on again after some
delay set by the dead time to prevent cross conduction.
14/28 Doc ID 018993 Rev 2
0010111.0
L6207Q Circuit description
Figure 13. Slow decay mode output stage configurations
D01IN1336
1 )BEMIT NO )A μs DEAD TIME C) SYNCHRONOUS
RECTIFICATION
D) 1μs DEAD TIME
4.5 Non-dissipative overcurrent detection and protection
The L6207Q integrates an overcurrent detection circuit (OCD).
With this internal overcurrent detection, the external current sense resistor normally used
and its associated power dissipation are eliminated. Figure 14 shows a simplified schematic
of the overcurrent detection circuit for bridge A. Bridge B is provided by an analogous circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high-side power MOSFET. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I
output current reaches the detection threshold (typically 5.6 A) the OCD comparator signals
a fault condition. When a fault condition is detected, an internal open drain MOSFET with a
pull-down capability of 4 mA connected to the EN pin is turned on. Figure 15 shows the
OCD operation.
By using an external R-C on the EN pin, as shown in Figure 14, the OFF time before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs.
The disable time t
DISABLE
before recovering normal operation can be easily programmed by
means of the accurate thresholds of the logic inputs. It is affected by both C
values and its magnitude is reported in Figure 16. The delay time t
the bridge when an overcurrent has been detected depends only on the C
magnitude is reported in Figure 17.
REF. When the
EN
before turning off
DELAY
value. Its
EN
and REN
C
is also used for providing immunity to pin EN against fast transient noises. Therefore
EN
the value of C
delay time and the R
The resistor R
values for R
should be chosen as big as possible according to the maximum tolerable
EN
EN
and CEN are respectively 100 kΩ and 5.6 nF which allow to obtain 200 µs
EN
value should be chosen according to the desired disable time.
EN
should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
disable time.
Doc ID 018993 Rev 2 15/28
Circuit description L6207Q
Figure 14. Overcurrent protection simplified schematic
POWER SENSE
1 cell
POWER DMOS
n cells
OCD
OVER TEMPERATURE
μC or LOGIC
+5V
TO GATE
LOGIC
COMPARATOR
R
EN
EN
A
C
EN
R
40Ω TYP.
DS(ON)
INTERNAL
OPEN-DRAIN
Figure 15. Overcurrent protection waveforms
I
OUT
I
SOVER
OUT1
I1A/ n
VS
A
I1AI
+
(I1A+I2A) / n
I
REF
OUT2
A
2A
A
POWER DMOS
n cells
I2A/ n
HIGH SIDE DMOSs OF
THE BRIDGE A
POWER SENSE
1 cell
AM02563v1
V
EN
V
V
th(ON)
V
th(OFF)
ON
OCD
OFF
ON
BRIDGE
OFF
DD
t
OCD(ON)
t
DELAY
t
EN(FALL)
t
D(OFF)EN
t
OCD(OFF)
V
EN(LOW)
t
DISABLE
t
EN(RISE)
t
D(ON)EN
AM02564v1
16/28 Doc ID 018993 Rev 2
L6207Q Circuit description
Figure 16. t
Figure 17. t
DISABLE
1.10
1.10
[µs]
[µs]
DISABLE
DISABLE
t
t
DELAY
vs. CEN and REN (VDD = 5 V)
Ω
REN= 220 k
3
3
100
100
10
10
1
1
110100
110100
REN= 220 k
Ω
CEN[nF ]
CEN[nF ]
REN= 100 k
REN= 100 k
Ω
Ω
R
R
= 47 k
= 47 k
EN
EN
R
R
= 33 k
= 33 k
EN
EN
R
R
= 10 k
= 10 k
EN
EN
vs. CEN (VDD = 5 V)
10
Ω
Ω
Ω
Ω
Ω
Ω
s]
μ
1
tdelay [
0.1
1 10 100
4.6 Thermal protection
In addition to the overcurrent detection, the L6207Q integrates a thermal protection to
prevent device destruction in the case of junction overtemperature. It works sensing the die
temperature by means of a sensitive element integrated in the die. The device switches off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).
Cen [nF]
Doc ID 018993 Rev 2 17/28
Application information L6207Q
5 Application information
A typical application using L6207Q is shown in Figure 18. Typical component values for the
application are shown in Ta bl e 7. A high quality ceramic capacitor in the range of 100 to 200
nF should be placed between the power pins (VS
to improve the high frequency filtering on the power supply and reduce high frequency
transients generated by the switching. The capacitors connected from the EN
inputs to ground set the shutdown time for bridge A and bridge B, respectively, when an
overcurrent is detected (see Section 4.5). The two current sensing inputs (SENSE
SENSE
) should be connected to the sensing resistors with a trace length as short as
B
possible in the layout. The sense resistors should be non-inductive resistors to minimize the
di/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN
and ENB) are best connected to 5 V (high logic level) or GND (low logic level) (see
A
Section 2). It is recommended to keep power ground and signal ground separated on the
PCB.
Table 7. Component values for typical application
Component Value
100 uF
C
1
C
100 nF
2
1 nF
C
A
1 nF
C
B
C
BOOT
10 nF
C
P
C
ENA
C
ENB
C
REFA
C
REFB
D
1N4148
1
1N4148
D
2
39 kΩ
R
A
R
39 kΩ
B
100 kΩ
R
ENA
100 kΩ
R
ENB
R
100 Ω
P
R
R
0.3 Ω
SENSEA
0.3 Ω
SENSEB
and VSB) and ground near the L6207Q
A
and ENB
A
and
A
220 nF
5.6 nF
5.6 nF
68 nF
68 nF
18/28 Doc ID 018993 Rev 2
L6207Q Application information
Figure 18. Typical application
VS
VS
8-52V
+
DC
POWER
GROUND
-
SIGNAL
GROUND
A
34, 35
P
VCP
C
P
VBOOT
SENSE
SENSE
OUT1
OUT2
OUT1
OUT2
GND
B
26, 27
40
21
A
45, 46
B
15, 16
A
2, 3
A
38, 39
B
10, 11
B
22, 23
6, 31
C
1
C
2
D
1
R
D
C
BOOT
R
SENSEA
R
SENSEB
LOAD
LOAD
2
A
B
VREF
VREF
EN
EN
IN1
IN2
IN1
IN2
RC
RC
A
B
C
REFA
A
B
C
ENA
B
B
A
A
C
A
A
R
A
C
B
B
R
B
IN1
IN2
IN1
IN2
C
R
R
C
B
B
A
A
REFB
ENA
ENB
ENB
V
V
REFA
REFB
EN
EN
= 0-1V
= 0-1V
A
B
42VS
19
41
20
17
18
43
44
48
13
AM02566v1
Note: To reduce the IC thermal resistance, therefore improving the dissipation path, the NC pins
can be connected to GND.
Doc ID 018993 Rev 2 19/28
Output current capability and IC power dissipation L6207Q
6 Output current capability and IC power dissipation
Figure 19 and 20 show the approximate relation between the output current and the IC
power dissipation using PWM current control driving two loads, for two different driving
types:
● One full bridge ON at a time (Figure 19) in which only one load at a time is energized.
● Two full bridges ON at the same time (Figure 20) in which two loads are energized at
the same time.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large the onboard
copper dissipating area must be to guarantee a safe operating junction temperature (125 °C
maximum).
Figure 19. IC power dissipation vs. output current with one full bridge ON at a time
ONE FULL BRIDGE ON AT A TIME
10
I
A
I
OUT
8
6
PD [W]
4
I
B
I
OUT
Test Conditions:
2
Supply Voltage = 24V
No PWM
0
00.511.522.5 3
I
[A]
OUT
f
= 30kHz (slow decay)
SW
AM02570v1
Figure 20. IC power dissipation vs. output current with two full bridges ON at the
same time
TWO FULL BRIDGES ON AT THE SAME TIME
10
8
6
PD [W]
4
I
A
I
B
I
OUT
I
OUT
2
0
00.511.522.53
[A]
I
OUT
20/28 Doc ID 018993 Rev 2
Test Conditions:
Supply Voltage = 24V
No PWM
= 30kHz (slow decay)
f
SW
AM02571v1
L6207Q Thermal management
7 Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it must
be considered very carefully. Besides the available space on the PCB, the right package
should be chosen considering the power dissipation. Heatsinking can be achieved using
copper on the PCB with proper area and thickness.
Doc ID 018993 Rev 2 21/28
Electrical characteristics curves L6207Q
8 Electrical characteristics curves
Figure 21. Typical quiescent current vs.
Iq [m A ]
5.6
5.4
5.2
5.0
4.8
4.6
0 102030405060
supply voltage
fsw = 1kHz Tj = 25°C
[V]
V
S
Tj = 85°C
Tj = 125°C
AM02572v1
Figure 23. Normalized typical quiescent
Iq / (Iq @ 1 k Hz)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
current vs. switching frequency
020406080100
f
[kHz]
SW
AM02574v1
Figure 22. Typical high-side R
DS(on)
voltage
R
[Ω]
DS(ON)
0.380
0.376
0.372
0.368
Tj = 25°C
0.364
0.360
0.356
0.352
0.348
0.344
0.340
0.336
0 5 10 15 20 25 30
[V]
V
S
Figure 24. Normalized R
DS(on)
vs. junction
temperature (typical value)
R
/ (R
DS(ON)
@ 25 °C)
Tj [°C]
DS(ON)
1.8
1.6
1.4
1.2
1.0
0.8
0 20406080100120140
vs. supply
AM02573v1
AM02575v1
22/28 Doc ID 018993 Rev 2
L6207Q Electrical characteristics curves
Figure 25. Typical low-side R
R
DS(ON)
voltage
[Ω]
DS(on)
vs. supply
0.300
0.296
0.292
Tj = 25°C
0.288
0.284
0.280
0.276
0 5 10 15 20 25 30
V
[V]
S
AM02576v1
Figure 26. Typical drain-source diode forward
ON characteristic
ISD[A]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
700 800 900 1000 1100 1200 1300
Tj = 25°C
V
[mV]
SD
AM02577v1
Doc ID 018993 Rev 2 23/28
Package mechanical data L6207Q
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 8. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data
(mm)
Dim.
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.02 0.05
A2 0.65 1.00
A3 0.25
b 0.18 0.23 0.30
D 6.85 7.00 7.15
D2 4.95 5.10 5.25
E 6.85 7.00 7.15
E2 4.95 5.10 5.25
e 0.45 0.50 0.55
L 0.30 0.40 0.50
ddd 0.08
24/28 Doc ID 018993 Rev 2
L6207Q Package mechanical data
Figure 27. VFQFPN48 (7 x 7 x 1.0 mm) package outline
Doc ID 018993 Rev 2 25/28
Order codes L6207Q
10 Order codes
Table 9. Ordering information
Order codes Package Packaging
L6207Q
VFQFPN48 7x7x1.0 mm
L6207QTR Tape and reel
Tr ay
26/28 Doc ID 018993 Rev 2
L6207Q Revision history
11 Revision history
Table 10. Document revision history
Date Revision Changes
29-Jul-2011 1 First release
28-Nov-2011 2 Document moved from preliminary to final datasheet
Doc ID 018993 Rev 2 27/28
L6207Q
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28/28 Doc ID 018993 Rev 2
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