The L6207 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BLOCK DIAGRAM
0.3Ω TYP. VA LUE @ Tj = 25 °C
DS(ON)
OFF
PWM
L6207
PowerDIP24
(20+2+2)
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on
the same chip. The device al so includes two independent constant off time PWM Current Controllers
that performs the chopping regulation. Available in
PowerDIP24 (20+2+2), PowerSO36 and SO24
(20+2+2) packages, the L6207 features a non-di ssi pative overcurrent protection on the high side Power
MOSFETs and thermal shutdown.
(1)Mounted on a multi-layer FR4 PCB with a dissipati ng copper surface on the bottom side of 6cm2 (with a thickness of 35µm).
(2)Mounted on a multi-layer FR4 PCB with a dissipati ng copper surface on the top side of 6cm2 (with a thickness of 35µm).
(3)Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes
and a groun d l ayer.
(4)Mounted on a multi-layer FR4 PCB without any hea t s i nking surfac e on the board.
PIN CONNECTIONS (Top View)
Maximum Thermal Resistance Junction-Pins1814-°C/W
Maximum Thermal Resistance Junction-Case--1°C/W
Maximum Thermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
1
2
3
4
4351-°C/W
--35°C/W
--15°C/W
587762°C/W
IN1
IN2
SENSE
RC
OUT1
GND
GND
OUT1
RC
SENSE
IN1
IN2
1
A
2
A
3
A
4
A
5
A
6
7
8
B
9
B
10
B
11
B
12
B
D02IN1346
VREF
24
23
22
21
20
EN
VCP
OUT2
VS
A
A
A
A
GND19
GND
18
VS
17
B
OUT2
16
15
14
13
VBOOT
EN
B
VREF
B
B
PowerDIP24 /SO2 4
(5)The slug is internally connected to pins 1,18,19 and 36 (GND pins).
GND
N.C.
N.C.
VS
OUT2
N.C.N.C.
VCP
EN
VREF
IN1
IN2
SENSE
RC
N.C.
OUT1
N.C.
N.C.N.C.
GNDGND
1
2
3
4
A
5
A
6
7
8
A
9
A
1027
A
11
A
12
A
1324
A
14
15
A
16
17
18
D02IN1347
PowerSO36
36
35
34
33
32
31
30
29
28
26
25
23
22
21
20
19
(5)
GND
N.C.
N.C.
VS
B
OUT2
VBOOT
EN
B
VREF
IN2
B
IN1
B
SENSE
RC
B
N.C.
OUT1
N.C.
B
B
B
B
3/23
L6207
PIN DESCRIPTION
P ACKAGE
SO24/
PowerDIP24
PowerSO36
NameT ypeFunction
PIN #PIN #
110IN1
211IN2
312SENSE
413RC
515OUT1
6, 7,
18, 19
1, 18,
19, 36
GNDGNDSignal Ground terminals. In Power DIP and SO packages,
822OUT1
924RC
1025SENSE
1126IN1
1227IN2
1328VREF
1429EN
A
A
Logic inputBridge A Logic Input 1.
Logic inputBridge A Logic Input 2.
Power Supply Bridge A Source Pin. This pin must be connected to Power
A
Ground through a sensing power resistor.
A
RC PinRC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
Power OutputBridge A Output 1.
A
these pins are also used for heat dissipation toward the
PCB.
Power OutputBridge B Output 1.
B
B
RC PinRC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
Power Supply Bridge B Source Pin. This pin must be connected to Power
B
Ground through a sensing power resistor.
B
B
Logic InputBridge B Input 1
Logic InputBridge B Input 2
Analog InputBridge B Current Controller Reference Voltage.
B
Do not leave this pin open or connect to GND.
(6)
B
Logic Input
Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
1530VBOOTSupply
Voltage
1632OUT2
1733VS
Power OutputBridge B Output 2.
B
Power Supply Bridge B Power Supply Voltage. It must be connected to
B
Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
the supply voltage together with pin VS
204VS
Power Supply Bridge A Power Supply Voltage. It must be connected to
A
the supply voltage together with pin VS
215OUT2
Power OutputBridge A Output 2.
A
227VCPOutputCharge Pump Oscillator Output.
4/23
.
A
.
B
L6207
PIN DESCRIPTION
238EN
(continued)
A
Logic Input
(6)
Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
249VREF
Analog InputBridge A Current Controller Reference Voltage.
A
Do not leave this pin open or connect to GND.
(6) Al so connec te d at the ou tput drain of the Over current and Thermal protecti on MOSFET . Therefore, it has to be driven putting in
series a re si stor with a v al ue in the ran ge of 2.2KΩ - 180KΩ, recomme nded 100KΩ.
Enable to out turn ON delay time
Input to out turn ON delay time
Output rise time
(8)
Enable to out turn OFF delay time
Input to out turn OFF delay time
Output Fall Time
Dead Time Protection0.51µs
t
dt
CP
Charge pump frequency
(8)
PWM Comparator and Monostable
(8)
=2.8A, Resistive Load100250400ns
LOAD
I
=2.8A, Resistive Load
LOAD
1.6µs
(dead time included)
I
=2.8A, Resistive Load40250ns
LOAD
I
=2.8A, Resistive Load300550800ns
LOAD
I
=2.8A, Resistive Load600ns
LOAD
I
=2.8A, Resistive Load40250ns
LOAD
-25°C<Tj <125°C0.61MHz
I
RCA, IRCB
V
offset
Source Current at pins RCA and
RC
B
Offset Voltage on Sense
V
= V
RCA
V
REFA, VREFB
= 2.5V3.55.5mA
RCB
= 0.5V±5mV
Comparator
t
PROP
t
BLANK
Turn OFF Propagation Delay
Internal Blanking Time on
(9)
SENSE pins
t
ON(MIN)
t
OFF
I
BIAS
Minimum On Time1.52µs
PWM Recirculation TimeR
R
OFF
OFF
= 20KΩ; C
= 100KΩ; C
OFF
OFF
= 1nF
= 1nF
Input Bias Current at pins VREFA
and VREFB
Over Current Protection
I
SOVER
R
OPDR
t
OCD(ON)
t
OCD(OFF)
(7)Tested at 25°C in a restricted range and guaranteed by characterization.
(8)See Fig. 1.
(9)Measured applying a voltage of 1V to pin SEN S E and a voltag e drop from 2V to 0V to pin VREF.
(10)See Fig. 2.
Input Supply Overcurrent
Protection Threshold
= -25°C to 125°C
T
j
Open Drain ON ResistanceI = 4mA4060Ω
OCD Turn-on Delay Time (10)I = 4mA; CEN < 100pF200ns
OCD Turn-off Delay Time (10)I = 4mA; CEN < 100pF100ns
(7)
45.67.1A
500ns
1µs
13
61
µs
µs
10µA
6/23
Figure 1. Switching Characteristic Definition
EN
V
th(ON)
V
th(OFF)
I
OUT
90%
10%
D01IN1316
t
D(OFF)EN
t
FALL
Figure 2. Ove rcurrent Detect i on Timi ng Definition
t
D(ON)EN
t
RISE
L6207
t
t
I
OUT
I
SOVER
ON
BRIDGE
OFF
V
EN
90%
10%
t
OCD(ON)
t
OCD(OFF)
D02IN1399
7/23
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