ST L5988D User Manual

L5988D

4 A continuous (more than 5 A pulsed) step-down switching regulator with synchronous rectification

Features

■4 A output current (more than 5 pulsed)

■Operating input voltage from 2.9 V to 18 V

■External 1.8 V ± 2% reference voltage

■Output voltage from 0.6 to input voltage

■MLCC compatible

■200 ns TON

■Programmable UVLO matches 3.3 V, 5 V and 12 V bus

■FSW programmable up to 1 MHz

■Voltage feed-forward

■Zero-load current operation

■Programmable current limit on both switches

■Programmable sink current capability

■Pre-bias start up capability

■Thermal shutdown

HTSSOP 16

Applications

■Consumer: STB, DVD, LCD TV, VCR, car radio, LCD monitors

■Networking: XDSL, modems, routers and switches

■Computer and peripherals: printers, audio / graphic cards, optical storage, hard disk drive

■Industrial: DC-DC modules, factory automation

■HC LED driving

Figure 1. Test application circuit

January 2010

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www.st.com

Contents	L5988D

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
3	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
5	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	5.1	Multifunction pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	5.2	Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	5.3	External voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.4	Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.5	Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19

5.5.1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.2 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.3 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5.4 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.6 Minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			25
	6.1	Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	6.2	Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	6.3	Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	6.4	Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
		6.4.1	Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
		6.4.2	Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33

6.5 R.M.S. current of the embedded power MOSFETs . . . . . . . . . . . . . . . . . 36 6.6 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.7 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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L5988D		Contents
7	Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 45
8	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 48
9	Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 50
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 51

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List of table	L5988D

List of table

Table 1. Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. A/D voltage windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. UOS voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. FSW resistor examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. ILIM-ADJ resistor examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10. Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. Component list application circuit (fSW = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 14. Component list application circuit (fSW = 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 15. HTSSOP16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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L5988D	List of figures

List of figures

Figure 1. Test application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Voltage mode control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Sawtooth: voltage feed forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Sawtooth: synchronization and frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Input RMS current of two synchronized regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. OVP not latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10. OVP latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. constant current protection at extreme duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. minimum TON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. Type III compensation network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 14. Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 15. Open loop gain bode diagram with ceramic output capacitor. . . . . . . . . . . . . . . . . . . . . . . 32 Figure 16. Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 17. Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 18. Open loop gain bode diagram with high ESR output capacitor . . . . . . . . . . . . . . . . . . . . . 35 Figure 19. Maximum continuos output current vs. duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 20. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 21. Estimation of the internal power losses (VIN = 12 V, VOUT = 1.2 V, fSW = 400 kHz) . . . . 38 Figure 22. Estimation of the internal power losses (VIN = 5 V, VOUT = 1.2 V, fSW = 400 kHz) . . . . . 39 Figure 23. Measurement of the thermal impedance of the evaluation board. . . . . . . . . . . . . . . . . . . . 40 Figure 24. Top board layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 25. Bottom board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 26. Demonstration board application circuit (fSW = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 27. Demonstration board application circuit (fSW = 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 28. Junction temperature vs. fSW at VIN = 12 V, VOUT = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 29. Junction temperature vs. fSW at VIN = 5 V, VOUT = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 30. Junction temperature vs. fSW at VIN = 3.3 V, VOUT = 1.2 V. . . . . . . . . . . . . . . . . . . . . . . 45 Figure 31. Junction temperature vs. VOUT at VIN = 12 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . . 45 Figure 32. Junction temperature vs. VOUT at VIN = 5 V, fSW = 400 kHz. . . . . . . . . . . . . . . . . . . . . . 46 Figure 33. Junction temperature vs. VOUT at VIN = 3.3 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . 46 Figure 34. Efficiency vs. output current at VIN = 3.3 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 35. Efficiency vs. output current at VIN = 5 V, fSW = 250 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 36. Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 37. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 38. Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 39. Load transient from 0 to 3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 40. Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 41. HTSSOP16 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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Description	L5988D

1 Description

The L5988D is a monolithic step down power switching regulator able to deliver a continuos output current of 4 A to the load in most of the application conditions limited only by the thermal performance (see Chapter 6.5 for details). The device is able to deliver more than 5 A to the load for a maximum time which is dependent on the thermal impedance of the system and the specific operating conditions (see Chapter 6.6).

The input voltage can range from 2.9 V to 18 V. The device is capable of 100% duty cycle operation thanks to the embedded high side PMOS switch which doesn’t need external bootstrap capacitor to be driven.

The internal switching frequency is adjustable by external resistor and can be set continuously from 100 kHz to 1 MHz. The L5988D can also be synchronized to an external frequency signal driven to the SYNCH pin I/O pin.

The multifunction UOS pin allows to set-up properly the additional embedded features depending on the value of the voltage level.

●U (UVLO): two UVLO thresholds can be selected to match the 3.3 V and 5 V or 12 V input buses

●O (OVP): latched or not latched OVP protection selectable. In latched mode the switching activity is interrupted until an UVLO or INH event happens

●S (SINK): the sink capability is always disabled during soft-start time to support prebiased output voltage. Afterwards the sink capability can be enabled or not depending on the voltage set on the multifunction pin.

During soft-start phase a constant current protection is active to deliver extra current necessary to load the output capacitor. The current limit protection is achieved by sensing the current flowing in both embedded switches to assure an effective protection even at extreme duty cycle operations. Finished the soft-start phase the current protection feature triggers the “HICCUP” mode forcing the soft-start capacitor to be discharged and recharged. The current thresholds of both switches can be adjusted in tracking by using an external resistor to dimension the current protection accordingly to the local application.

The soft-start time is based on a constant current charge of an external capacitor. As a consequence the time can be set accordingly to the value of the output capacitor.

The latest smart power technology BCD6 (Bipolar-CMOS-DMOS version 6) features a low resistance of the embedded switches (35 mΩ typical for a NMOS, 50 mΩ typical for a PMOS), achieving high efficiency levels.

The HTSSOP16 package with exposed pad accomplishes low RthJA (40 °C/W), useful in dissipating power internally generated during high output current / high frequency operations.

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L5988D	Pin function

2 Pin function

Figure 2. Pin connection

	Table 1.	Pinout description
	N.	Name			Description
	1, 16	OUT			Regulator output
	2, 3	VIN			Unregulated DC input voltage
	4	VCC			Unregulated DC signal input voltage
					An external logic signal (active LOW) disables the device. In case the pin is
	5				floating the device deliver a constant current (22 μA typ.) to charge the
		SS/INH
					soft-start capacitor (see 5.4)
	6	COMP			Error amplifier output for frequency compensation
					Connecting a pull-up resistor to VREF or a pull-down resistor to GND the
	7	ILIM-ADJ			internal current limit thresholds can be tuned to match the local application.
					In case the pin is left floating no changes are applied to the default current
					limit thresholds
					Feedback input. Connecting the output voltage directly to this pin results in
	8	FB			a regulation voltage of 600 mV. An external resistive divider is required for
					higher output voltages
	9	SYNCH			Master/slave synchronization
					Connecting a pull-up resistor to VREF or a pull-down resistor to GND the
	10	FSW			internal oscillator frequency will be increased or decreased respectively. In
					case the pin is left floating the predefined oscillator frequency
					(400 kHz ± 10%) is active
	11	U/O/S			Multifunction pin used to program additional features: UVLO thresholds,
					OVP latched/not latched, SINK enabled/disabled
	12	VREF			1.8 V voltage reference
	13	SGND			Signal ground
	14, 15	PGND			Power ground

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Maximum ratings	L5988D

3 Maximum ratings

Table 2.		Absolute maximum ratings
Symbol				Parameter	Value	Unit
VCC				Input voltage	20	V
VOUT				Output DC voltage	-0.3 (1)to VCC	V
U/O/S, SS/INH,
COMP, SYNCH,				Analog pins	-0.3 to 4	V
Fsw, ILIM-ADJ
FB				Feedback voltage	1.5	V
Ptot				Power dissipation at TA < 60 °C	2.25	W
TJ				Junction temperature range	-40 to 150	°C
TSTG				Storage temperature range	-55 to 150	°C

1.During the switching activity the negative peak voltage could reach -1.5 V without any damage for the device

Table 3.	Thermal data
Symbol		Parameter	Value	Unit
R		Thermal resistance junction to ambient max	40 (1)	°C/W
thJA

1. HTSSOP16 package mounted on ST demonstration board

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L5988D	Electrical characteristics

4 Electrical characteristics

	VCC = 12 V, TJ = 25 °C unless otherwise specified.
	Table 4.			Electrical characteristic
	Symbol			Parameter	Test condition			Min	Typ	Max	Unit
		VCC		Operating input voltage	Vout = 0.6 V; Iout=3 A			2.9		18	V
				range
	R		HS	High side MOSFET on	Iout=1.0 A			75	85	95	mΩ
	DS(on)			resistance			(1)	111	120	132	mΩ
	R		LS	Low side MOSFET on	Iout=1.0 A			62	67	72	mΩ
		DS(on)
				resistance			(1)	92	100	106	mΩ
	IL HIGH SIDE			Maximum peak limiting	ILIM-ADJ = float			3.6	4	4.4	A
				current
	IL LOW SIDE			Maximum valley limiting	ILIM-ADJ = float			4.14	4.6	5.06	A
				current
		fSW		Switching frequency	FSW = floating			360	400	440	kHz
		fSW ADJ		adjusted switching	RFSW PULL DWN = 27 kΩ				1000		kHz
				frequency
		D		Duty cycle				0		100	%
	Selectable under voltage lock-out (UVLO)
				Turn ON Vcc threshold					2.7	2.8	V
	3.3 V BUS			Turn OFF Vcc threshold				2.4	2.5		V
				Hysteresis					200		mV
				Turn ON Vcc threshold					8	8.6	V
	12 V BUS			Turn OFF Vcc threshold				6.8	7		V
				Hysteresis					1		V
	DC characteristic
		ISS		Soft-start current	VSS/INH	= 2 V			22		μA
					VSS/INH	= 0			5		μA
		INH		Device ON level				0.8			V
				Device OFF level						0.3	V
		Iq		Quiescent current	Duty Cycle = 0;					3	mA
					VFB = 1 V
		Iq st-by		Total stand-by quiescent						35	μA
				current

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Electrical characteristics								L5988D
	Table 4.	Electrical characteristic (continued)
	Symbol	Parameter	Test condition			Min	Typ	Max	Unit
	Dynamic characteristic (see figure 1)
	VFB	Voltage feedback in	2.9 V < VCC < 18 V			0.595	0.6	0.605	V
		regulation			(1)	0.592	0.6	0.609
	Error amplifier
	VOH	High level output voltage	VFB = 0.2 V; SS floating			3.1			V
	VOL	Low level output voltage	VFB = 1.0 V					0.1	V
	IO SOURCE	Source output current	VFB = 0.2 V		(2)		25		mA
	IO SRCE LIM	Source current limitation	VFB = 0.2 V, VCOMP = 3 V				2		mA
	IO SINK	Sink output current	VFB = 1.0 V, VCOMP = 0.5 V				30		mA
	AV0	DC open loop gain			(2)		100		dB
	Sync function
		High input voltage				2.9		4.0	V
		Low input voltage						0.74	V
		Slave sink current	VSYNC = 3.3 V;				1		mA
			FSW = float
		Master output amplitude	ISOURCE = 5 mA			2.9			V
		Output pulse width	SYNCH = floating				100		ns
		Input pulse width				70			ns
	Reference section
	VREF	Reference voltage	Vcc = 2.9 V to 18 V			1.756	1.8	1.837	V
					(1)	1.754	1.8	1.852	V
		Line regulation	Vcc = 2.9 V to 18 V				6	12	mV
			IREF = 0 mA
		Load regulation	IREF = 0 to 5 mA				7.5	15	mV
		Short circuit current				12	18	24	mA
	Protections
	VFB_OVP	Overvoltage trip	VFB rising			15	20	24	%
		(VFB_OVP - VFB) / VFB							VFB
	Bus thresholds
		- UVLO 3.3 V bus
	TH1	- OVP not latched			(3)	0		0.2	V
		- No sink
		- UVLO 3.3 V bus
	TH2	- OVP not latched			(3)	0.26		0.425	V
		- Sink

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L5988D						Electrical characteristics
	Table 4.	Electrical characteristic		(continued)
	Symbol	Parameter		Test condition		Min	Typ	Max	Unit
		- UVLO 3.3 V bus
	TH3	- OVP latched			(3)	0.48		0.65	V
		- No sink
		- UVLO 3.3 V bus
	TH4	- OVP latched			(3)	0.71		0.875	V
		- Sink
		- UVLO 12 V bus
	TH5	- OVP not latched			(3)	0.93		1.085	V
		- No sink
		- UVLO 12 V bus
	TH6	- OVP not latched			(3)	1.16		1.31	V
		- Sink
		- UVLO 12 V bus
	TH7	- OVP latched			(3)	1.385		1.525	V
		- No sink
		- UVLO 12 V bus
	TH8	- OVP latched			(3)	1.615		VREF	V
		- Sink

1.Specification over the junction temperature range (TJ) of -40 to +125 °C are guaranteed by design, characterization and statistical correlation

2.Guaranteed by design

3.VCC = 4 V

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Functional description	L5988D

5 Functional description

The L5988D is based on a voltage mode control loop. Therefore the duty ratio of the internal switch is obtained through a comparison between a saw-tooth waveform (generated by an oscillator) and the output voltage of the error amplifier as shown in Figure 3. The advantage of this technique is the very short conduction time of the power elements thanks to the proper operation of the control loop without a precise current sense, which instead is required in current mode regulators. Thanks to this architecture the L5988D supports extremely low conversion ratio (D = VOUT/VIN) even at very high switching frequency

(up to 1 MHz).

Figure 3. Voltage mode control loop

VOUT OSCILLATOR RAMP

	VREF	-
	+	PWM
		+
	E/A
	-

The main internal blocks are represented in Figure 4.

Figure 4. Internal block diagram

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L5988D	Functional description

Below follows a brief description of the main blocks:

●A voltage pre-regulator supplies the internal circuitry. The external 1.8 V voltage reference is supplied by this regulator.

●A voltage monitor circuit that checks the input and internal voltages

●A fully integrated sawtooth oscillator whose frequency is 400 kHz ± 10% when the Fsw pin is floating. Its frequency can be increased/decreased connecting a proper resistor to GND or VREF

●The internal current limitation circuitry monitors the current flowing in both embedded switches to guarantee an effective protection even in extreme duty cycle conditions

●The over voltage protection (OVP) monitors the feedback voltage. If the voltage of this pin overcomes the 20% of the internal reference value (600 mV ± 1%) it will force the conduction of the low side switch until the overshoot is present

●A voltage mode amplifier. The inverting input and the output are externally available for compensation

●A pulse width modulator (PWM) comparator and the relative logic to drive the embedded switches

●The soft-start circuit charges an external capacitor with a constant current equal to 20 µA (typ.). The soft-start feature is realized clamping the output of the error amplifier until the voltage across the capacitor is below 2.7 V

●The circuitry acting on the SYNCH pin provides external signal reference to slave devices when the regulator works as a master or accept the synchronization from an external reference source

●The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. It recognizes eight different voltage windows of a VREF voltage magnitude for selecting additional features.

●An inhibit block for stand-by operation

●A circuit to realize the thermal protection function

5.1Multifunction pin

The UOS pin is used to configure the device additional features accordingly to the voltage bias imposed through VREF voltage partitioning.

The selectable options are:

●UVLO level: two pre-defined the under voltage lock out thresholds can be selected to match the 3.3 V and 5 V or 12 V power bus

●SINK capability: this feature is always disabled during the soft-start period to be compatible with pre-biased output voltages. After the soft-start phase, the synchronous rectification can be enabled or not depending on the status of the UOS pin. Anyway, in case an overvoltage is detected, the sink capability is always enabled to bring the FB back to regulation as fast as possible

●OVP management: in case the latched mode is selected and an overvoltage event recurs, the switching activity will be suspended until VCC is reapplied or the SS/INH pin is toggled. Otherwise when the overvoltage transient is ended the regulator will work accordingly to the load request without regulation discontinuity

The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. Table 5 shows the internal thresholds of each voltage window

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Functional description	L5988D

composing the VREF magnitude. The voltage biasing of the multifunction can be set accordingly to table Table 6.

	Table 5.		A/D voltage windows
			UVLO	OVP	SINK
	1.8	V
			12 V BUS	LATCH	SINK
	1.575 V
			12 V BUS	LATCH	NO SINK
	1.35	V
			12 V BUS	NO LATCH	SINK
	1.125	V
			12 V BUS	NO LATCH	NO SINK
	0.9	V
			3.3 V BUS	LATCH	SINK
	0.675 V
			3.3 V BUS	LATCH	NO SINK
	0.45 V
			3.3 V BUS	NO LATCH	SINK
	0.225 V
			3.3 V BUS	NO LATCH	NO SINK
	0 V

Table 6.	UOS voltage biasing
R1 (kΩ)		R2 (kΩ)		VOUS (V)	UVLO	OVP	SINK
0		N.C.		1.8	12 V BUS	LATCH	SINK
0.68		2.7		1.438	12 V BUS	LATCH	NO SINK
1.2		2.7		1.246	12 V BUS	NO LATCH	SINK
2		2.7		1.034	12 V BUS	NO LATCH	NO SINK
3.3		2.7		0.810	3.3 V BUS	LATCH	SINK
6.2		2.7		0.546	3.3 V BUS	LATCH	NO SINK
11		2.7		0.355	3.3 V BUS	NO LATCH	SINK
N.C.		0		0	3.3 V BUS	NO LATCH	NO SINK

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L5988D	Functional description

5.2Oscillator and synchronization

The generation of the internal saw-tooth waveform is based on the constant current charge / discharge of an internal capacitor. The current generator is designed to get a switching frequency of 400 kHz ± 10% in case the FSW pin is left floating.

The current mirror connected to FSW (see Figure 5.) pin acts increasing / decreasing the value of the internal charging current to adjust the oscillator frequency. Since the internal circuitry forces the FSW voltage bias at 1.235 V, the user can easily source / sink current in this pin connecting a pull up resistor to VREF or a pull down to GND respectively.

Figure 5. Oscillator circuit block diagram

	VREF
	Clock
	Clock	SYNCH
	Synchronization
	Generator
	Ramp	Sawtooth
	Generator

The value of the pull up resistor versus VREF to decrease the oscillator frequency follows the formula:

	R1(KΩ) =	8.5 103	+ 0.95
		400------------–----F----SW---------(--KHz-------------)

In the same way to increase the switching frequency the pull down resistor is selected using the formula:

R2	(KΩ) =	18 103
		F----SW---------(--KHz-------------)---	------------- – 2.1
			– 400

Table 10 shows some resistor values to adjust the oscillator frequency

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Functional description					L5988D
	Table 7.	FSW resistor examples
	R1 (kΩ)		fSW (kHz)	R2 (kΩ)	fSW (kHz)
		43	198	360	450
		47	215	180	499
		56	245	120	548
		62	261	91	594
		82	295	56	711
		110	322	43	801
		150	343	33	915
		220	361	27	1022

To improve the line transient performance, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 6 a).

Figure 6. Sawtooth: voltage feed forward

The slope of the sawtooth does not change if the oscillator frequency is increased by an external signal or adjusted by the external resistor (see Figure 7). As a consequence the gain of the PWM stage is a function of the switching frequency and its contribution must be taken in account when performing the calculations of the compensation network (see

Chapter 6.4.1 and Chapter 6.4.2).

Figure 7. Sawtooth: synchronization and frequency adjust

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