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■ LED driving
Figure 1.Application circuit
L5987
3 A step-down switching regulator
VFQFPN8 3x3 mm
Description
The L5987 is a step-down switching regulator with
3.5 A (minimum) current limited embedded power
MOSFET, so it is able to deliver up to 3 A current
to the load depending on the application
conditions (Section 5.7 and Section 5.8).
The input voltage can range from 2.9 V to 18 V,
while the output voltage can be set starting from
0.6 V to V
2.9 V, the device is suitable also for 3.3 V bus.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The QFN and the HSOP packages with exposed
pad allow reducing the R
and 40 °C/W respectively.
Master/slave synchronization. When it is left floating, a signal with a
phase shift of half a period respect to the power turn on is present at the
pin. When connected to an external signal at a frequency higher than the
2SYNCH
3INH
4COMPError amplifier output to be used for loop frequency compensation
5FB
6F
SW
7GNDGround
8VCCUnregulated DC input voltage
internal one, then the device is synchronized by the external signal, with
zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher
frequency works as master and the other one as slave; so the two
powers turn on have a phase shift of half a period.
A logical signal (active high) disable the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to FB pin.
The switching frequency can be increased connecting an external
resistor from FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 kHz.
4/41 Doc ID 14972 Rev 3
L5987Maximum ratings
2 Maximum ratings
Table 2.Absolute maximum ratings
SymbolParameterValueUnit
VccInput voltage20
OUTOutput DC voltage-0.3 to V
FSW, COMP, SYNCH Analog pin-0.3 to 4
CC
V
INHInhibit pin-0.3 to V
FBFeedback voltage-0.3 to 1.5
P
TOT
T
J
T
stg
3 Thermal data
Table 3.Thermal data
SymbolParameterValueUnit
R
thJA
1. Package mounted on demonstration board.
CC
Power dissipation at
< 60 °C
T
A
VFQFPN1.5.W
HSOP2
Junction temperature range-40 to 150°C
Storage temperature range-55 to 150°C
Maximum thermal resistance
junction-ambient
(1)
VFQFPN60
°C/W
HSOP40
Doc ID 14972 Rev 35/41
Electrical characteristicsL5987
4 Electrical characteristics
TJ = 25 °C, V
= 12 V, unless otherwise specified.
CC
Table 4.Electrical characteristics
Val ues
SymbolParameterTest condition
MinTypMax
V
CC
V
CCON
V
CCHYSVCC
R
DS(on)
I
LIM
Operating input voltage
range
Turn on VCC threshold
UVLO hysteresis
MOSFET on resistance
Maximum limiting current3.54.04.4A
Oscillator
V
F
FSW
SW
Switching frequency
FSW pin voltage1.262V
DDuty cycle0100%
F
ADJ
Adjustable switching
frequency
(1)
(1)
(1)
2.918
0.1750.3
140170
(1)
140220
225250275
(1)
= 33 kΩ1000kHz
R
FSW
220265
2.9
Unit
V
mΩ
kHz
Dynamic characteristics
V
FB
Feedback voltage2.9 V < V
CC
< 18 V
(1)
0.5930.60.607V
DC characteristics
I
Q
I
QST-BY
Quiescent current
Total stand-by quiescent
current
Duty Cycle = 0,
V
= 0.8 V
FB
2.4mA
2030μA
Inhibit
Device ON level0.6
INH threshold voltage
V
Device OFF level1.9
INH currentINH = 07.510μA
Soft-start
T
SS
Soft-start duration
FSW pin floating7.48.29.1
F
= 1 MHz,
R
SW
FSW
= 33 kΩ
2
ms
6/41 Doc ID 14972 Rev 3
L5987Electrical characteristics
Table 4.Electrical characteristics (continued)
Val ues
SymbolParameterTest condition
MinTypMax
Error amplifier
Unit
V
CH
V
CL
I
FB
I
O SOURCE
I
O SINK
G
High level output voltageV
Low level output voltageV
Bias source currentV
Source COMP pin
Sink COMP pin
Open loop voltage gain
V
Synchronization function
High input voltage23.3
Low input voltage1
Slave sink currentV
Master output amplitudeI
Output pulse widthSYNCH floating110
Input pulse width70
Protection
I
FBDISC
FB disconnection source
current
Thermal shutdown150
T
SHDN
Hysteresis30
< 0.6 V3
FB
> 0.6 V0.1
FB
= 0 V to 0.8 V1μA
FB
= 0.5 V,
V
FB
V
COMP
= 0.7 V,
V
FB
V
COMP
(2)
SYNCH
SOURCE
= 1 V
= 1 V
= 2.9 V0.70.9mA
= 4.5 mA2.0V
20mA
25mA
100dB
1μA
V
V
ns
°C
1. Specification referred to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.
Doc ID 14972 Rev 37/41
Functional descriptionL5987
5 Functional description
The L5987 is based on a “voltage mode”, constant frequency control. The output voltage
V
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
OUT
an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
●A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed forward are implemented.
●The soft-start circuitry to limit inrush current during the start up phase.
●The voltage mode error amplifier
●The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
●The High-side driver for embedded P-channel power MOSFET switch.
●The peak current limit sensing block, to handle over load and short circuit conditions.
●A voltage regulator and internal reference. It supplies internal circuitry and provides a
fixed internal reference.
●A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
●A thermal shutdown block, to prevent thermal run away.
Figure 3.Block diagram
8/41 Doc ID 14972 Rev 3
L5987Functional description
5.1 Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to FSW
pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as
shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM gain
expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with
higher oscillator frequency works as Master, so the Slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor [see L5988D data sheet].
Figure 4.Oscillator circuit block diagram
Clock
ClockClock
FSW
FSW
Clock
Clock
Generator
Generator
Synchronization
Synchronization
Ramp
Ramp
Generator
Generator
SYNCH
SYNCH
Sawtooth
Sawtooth
The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with a
resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting
of the frequency will change the sawtooth slope in order to get negligible the truncation of
sawtooth, due to the external synchronization.
Doc ID 14972 Rev 39/41
Functional descriptionL5987
Figure 5.Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6.Oscillator frequency versus FSW pin resistor
10/41 Doc ID 14972 Rev 3
L5987Functional description
5.2 Soft-start
The soft-start is essential to assure correct and safe start up of the step-down converter. It
avoids inrush current surge and makes the output voltage increases monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (V
) of the error
REF
amplifier. So the output voltage slew rate is:
Equation 1
R1
⎛⎞
⋅=
VREF
⎝⎠
1
------- -+
R2
where SR
SR
is the slew rate of the non-inverting input, while R1and R2 is the resistor
VREF
OUT
SR
divider to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64
steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft-start time and then the output voltage slew rate depend on the switching
frequency.
Figure 7.Soft-start scheme
Soft-start time results:
Equation 2
SS
TIME
For example with a switching frequency of 250 kHz the SS
Doc ID 14972 Rev 311/41
32 64⋅
-----------------=
Fsw
TIME
is 8 ms.
Functional descriptionL5987
5.3 Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
In continuos conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Chapter 6.4 for details about the
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
12/41 Doc ID 14972 Rev 3
L5987Functional description
5.4 Overcurrent protection
The L5987 implements the over-current protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
When the over-current is detected, two different behaviors are possible depending on the
operating condition.
●Output voltage in regulation. When the over current is sensed, the power MOSFET is
switched off and the internal reference (V
error amplifier, is set to zero and kept in this condition for a soft-start time (T
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
●Soft-start phase. If the over current limit is reached the power MOSFET is turned off
implementing the pulse by pulse over current protection. During the soft-start phase,
under over current condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If at the end of the “masking time” the
current is higher than the over current threshold, the power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the “masking time” the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the “masking time” the current is lower than the over current threshold, the number of
skipped cycles is decreased of one unit. At the end of soft-start phase the output
voltage is in regulation and if the over current persists the behavior explained above
takes place. (see Figure 8.b)
), that biases the non-inverting input of the
REF
SS
, 2048
So the over current protection can be summarized as an “hiccup” intervention when the
output is in regulation and a constant current during the soft-start phase. If the output is
shorted to ground when the output voltage is on regulation, the over current is triggered and
the device starts cycling with a period of 2048 clock cycles between “hiccup” (power
MOSFET off and no current to the load) and “constant current” with very short on-time and
with reduced switching frequency (up to one eighth of normal switching frequency). See for
short circuit behavior.
Doc ID 14972 Rev 313/41
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