Features
■ 2.5 A DC output current
■ 2.9 V to 18 V input voltage
■ Output voltage adjustable from 0.6 V
■ 250 kHz switching frequency, programmable
up to 1 MHz
■ Internal soft-start and inhibit
■ Low dropout operation: 100 % duty cycle
■ Voltage feed-forward
■ Zero load current operation
■ Overcurrent and thermal protection
■ VFQFPN3x3-8L and HSOP8 package
Applications
■ Consumer: STB, DVD, DVD recorder, car
audio, LCD TV and monitors
■ Industrial: chargers, PLD, PLA, FPGA
■ Networking: XDSL, modems, DC-DC modules
■ Computer: optical storage, hard disk drive,
printers, audio/graphic cards
■ LED driving
L5986
2.5 A step-down switching regulator
VFQFPN8 3x3 mm
Description
The L5986 is a step-down switching regulator with
a 3.0 A (min.) current limited embedded power
MOSFET, so it is able to deliver up to 2.5 A
current to the load depending on the application
conditions.
The input voltage can range from 2.9 V to 18 V,
while the output voltage can be set starting from
0.6 V to V
2.9 V, the device is suitable also for 3.3 V bus.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The QFN and the HSOP packages with exposed
pad allow reducing the R
and 40 °C/W respectively.
. Having a minimum input voltage of
IN
HSOP8 exposed pad
down to 60 °C/W
thJA
Figure 1. Application circuit
November 2010 Doc ID 14971 Rev 4 1/44
www.st.com
44
Contents L5986
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/44 Doc ID 14971 Rev 4
L5986 Contents
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Doc ID 14971 Rev 4 3/44
Pin settings L5986
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
OUT
1.2 Pin description
OUT
SYNCH
SYNCH
INH
INH
COMP
COMP
V
V
CC
CC
GND
GND
FSW
FSW
FB
FB
Table 1. Pin description
N. Type Description
1 OUT Regulator output
Master/slave synchronization. When it is left floating, a signal with a
phase shift of half a period with respect to the power turn on is present at
the pin. When connected to an external signal at a frequency higher than
2 SYNCH
3INH
4 COMP Error amplifier output to be used for loop frequency compensation
5FB
6F
SW
7 GND Ground
8VCCUnregulated DC input voltage
the internal one, then the device is synchronized by the external signal,
with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with the
higher frequency works as master and the other as slave; so the two turn
on powers have a phase shift of half a period.
A logical signal (active high) disables the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to the FB pin.
The switching frequency can be increased connecting an external
resistor from the FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 kHz.
4/44 Doc ID 14971 Rev 4
L5986 Maximum ratings
2 Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
Vcc Input voltage 20
OUT Output DC voltage -0.3 to V
FSW, COMP, SYNCH Analog pin -0.3 to 4
CC
V
INH Inhibit pin -0.3 to V
FB Feedback voltage -0.3 to 1.5
P
TOT
T
J
T
stg
3 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
thJA
1. Package mounted on demonstration board.
CC
Power dissipation at
< 60 °C
T
A
VFQFPN 1.5. W
HSOP 2
Junction temperature range -40 to 150 °C
Storage temperature range -55 to 150 °C
Maximum thermal resistance
junction-ambient
(1)
VFQFPN 60
°C/W
HSOP 40
Doc ID 14971 Rev 4 5/44
Electrical characteristics L5986
4 Electrical characteristics
TJ = 25 °C, V
= 12 V, unless otherwise specified.
CC
Table 4. Electrical characteristics
Val ues
Symbol Parameter Test condition
Min Typ Max
V
CC
V
CCON
V
CCHYSVCC
R
DS(on)
I
LIM
Operating input voltage
range
Turn on VCC threshold
UVLO hysteresis
MOSFET on resistance
Maximum limiting current 3.0 3.5 3.9 A
Oscillator
V
F
FSW
SW
Switching frequency
FSW pin voltage 1.262 V
D Duty cycle 0 100 %
(1)
(1)
(1)
(1)
(1)
2.9 18
0.175 0.3
140 170
140 220
225 250 275
220 275
2.9
Unit
V
mΩ
kHz
F
ADJ
Adjustable switching
frequency
= 33 kΩ 1000 kHz
R
FSW
Dynamic characteristics
V
FB
Feedback voltage 2.9 V < V
CC
< 18 V
(1)
0.593 0.6 0.607 V
DC characteristics
I
Q
I
QST-BY
Quiescent current
Total standby quiescent
current
Duty cycle = 0,
V
= 0.8 V
FB
2.4 mA
20 30 μA
Inhibit
Device ON level 0.6
INH threshold voltage
V
Device OFF level 1.9
INH current INH = 0 7.5 10 μA
Soft-start
FSW pin floating 7.4 8.2 9.1
T
SS
Soft-start duration
F
R
SW
FSW
= 1 MHz,
= 33 kΩ
2
ms
6/44 Doc ID 14971 Rev 4
L5986 Electrical characteristics
Table 4. Electrical characteristics (continued)
Val ues
Symbol Parameter Test condition
Min Typ Max
Error amplifier
Unit
V
CH
V
CL
I
FB
I
O SOURCE
I
O SINK
G
High level output voltage V
Low level output voltage V
Bias source current V
Source COMP pin
Sink COMP pin
Open loop voltage gain
V
Synchronization function
High input voltage 2 3.3
Low input voltage 1
Slave sink current V
Master output amplitude I
Output pulse width SYNCH floating 110
Input pulse width 70
Protection
I
FBDISC
FB disconnection source
current
Thermal shutdown 150
T
SHDN
Hysteresis 30
< 0.6 V 3
FB
> 0.6 V 0.1
FB
= 0 V to 0.8 V 1 μA
FB
= 0.5 V,
V
FB
V
COMP
= 0.7 V,
V
FB
V
COMP
(2)
SYNCH
SOURCE
= 1 V
= 1 V
= 2.9 V 0.7 0.9 mA
= 4.5 mA 2.0 V
20 mA
25 mA
100 dB
1 μA
V
V
ns
°C
1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.
Doc ID 14971 Rev 4 7/44
Functional description L5986
5 Functional description
The L5986 is based on a “voltage mode”, constant frequency control. The output voltage
V
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
OUT
an error signal that, compared to a fixed frequency sawtooth, controls the ON and OFF time
of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed forward are implemented.
● The soft-start circuitry to limit inrush current during the start-up phase
● The voltage mode error amplifier
● The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch
● The high-side driver for embedded p-channel power MOSFET switch
● The peak current limit sensing block, to handle over load and short-circuit conditions
● A voltage regulator and internal reference. It supplies internal circuitry and provides a
fixed internal reference.
● A voltage monitor circuitry (UVLO) that checks the input and internal voltages
● A thermal shutdown block, to prevent thermal run-away
Figure 3. Block diagram
8/44 Doc ID 14971 Rev 4
L5986 Functional description
5.1 Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to the
FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased
as shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM gain
expression).
The synchronization signal is generated on the SYNCH pin. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pins together. When SYNCH pins are connected, the device with a
higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D; 4 A continuous (more than 5 A pulsed) step-
down switching regulator with synchronous rectification, datasheet).
Figure 4. Oscillator circuit block diagram
Clock
ClockClock
FSW
FSW
Clock
Clock
Generator
Generator
Synchronization
Synchronization
Ramp
Ramp
Generator
Generator
SYNCH
SYNCH
Sawtooth
Sawtooth
The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This change has to be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free running frequency should be set (with a
resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render the truncation of
sawtooth negligible, due to the external synchronization.
Doc ID 14971 Rev 4 9/44
Functional description L5986
Figure 5. Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6. Oscillator frequency vs. FSW pin resistor
10/44 Doc ID 14971 Rev 4
L5986 Functional description
5.2 Soft-start
The soft-start is essential to assure correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (V
) of the error
REF
amplifier. So the output voltage slew rate is:
Equation 1
R1
⎛⎞
⋅=
VREF
⎝⎠
1
------- -+
R2
where SR
SR
is the slew rate of the non-inverting input while R1 and R2 is the resistor
VREF
OUT
SR
divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64
steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So
the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
SS
TIME
For example, with a switching frequency of 250 kHz the SS
Doc ID 14971 Rev 4 11/44
32 64⋅
-----------------=
Fsw
TIME
is 8 ms.
Functional description L5986
5.3 Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Parameter Value
Low frequency gain 100 dB
GBWP 4.5 MHz
Slew rate 7 V/μs
Output voltage swing 0 to 3.3 V
Maximum source/sink current 25 mA/40 mA
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Section 6.4 for details of the compensation
network selection).
However, the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
12/44 Doc ID 14971 Rev 4
L5986 Functional description
5.4 Overcurrent protection
The L5986 implements the overcurrent protection sensing current flowing through the power
MOSFET. Due to the noise created by the switching activity of the power MOSFET, the
current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the
operating condition.
1. Output voltage in regulation. When the overcurrent is sensed, the power MOSFET is
switched off and the internal reference (V
error amplifier, is set to zero and kept in this condition for a soft-start time (T
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
2. Soft-start phase. If the overcurrent limit is reached, the power MOSFET is turned off
implementing the pulse by pulse overcurrent protection. During the soft-start phase,
under the overcurrent condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If, at the end of the “masking time”, the
current is higher than the overcurrent threshold, the power MOSFET is turned off and it
skips one pulse. If, at the next switching on at the end of the “masking time”, the current
is still higher than the threshold, the device skips two pulses. This mechanism is
repeated and the device can skip up to seven pulses. While, if at the end of the
“masking time” the current is lower than the overcurrent threshold, the number of
skipped cycles is decreased by one unit. At the end of the soft-start phase the output
voltage is in regulation and if the overcurrent persists, the behavior explained above
takes place. (see Figure 8.b)
), that biases the non-inverting input of the
REF
SS
, 2048
So the overcurrent protection can be summarized as a “hiccup” intervention when the output
is in regulation and a constant current during the soft-start phase.
If the output is shorted to ground when the output voltage is in regulation, the overcurrent is
triggered and the device starts cycling with a period of 2048 clock cycles between “hiccup”
(power MOSFET off and no current to the load) and “constant current” with very short ON
time and with reduced switching frequency (up to one eighth of normal switching frequency).
See Figure 31. for short-circuit behavior.
Doc ID 14971 Rev 4 13/44
Functional description L5986
Figure 8. Overcurrent protection strategy
5.5 Inhibit function
The inhibit feature allows the device to be put into standby mode. With the INH pin higher
than 1.9 V, the device is disabled and the power consumption is reduced to less than 30 μA.
With the INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an
internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also V
CC
5.6 Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
14/44 Doc ID 14971 Rev 4
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, therefore ensuring an accurate and fast temperature detection.
compatible.
L5986 Application information
6 Application information
6.1 Input capacitor selection
The capacitor connected to the input must be able to support the maximum input operating
voltage and the maximum RMS input current required by the device. The input capacitor is
subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the
overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
2
I
RMSIO
D
⋅
2D
-------------- -–
η
2
D
------ -+⋅=
2
η
where I
Considering η = 1, this function has a maximum at D = 0.5 and it is equal to I
is the maximum DC output current, D is the duty cycle, η is the efficiency.
o
/2.
o
In a specific application the range of possible duty cycles must be considered in order to find
out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 4
V
+
OUTVF
D
MAX
------------------------------------ -=
V
–
INMINVSW
and
Equation 5
V
+
OUTVF
--------------------------------------=
V
–
INMAXVSW
where V
D
MIN
is the forward voltage on the freewheeling diode and VSW is voltage drop across
F
the internal PDMOS.
In Ta bl e 6 some multi layer ceramic capacitors suitable for this device are reported.
Table 6. Input capacitors
Manufacturer Series Cap value (μF) Rated voltage (V)
GRM31 10 25
MURATA
GRM55 10 25
TDK C3225 10 25
Doc ID 14971 Rev 4 15/44
Application information L5986
6.2 Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value, in order to have the expected current ripple, must be selected.
The rule to fix the current ripple value is to have a ripple at 20 %-40 % of the output current.
In the continuous current mode (CCM), the inductance value can be calculated by the
following equation:
Equation 6
VINV
ΔI
L
–
OUT
----------------------------- -
L
T
⋅
ON
V
+
OUTVF
--------------------------- -
L
T
⋅==
OFF
where T
time of the external diode (in CCM, F
fixed V
section to calculate minimum duty). So fixing ΔI
is the conduction time of the internal high side switch and T
ON
, is obtained at maximum T
OUT
= 1/(TON + T
SW
that is at minimum duty cycle (see previous
OFF
= 20 % to 30 % of the maximum output
L
)). The maximum current ripple, at
OFF
is the conduction
OFF
current, the minimum inductance value can be calculated:
Equation 7
+
1D
–
---------------------- -
⋅=
F
).
OFF
SW
MIN
= 250 kHz, the minimum
SW
where F
For example, for V
is the switching frequency, 1/(TON + T
SW
= 3.3 V, V
OUT
inductance value to have ΔI
V
OUTVF
L
IN
= 30 % of IO is about 12 μH.
L
--------------------------- -
MIN
ΔI
MAX
= 12 V, IO = 2.5 A and F
The peak current through the inductor is given by:
Equation 8
ΔI
I
LPK,
L
--------+=
I
O
2
So if the inductor value decreases, the peak current (which must be lower than the current
limit of the device) increases. The higher the inductor value, the higher the average output
current that can be delivered, without reaching the current limit.
In Ta bl e 7 some inductor part numbers are listed.
Table 7. Inductors
Manufacturer Series Inductor value (μH) Saturation current (A)
Coilcraft
Wurth
SUMIDA
16/44 Doc ID 14971 Rev 4
MSS1038 3.8 to 10 3.9 to 6.5
MSS1048 12 to 22 3.84 to 5.34
PD Type L 8.2 to 15 3.75 to 6.25
PD Type M 2.2 to 4.7 4 to 6
CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2
CDR10D48MN 6.6 to 12 4.1 to 5.7
L5986 Application information
6.3 Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge and discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 9
ΔI
MAX
ΔV
OUT
ESR ΔI
⋅
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is
illustrated.
MAX
------------------------------------ -+=
8C
⋅⋅
OUTfSW
For example with V
order to have a ΔV
OUT
OUT
= 3.3 V, V
= 0.01·V
= 12 V, ΔIL = 0.75 A (resulting from the inductor value), in
IN
, if the multi layer ceramic capacitor is adopted, 11 µF is
OUT
needed and the ESR effect on the output voltage ripple can be neglected. In case of not
negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value.
So in case of 330 µF with ESR = 30 mΩ, the resistive component of the drop dominates and
the voltage ripple is 22.5 mV.
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth, the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
must be chosen in order to sustain the load transient.
In Ta bl e 8 some capacitor series are listed.
Table 8. Output capacitors
Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ)
MURATA
PANASONIC
GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
Doc ID 14971 Rev 4 17/44
Application information L5986
6.4 Compensation network
The compensation network has to assure stability and good dynamic performance. The loop
of the L5986 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So, by selecting the compensation network the
E/A is considered as ideal, that is, its bandwidth is much larger than that of the system.
The transfer functions of the PWM modulator and the output LC filter are studied (see Figure
10.). The transfer function of the PWM modulator, from the error amplifier output (COMP
pin) to the OUT pin, results:
Equation 10
V
G
PW0
IN
-------- -=
V
s
where V
is the sawtooth amplitude. As seen in Section 5.1, the voltage feed forward
S
generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 11
V
KVIN⋅=
S
In this way the PWM modulator gain results constant and equal to:
Equation 12
V
1
IN
-------- -
G
PW0
V
s
--- - 9===
K
The synchronization of the device with an external clock provided trough the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 9. The error amplifier, the PWM modulation and the LC output filter
V
V
CC
CC
V
V
S
S
V
V
REF
FB
FB
REF
E/A
E/A
COMP
COMP
PWM
PWM
OUT
OUT
L
L
G
G
PW0
PW0
The transfer function on the LC filter is given by:
18/44 Doc ID 14971 Rev 4
ESR
ESR
G
G
LC
LC
C
C
OUT
OUT
L5986 Application information
Equation 13
GLCs()
1
------------------------------------------------------------------------ -=
1
----------------------------
++
2π Qf⋅LC⋅
s
s
------------------------- -+
2π f
⋅
zESR
⎛⎞
-------------------
⎝⎠
2π f
2
s
⋅
LC
where:
Equation 14
f
----------------------------------------------------------------------- -= f
LC
2π LC
1
⋅ 1
OUT
ESR
-------------- -+⋅⋅
R
OUT
zESR
------------------------------------------- -=,
2π ESR C
1
⋅⋅
OUT
Equation 15
R
LC
Q
LC
OUT
------------------------------------------------------------------------------------------
OUTROUT
OUTROUT
ESR+()⋅⋅ ⋅
ESR⋅⋅+
R
OUT
V
--------------=,=
I
OUT
OUT
As seen in Section 5.3, two different kinds of network can compensate the loop. In the two
following paragraphs the guidelines to select the type II and type III compensation network
are illustrated.
6.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, therefore increasing phase margin; then to place one pole in the
origin to minimize the DC error on regulated output voltage; finally to place other poles far
from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR
(<1 mΩ), with very high frequency zero, so a type III network is adopted to compensate the
loop.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(f
, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:
Z1
Equation 16
f
Z1
------------------------------------------------= f
2π C
1
+()⋅⋅
3R1R3
Z2
----------------------------- -=,
⋅⋅
2π R
1
4C4
Doc ID 14971 Rev 4 19/44
Application information L5986
Equation 17
1
f
0= f
P0
----------------------------- -= f
P1
⋅⋅
2π R
3C3
P2
------------------------------------------- -=,,
2π R
1
C4C5⋅
--------------------
⋅⋅
4
C
+
4C5
Figure 10. Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G
LOOP
(f) = G
· GLC(f) · G
PW0
TYPEIII
(f)) is given.
PW0
· GLC(f))
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeros and for calculating the component
values can be summarized as follows:
1. Choose a value for R
2. Choose a gain (R
, usually between 1 k and 5 k.
1
) in order to have the required bandwidth (BW), that means:
4/R1
20/44 Doc ID 14971 Rev 4
L5986 Application information
Equation 18
BW K⋅
------------------
R
4
⋅=
R
f
LC
1
where K is the feed forward constant and 1/K is equal to 9.
3. Calculate C
by placing the zero at 50 % of the output filter double pole frequency (fLC):
4
Equation 19
1
---------------------------=
C
4
⋅⋅
π R
4fLC
4. Calculate C
by placing the second pole at four times the system bandwidth (BW):
5
Equation 20
C
C
------------------------------------------------------------- -=
5
2π R4C44BW⋅ 1–⋅⋅⋅
4
5. Set the first pole also at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 21
R
R
3
1
-------------------------- -= C
4BW⋅
----------------- 1–
f
LC
3
1
---------------------------------------- -=,
2π R34BW⋅⋅⋅
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (F
For example, with V
/3.5), but lower than 100 kHz if the FSW is set higher than 500 kHz.
SW
OUT
= 3.3 V, V
= 12 V, IO = 2.5 A, L=12μH, C
IN
OUT
= 22 μF, ESR < 1 mΩ,
the type III compensation network is:
4.99k Ω= R21.1kΩ= R3180Ω= R43.9kΩ= C33.3nF= C410nF= C5150pF=,,,,,,
R
1
In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about
71 kHz and the phase margin is 48°.
Doc ID 14971 Rev 4 21/44
Application information L5986
Figure 12. Open loop gain Bode diagram with ceramic output capacitor
22/44 Doc ID 14971 Rev 4
L5986 Application information
6.4.2 Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π
∗
ESR
∗
C
>1/BW), this zero
OUT
helps stabilize the loop. electrolytic capacitors show not negligible ESR (> 30 mΩ), so with
this kind of output capacitor the type II network combined with the zero of the ESR allows
the loop to be stabilized.
In Figure 13 the type II network is shown.
Figure 13. Type II compensation network
The singularities of the network are:
f
Z1
⋅⋅
2π R
4C4
P0
0= f
P1
------------------------------------------- -=,,
2π R
1
----------------------------- -= f
In Figure 14 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G
LOOP
(f) = G
· GLC(f) · G
PW0
TYPEII
1
C4C5⋅
--------------------
⋅⋅
4
+
C
4C5
(f)) is given.
PW0
· GLC(f))
Doc ID 14971 Rev 4 23/44
Application information L5986
Figure 14. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeros and for calculating the component
values can be summarized as follows:
1. Choose a value for R
, usually between 1 k and 5 k, in order to have values of C4 and
1
C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
) in order to have the required bandwidth (BW), that means:
4/R1
Equation 22
where f
is the ESR zero:
ESR
R
4
2
f
ESR
⎛⎞
----------- -
⎝⎠
⋅⋅⋅=
f
LC
BW
----------- -
f
ESR
V
-------- -
V
IN
S
R
1
Equation 23
f
ESR
------------------------------------------- -=
2π ESR C
1
⋅⋅
OUT
and Vs is the sawtooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.
3. Calculate C
by placing the zero one decade below the output filter double pole:
4
Equation 24
------------------------------ -=
⋅⋅
2π R
10
4fLC
C
4
4. Then calculate C
in order to place the second pole at four times the system bandwidth
3
(BW):
24/44 Doc ID 14971 Rev 4
L5986 Application information
Equation 25
C
------------------------------------------------------------- -=
C
5
2π R4C44BW⋅ 1–⋅⋅⋅
4
For example, with V
OUT
= 3.3 V, V
= 12 V, IO = 2.5 A, L = 12 μH, C
IN
= 330 μF, ESR = 35
OUT
mΩ, the type II compensation network is:
R
1.5kΩ= R2330Ω= R410k Ω= C447nF= C582pF=,,,,
1
In Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about
32 kHz and the phase margin is 45°.
Doc ID 14971 Rev 4 25/44
Application information L5986
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
26/44 Doc ID 14971 Rev 4
L5986 Application information
6.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a) conduction losses due to the not negligible R
equal to:
Equation 26
of the power switch; these are
DS(on)
P
ONRDSONIOUT
where D is the duty cycle of the application and the maximum R
Note that the duty cycle is theoretically given by the ratio between V
()2D⋅⋅=
is 220 mΩ.
DS(on)
and VIN, but actually
OUT
it is quite higher to compensate the losses of the regulator. So the conduction losses
increase compared with the ideal case.
b) switching losses due to power MOSFET turn on and off; these can be calculated
as:
Equation 27
T
+()
RISETFALL
where T
RISE
P
SWVINIOUT
and T
FAL L
------------------------------------------ -
2
are the overlap times of the voltage across the power switch (VDS)
Fsw⋅⋅ ⋅ V
⋅⋅⋅==
INIOUTTSWFSW
and the current flowing into it during turn on and turn off phases, as shown in Figure 16. T
is the equivalent switching time.
For this device the typical value for the equivalent switching time is 50 ns.
c) Quiescent current losses, calculated as:
Equation 28
SW
where I
is the quiescent current (IQ = 2.4 mA).
Q
The junction temperature T
P
QVINIQ
can be calculated as:
J
⋅=
Equation 29
T
JTA
where T
Rth
is the ambient temperature and P
A
is the equivalent thermal resistance junction to ambient of the device; it can be
JA
RthJAP
⋅+=
TOT
is the sum of the power losses just seen.
TOT
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
Doc ID 14971 Rev 4 27/44
Application information L5986
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The Rth
, measured on the demonstration board described in the following
JA
paragraph, is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP
package.
Figure 16. Switching losses
6.6 Layout considerations
The PC board layout of the switching DC/DC regulator is very important to minimize the
noise injected in high impedance nodes and interferences generated by the high switching
current loops.
In a step-down converter the input loop (including the input capacitor, the power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as
short as possible.
To filter the high frequency noise, a small capacitor (220 nF) can be added as close as
possible to the input voltage pin of the device.
The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interferences can be minimized placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick up noise the resistor divider has to
be placed very close to the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
In Figure 17 a layout example is shown.
28/44 Doc ID 14971 Rev 4
L5986 Application information
Figure 17. Layout example
Doc ID 14971 Rev 4 29/44
Application information L5986
6.7 Application circuit
In Figure 18 the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit
Vin=2.9V - 18V
C1
22u
25V
C6
220n
25V
VCC
8
INH
32
L5986/A
GND
7
4
6
1
5
OUT
SYNCH
FB
L1 5.2uH MSS1038
D1
STPS2L25
Vout=1.8V
COMPFSW
R5
150k
R4
2K
C5 330pF
C4 10hF
R2
2.49k
R1 4.99K
R3
330
C3 2.2nF
Table 9. Component list
Reference Part number Description Manufacturer
C1 GRM32ER61E226KE15 22 μF, 25 V MURATA
C2 GRM32ER61E226KE15 22 μF, 25 V MURATA
C3 2.2 nF, 50 V
C4 10 nF, 50 V
C5 330 pF, 50 V
C6 220 nF, 25 V
C2
22u
25V
R1 4.99 kΩ, 1 %, 0.1W 0603
R2 2.49 kΩ, 1 %, 0.1W 0603
R3 330 Ω, 1 %, 0.1W 0603
R4 2 kΩ, 1 %, 0.1W 0603
R5 100 k.
D1 STPS2L25V 2 A, 25 V STMicroelectronics
L1 MSS1038-522NL
30/44 Doc ID 14971 Rev 4
5.2 μH, 30 %, 5.28 A,
MAX
= 22 mΩ
DCR
Coilcraft
L5986 Application information
Figure 19. PCB layout: L5986 and L5986A (component side)
Figure 20. PCB layout: L5986 and L5986A (bottom side)
Figure 21. PCB layout: L5986 and L5986A (front side)
Doc ID 14971 Rev 4 31/44
Application information L5986
y
y
[
]
y
Figure 22. Junction temperature vs.
output current
Figure 23. Junction temperature vs.
output current
Figure 24. Junction temperature vs.
output current
Figure 25. Efficiency vs. output current
92
90
88
86
[% ]
84
82
Efficienc
80
78
VIN=12V
76
0.30.81.31.82.3
V
V
V
=5V
O
=3.3V
O
=2.5V
O
Io [A]
Figure 26. Efficiency vs. output current Figure 27. Efficiency vs. output current
95
90
%
85
80
E ffic ien c
75
=5V
V
IN
70
0.30.81.31.82.3
V
=3.3V
O
V
=2.5V
O
VO=1.8V
Io [A]
95
90
85
[% ]
80
75
Efficienc
70
V
=3.3V
IN
65
0.30.81.31.82.3
V
=2.5V
O
=1.8V
V
O
VO=1.2V
Io [A]
32/44 Doc ID 14971 Rev 4
L5986 Application information
Figure 28. Load regulation Figure 29. Line regulation
1.2
1
0.8
[%]
FB
0.6
/V
FB
V
Δ
0.4
0.2
VCC=12V
VCC=5V
1
IO=1A
0.8
0.6
[%]
FB
/V
FB
0.4
V
Δ
0.2
IO=2A
0
00.5 11.5 22.5
IO [A]
Figure 30. Load transient: from 0.4 A to
V
V
OUT
OUT
200mV/div
200mV/div
AC coupled
AC coupled
1A/div
1A/div
I
I
L
L
Figure 32. Short-circuit behavior
OUT 10V/div
OUT 10V/div
OUT 10V/div
OUT 10V/div
2.5 A
Time base 100us/div
Time base 100us/div
C
C
=22uF
=22uF
OUT
OUT
L=5.2uH
L=5.2uH
=520k
=520k
F
F
SW
SW
0
2 4 6 8 10 12 14 16 18
V
[V]
CC
Figure 31. Soft-start
I
I
IL1A/div
1A/div
IL1A/div
1A/div
L
L
Time base 1ms/div
Time base 1ms/div
Time base 1ms/div
Time base 1ms/div
0.5V/divV
0.5V/divV
0.5V/divV
V
V
OUT
OUT
OUT
OUTVOUT
OUT
SHORTED OUTPUT
V
V
1V/divV
1V/divV
1V/divV
OUT
OUT
OUT
OUTVOUT
OUT
SHORTED OUTPUTSHORTED OUTPUT
1A/divIL1A/div
1A/divIL1A/divIL1A/divIL1A/div
I
I
L
L
Time base 5ms/div
Time base 5ms/divTime base 5ms/div
Doc ID 14971 Rev 4 33/44
Application ideas L5986
7 Application ideas
7.1 Positive buck-boost
The L5986 can implement the step-up/down converter with a positive output voltage.
Figure 33 shows the schematic: one power MOSFET and one Schottky diode are added to
the standard buck topology to provide 12 V output voltage with input voltage from 2.9 V to 18
V.
Figure 33. Positive buck-boost regulator
The relationship between input and output voltage is:
Equation 30
D
-------------
V
OUTVIN
⋅=
1D–
so the duty cycle is:
Equation 31
V
D
OUT
----------------------------- -=
V
+
OUTVIN
The output voltage is not limited by the maximum operating voltage of the device (18 V),
because the output voltage is sensed only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 33, if V
is
IN
higher than 16 V, the gate must be protected through a Zener diode and resistor).
The current flowing through the internal power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (2.5 A), the maximum
output current for the buck-boost topology can be calculated from the following equation.
34/44 Doc ID 14971 Rev 4
L5986 Application ideas
Equation 32
I
OUT
I
SW
-------------
1D–
2.5 A<=
where I
is the average current in the embedded power MOSFET in the ON time.
SW
To chose the right value of the inductor and to manage transient output current, which for a
short time can exceed the maximum output current calculated by Equation 32, the peak
current in the power MOSFET must also be calculated. The peak current, shown in Equation
33, must be lower than the minimum current limit (3.0 A):
Equation 33
I
SW,PK
r
OUT
-------------
1D–
V
OUT
------------------------------------
I
LF
⋅⋅
OUT
1
⋅=
SW
r
-- -+ 3.0A<⋅=
2
2
1D–()
I
where r is defined as the ratio between the inductor current ripple and the inductor DC
current.
Therefore, in the buck-boost topology the maximum output current depends on the
application conditions (firstly input and output voltage, secondly switching frequency and
inductor value).
In Figure 34 the maximum output current for the above configuration is depicted varying the
input voltage from 2.9 V to 18 V.
The dashed line considers a more accurate estimation of the duty cycles given by Equation
34, where power losses across diodes, external power MOSFET, and internal power
MOSFET are taken into account.
Doc ID 14971 Rev 4 35/44
Application ideas L5986
Figure 34. Maximum output current according to max DC switch current (2.5 A):
V
= 12 V
O
Equation 34
where V
is the voltage drop across the diodes, and VSW and V
D
external power MOSFET.
7.2 Inverting buck-boost
The L5986 can implement the step-up/down converter with a negative output voltage.
Figure 33 shows the schematic to regulate -5 V: no further external components are added
to the standard buck topology.
The relationship between input and output voltage is:
Equation 35
so the duty cycle is:
Equation 36
V
V
OUT
------------------------------------------------------------------------------------------- -=
D
V
INVSWVSWEVOUT
D
OUT
VIN–
V
OUT
----------------------------- -=
V
OUTVIN
–
2VD⋅+
++––
⋅=
D
-------------
1D–
2V⋅
D
across the internal and
SWE
36/44 Doc ID 14971 Rev 4
L5986 Application ideas
As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.5 A), the maximum output current can be calculated from Equation 32,
where the duty cycle is given by Equation 36.
Figure 35. Inverting buck-boost regulator
The GND pin of the device is connected to the output voltage so, given the output voltage,
the input voltage range is limited by the maximum voltage the device can withstand across
V
and GND (18 V). Therefore, if the output is -5 V, the input voltage can range from 2.9 V
CC
to 13 V.
As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 36. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 37, where power losses across diodes and the internal
power MOSFET are taken into account.
Equation 37
V
–
---------------------------------------------------------------- -=
D
OUTVD
V–
INVSWVOUTVD
–+–
Doc ID 14971 Rev 4 37/44
Application ideas L5986
Figure 36. Maximum output current according to max DC switch current (2.5 A):
V
= -5 V
O
38/44 Doc ID 14971 Rev 4
L5986 Package mechanical data
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST registered trademark.
Doc ID 14971 Rev 4 39/44
Package mechanical data L5986
Table 10. VFQFPN8 (3 x 3 x 1.08 mm) mechanical data
mm inch
Dim.
Min Typ Max Min Typ Max
A 0.80 0.90 1.00 0.0315 0.0354 0.0394
A1 0.02 0.05 0.0008 0.0020
A2 0.70 0.0276
A3 0.20 0.0079
b 0.18 0.23 0.30 0.0071 0.0091 0.0118
D 2.95 3.00 3.05 0.1161 0.1181 0.1200
D2 2.23 2.38 2.48 0.0878 0.0937 0.0976
E 2.95 3.00 3.05 0.1161 0.1181 0.1200
E2 1.65 1.70 1.75 0.0649 0.0669 0.0689
e 0.50 0.0197
L 0.35 0.40 0.45 0.0137 0.0157 0.0177
ddd 0.08 0.0031
Figure 37. Package dimensions
40/44 Doc ID 14971 Rev 4
L5986 Package mechanical data
Table 11. HSOP8 mechanical data
mm inch
Dim
Min Typ Max Min Typ Max
A 1.70 0.0669
A1 0.00 0.15 0.00 0.0059
A2 1.25 0.0492
b 0.31 0.51 0.0122 0.0201
c 0.17 0.25 0.0067 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
E 5.80 6.00 6.20 0.2283 0.2441
E1 3.80 3.90 4.00 0.1496 0.1575
e1.27
h 0.25 0.50 0.0098 0.0197
L 0.40 1.27 0.0157 0.0500
k0 8 0.3150
ccc 0.10 0.0039
Figure 38. Package dimensions
Doc ID 14971 Rev 4 41/44
Order codes L5986
9 Order codes
Table 12. Order codes
Order codes Package Packaging
L5986 VFQFPN8
L5986A HSOP8
L5986TR VFQFPN8
L5986ATR HSOP8
Tube
Tape and reel
42/44 Doc ID 14971 Rev 4
L5986 Revision history
10 Revision history
Table 13. Document revision history
Date Revision Changes
28-Aug-2008 1 Initial release.
29-Jan-2009 2 Updated: Equation 18
17-Jun-2009 3 Updated Table 4 on page 5 and Figure 6 on page 10
30-Nov-2010 4
Added: Section 6 on page 15
Updated: Figure 19, Figure 20 and Figure 21 on page 31
Doc ID 14971 Rev 4 43/44
L5986
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www.st.com
44/44 Doc ID 14971 Rev 4
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