L5985
2 A step-down switching regulator
Features
■2 A DC output current
■2.9 V to 18 V input voltage
■Output voltage adjustable from 0.6 V
■250 kHz switching frequency, programmable up to 1 MHz
■Internal soft-start and Inhibit
■Low dropout operation: 100% duty cycle
■Voltage feed-forward
■Zero load current operation
■Over current and thermal protection
■VFQFPN8 3 mm x 3 mm package
Applications
■Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors
■Industrial: chargers, PLD, PLA, FPGA
■Networking: XDSL, modems, DC-DC modules
■Computer: optical storage, hard disk drive, printers, audio/graphic cards
■LED driving
VFQFPN8 3 mm x 3 mm
Description
The L5985 is a step-down switching regulator with 2.5 A (min) current limited embedded power MOSFET, so it is able to deliver up to 2 A DC current to the load depending on the application condition.
The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from 0.6 V to VIN. Having a minimum input voltage of 2.9 V, the device is suitable for 3.3 V bus.
Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz.
The VFQFPN8 package with exposed pad allows reducing the RthJA down to approximately
60 °C/W.
June 2009 |
Doc ID 13006 Rev 5 |
1/37 |
www.st.com
Contents |
L5985 |
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Contents
1 |
Pin settings |
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1.1 |
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
3 |
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1.2 |
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
3 |
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2 |
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.1 |
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.2 |
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.1 |
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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4.2 |
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
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4.3 |
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.4 |
Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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4.5 |
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
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4.6 |
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5 |
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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5.1 |
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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5.2 |
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3 |
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.4 |
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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5.4.1 |
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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5.4.2 |
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.5 |
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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5.6 |
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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5.7 |
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Order codes . |
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8 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2/37 |
Doc ID 13006 Rev 5 |
L5985 |
Pin settings |
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OUT |
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VCC |
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SYNCH |
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GND |
INH |
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FSW |
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COMP |
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FB |
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1.2Pin description
Table 1. |
Pin description |
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N° |
Type |
Description |
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1 |
OUT |
Regulator output |
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Master/slave synchronization. When it is left floating, a signal with a |
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phase shift of half a period respect to the power turn on is present at the |
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pin. When connected to an external signal at a frequency higher than the |
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2 |
SYNCH |
internal one, then the device is synchronized by the external signal, with |
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zero phase shift. |
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Connecting together the SYNCH pin of two devices, the one with higher |
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frequency works as master and the other one as slave; so the two power |
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turn on have a phase shift of half a period. |
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3 |
INH |
A logical signal (active high) disable the device. With INH higher than |
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1.9 V the device is OFF and with INH lower than 0.6 V the device is ON. |
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4 |
COMP |
Error amplifier output to be used for loop frequency compensation |
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Feedback input. Connecting the output voltage directly to this pin the |
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5 |
FB |
output voltage is regulated at 0.6 V. To have higher regulated voltages an |
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external resistor divider is required from Vout to FB pin. |
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The switching frequency can be increased connecting an external |
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6 |
FSW |
resistor from FSW pin and ground. If this pin is left floating the deice |
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works at its free-running frequency of 250 kHz. |
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7 |
GND |
Ground |
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8 |
VCC |
Unregulated DC input voltage |
Doc ID 13006 Rev 5 |
3/37 |
Maximum ratings |
L5985 |
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2.1Absolute maximum ratings
Table 2. |
Absolute maximum ratings |
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Symbol |
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Parameter |
Value |
Unit |
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Vcc |
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Input voltage |
20 |
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OUT |
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Output DC voltage |
-0.3 to VCC |
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FSW, COMP, |
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Analog pin |
-0.3 to 4 |
V |
SYNCH |
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INH |
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Inhibit pin |
-0.3 to VCC |
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FB |
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Feedback voltage |
-0.3 to 1.5 |
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PTOT |
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Power dissipation at TA < 60 °C |
1.5 |
W |
TJ |
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Junction temperature range |
-40 to 150 |
°C |
Tstg |
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Storage temperature range |
-55 to 150 |
°C |
2.2Thermal data
Table 3. |
Thermal data |
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Symbol |
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Parameter |
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Value |
Unit |
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RthJA |
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Maximum thermal resistance |
VFQFPN |
60 |
°C/W |
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junction-ambient (1) |
1. Package mounted on demonstration board.
4/37 |
Doc ID 13006 Rev 5 |
L5985 |
Electrical characteristics |
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TJ = 25 °C, VCC = 12 V, unless otherwise specified.
Table 4. |
Electrical characteristics |
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Symbol |
Parameter |
Test condition |
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Values |
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Unit |
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Min |
Typ |
Max |
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VCC |
Operating input voltage |
(1) |
2.9 |
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18 |
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range |
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V |
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VCCON |
Turn on VCC threshold |
(1) |
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2.9 |
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VCCHYS |
VCC UVLO hysteresis |
(1) |
0.175 |
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0.3 |
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RDS(on) |
MOSFET on resistance |
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140 |
170 |
mΩ |
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(1) |
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140 |
220 |
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ILIM |
Maximum limiting current |
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2.5 |
2.9 |
3.3 |
A |
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Oscillator |
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FSW |
Switching frequency |
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225 |
250 |
275 |
kHz |
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(1) |
220 |
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275 |
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VFSW |
FSW pin voltage |
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1.254 |
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V |
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D |
Duty cycle |
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0 |
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100 |
% |
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FADJ |
Adjustable switching |
RFSW = 33 kΩ |
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1000 |
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kHz |
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frequency |
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Dynamic characteristics |
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V |
FB |
Feedback voltage |
2.9 V < V < 18 V (1) |
0.593 |
0.6 |
0.607 |
V |
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CC |
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DC characteristics |
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IQ |
Quiescent current |
Duty cycle = 0, |
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2.4 |
mA |
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VFB = 0.8 V |
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IQST-BY |
Total stand-by quiescent |
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20 |
30 |
μA |
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current |
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Inhibit |
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INH threshold voltage |
Device ON level |
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0.6 |
V |
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Device OFF level |
1.9 |
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INH current |
INH = 0 |
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7.5 |
10 |
μA |
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Soft-start |
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FSW pin floating |
7.4 |
8.2 |
9.1 |
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TSS |
Soft-start duration |
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ms |
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F = 1 MHz, |
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SW |
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2 |
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RFSW = 33 kΩ |
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Doc ID 13006 Rev 5 |
5/37 |
Electrical characteristics |
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L5985 |
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Table 4. |
Electrical characteristics |
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Symbol |
Parameter |
Test condition |
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Values |
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Unit |
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Min |
Typ |
Max |
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Error amplifier |
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VCH |
High level output voltage |
VFB < 0.6 V |
3 |
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V |
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VCL |
Low level output voltage |
VFB > 0.6 V |
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0.1 |
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IFB |
Bias source current |
VFB = 0 V to 0.8 V |
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1 |
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μA |
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IO SOURCE |
Source COMP pin |
VFB = 0.5 V, VCOMP = 1 V |
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20 |
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mA |
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IO SINK |
Sink COMP pin |
VFB = 0.7 V, |
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25 |
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mA |
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VCOMP = 1 V |
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GV |
Open loop voltage gain |
(2) |
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100 |
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dB |
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Synchronization function |
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High input voltage |
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2 |
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3.3 |
V |
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Low input voltage |
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1 |
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Slave sink current |
VSYNCH = 2.9 V |
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0.7 |
0.9 |
mA |
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Master output amplitude |
ISOURCE = 4.5 mA |
2.0 |
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V |
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Output pulse width |
SYNCH floating |
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110 |
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ns |
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Input pulse width |
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70 |
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Protection |
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IFBDISC |
FB disconnection source |
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1 |
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μA |
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current |
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TSHDN |
Thermal shutdown |
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150 |
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°C |
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Hysteresis |
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30 |
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1.Specification referred to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation.
2.Guaranteed by design.
6/37 |
Doc ID 13006 Rev 5 |
L5985 |
Functional description |
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The L5985 is based on a “voltage mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
●A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by a external resistor. The voltage and frequency feed forward are implemented.
●The soft-start circuitry to limit inrush current during the start up phase.
●The voltage mode error amplifier
●The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch.
●The high-side driver for embedded p-channel power MOSFET switch.
●The peak current limit sensing block, to handle over load and short circuit conditions.
●A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference.
●A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
●The thermal shutdown block, to prevent thermal run away.
Doc ID 13006 Rev 5 |
7/37 |
Functional description |
L5985 |
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Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connect to FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to keep the PWM gain constant versus the switching frequency (see Section 5.4 for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pin together. When SYNCH pins are connected, the device with higher oscillator frequency works as Master, so the Slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor [see L5988D data sheet].
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Clock |
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FSW |
Clock |
SYNCH |
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Synchronization |
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Generator |
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Ramp |
Sawtooth |
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Generator |
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The device can be synchronized to work at higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 5.c). This changing has to be taken into account when the loop stability is studied. To minimize the change of the PWM gain, the free running frequency should be set (with a resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of the frequency will change the sawtooth slope in order to get negligible the truncation of sawtooth, due to the external synchronization.
8/37 |
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L5985 |
Functional description |
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Figure 5. |
Sawtooth: voltage and frequency feed forward; external synchronization |
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Doc ID 13006 Rev 5 |
9/37 |
Functional description |
L5985 |
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The soft-start is essential to assure correct and safe start up of the step-down converter. It avoids inrush current surge and makes the output voltage increases monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error amplifier. So the output voltage slew rate is:
Equation 1
SROUT = SRVREF |
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R1 |
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+ ------- |
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R2 |
where SRVREF is the slew rate of the non-inverting input while R1 and R2 the resistor divider to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64 steps of
9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency.
Soft-start time results:
Equation 2
32 64 SSTIME = -----------------
Fsw
For example with a switching frequency of 250 kHz the SSTIME is 8 ms.
10/37 |
Doc ID 13006 Rev 5 |
L5985 |
Functional description |
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The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Error amplifier |
Value |
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Low frequency gain |
100 dB |
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GBWP |
4.5 MHz |
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Slew rate |
7 V/μs |
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Output voltage swing |
0 to 3.3 V |
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Maximum source/sink current |
25 mA/40 mA |
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In continuos conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see Chapter 5.4 for details about the compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.
Doc ID 13006 Rev 5 |
11/37 |
Functional description |
L5985 |
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4.4Over-current protection
The L5985 implements the over current protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns.
When the over current is detected, two different behaviors are possible depending on the operating condition.
1.Output voltage in regulation. When the over current is sensed, the power MOSFET is
switched off and the internal reference (VREF), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal reference begins ramping (see Figure 8.a).
2.Soft-start phase. If the over current limit is reached the power MOSFET is turned off implementing the pulse by pulse over current protection. During the soft-start phase, under over current condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If at the end of the “masking time” the current is higher than the over current threshold, the power MOSFET is turned off and it will skip one pulse. If, at the next switching on at the end of the “masking time” the current is still higher than the threshold, the device will skip two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time” the current is lower than the over current threshold, the number of skipped cycles is decreased of one unit. At the end of soft-start phase the output voltage is in regulation and if the over current persists the behavior explained above takes place. (see Figure 8.b)
So the over current protection can be summarized as an “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase.
If the output is shorted to ground when the output voltage is on regulation, the over current is triggered and the device starts cycling with a period of 2048 clock cycles between “hiccup” (power MOSFET off and no current to the load) and “constant current” with very short ontime and with reduced switching frequency (up to one eighth of normal switching frequency). See Figure 32 for short circuit behavior.
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