ST L4971 User Manual
L4971
1.5A STEP DOWN SWITCHING REGULATOR
1 FEATURES
■UP TO 1.5A STEP DOWN CONVERTER
■OPERATING INPUT VOLTAGE FROM 8V TO 55V
■PRECISE 3.3V (±1%) INTERNAL REFERENCE VOLTAGE
Figure 1. Package
DIP8 |
SO16W |
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■OUTPUT VOLTAGE ADJUSTABLE FROM 3.3V TO 50V
■SWITCHING FREQUENCY ADJUSTABLE UP TO 300KHz
■VOLTAGE FEEDFORWARD
■ZERO LOAD CURRENT OPERATION
■INTERNAL CURRENT LIMITING (PULSEBYPULSE AND HICCUP MODE)
■INHIBIT FOR ZERO CURRENT CONSUMPTION
■PROTECTION AGAINST FEEDBACK DISCONNECTION
■THERMAL SHUTDOWN
■SOFT START FUNCTION
2 DESCRIPTION
The L4971 is a step down monolithic power switching regulator delivering 1.5A at a voltage between 3.3V and 50V (selected by a simple external divider). Realized in BCD mixed technology, the device uses an internal power D-MOS transistor (with a typical Rdson of 0.25Ω) to obtain very high efficency and high switching speed.
Figure 1. Block Diagram
Table 1. Order Codes
Part Number |
Package |
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L4971 |
DIP8 |
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L4971D |
SO16W |
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L4971D013TR |
SO16 in Tape & Reel |
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A switching frequency up to 300KHz is achievable (the maximum power dissipation of the packages must be observed).
A wide input voltage range between 8V to 55V and output voltages regulated from 3.3V to 50V cover the majority of today’s applications.
Features of this new generations of DC-DC converter include pulse-by-pulse current limit, hiccup mode for short circuit protection, voltage feedforward regulation, soft-start, protection against feedback loop disconnection, inhibit for zero current consumption and thermal shutdown.
The device is available in plastic dual in line, DIP8 for standard assembly, and SO16W for SMD assembly.
Vi=8V to 55V |
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5 |
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8 |
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R1 |
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20K |
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L4971 |
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3 |
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4 |
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C1 |
C7 |
C2 |
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2 |
7 |
1 |
6 |
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L1 |
VO=3.3V/1.5A |
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220 F |
220nF |
2.7nF |
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126 H |
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63V |
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(77120) |
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R2 |
C6 |
D1 |
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100nF |
C8 |
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C5 |
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9.1K |
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STPS |
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3L60U |
330 F |
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100nF |
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C4 |
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22nF |
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D97IN748A |
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Rev. 11 |
May 2005 |
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1/13 |
L4971
Figure 2. Block Diagram
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VCC |
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5 |
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THERMAL |
VOLTAGES |
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SHUTDOWN |
MONITOR |
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CBOOT |
2 |
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CHARGE |
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INTERNAL |
INTERNAL |
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SS_INH |
INHIBIT |
SOFTSTART |
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REFERENCE |
SUPPLY |
5.1V |
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3.3V |
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7 |
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6 |
COMP |
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8 |
E/A |
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BOOT |
PWM |
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FB |
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R |
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3.3V |
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Q |
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CBOOT |
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S |
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CHARGE |
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DRIVE |
AT LIGHT |
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OSCILLATOR |
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LOADS |
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1 |
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4 |
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OSC |
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GND |
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OUT |
D97IN594 |
Figure 3. Pin Connections
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N.C. |
1 |
16 |
N.C. |
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GND |
2 |
15 |
N.C. |
GND |
1 |
8 |
FB |
SS_INH |
3 |
14 |
FB |
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SS_INH |
2 |
7 |
COMP |
OSC |
4 |
13 |
COMP |
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OSC |
3 |
6 |
BOOT |
OUT |
5 |
12 |
BOOT |
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OUT |
4 |
5 |
VCC |
OUT |
6 |
11 |
VCC |
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D97IN595 |
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N.C. |
7 |
10 |
N.C. |
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N.C. |
8 |
9 |
N.C. |
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D97IN596 |
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DIP8 |
SO16 |
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Table 2. Pin Description
DIP |
SO (*) |
Name |
Function |
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1 |
2 |
GND |
Ground |
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2 |
3 |
SS_INH |
A logic signal (active low) disables the device (sleep mode operation). |
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A capacitor connected between this pin and ground determines the soft start time. |
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When this pin is grounded disabled the device (driven by open collector/drain). |
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3 |
4 |
OSC |
An external resistor connected between the unregulated input voltage and this pin and |
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a capacitor connected from this pin to ground fix the switching frequency. (Line feed |
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forward is automatically obtained) |
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4 |
5, 6 |
OUT |
Stepdown regulator output |
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5 |
11 |
VCC |
Unregulated DC input voltage |
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6 |
12 |
BOOT |
A capacitor connected between this pin and OUT allows to drive the internal DMOS |
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Transistor |
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7 |
13 |
COMP |
E/A output to be used for frequency compensation |
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8 |
14 |
FB |
Stepdown feedback input. Connecting directly to this pin results in an output voltage of |
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3.3V. An external resistive divider is required for higher output voltages. |
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(*) Pins 1, 7, 8, 9, 10, 15 and 16 are not internally, electrically connected to the die.
2/13
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L4971 |
Table 3. Absolute Maximum Ratings |
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Symbol |
Parameter |
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Value |
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Unit |
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Minidip |
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S016 |
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V5 |
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V11 |
Input voltage |
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58 |
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V |
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V4 |
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V5,V6 |
Output DC voltage |
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-1 |
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V |
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Output peak voltage at t = 0.1µs f=200KHz |
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-5 |
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V |
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I4 |
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I5,I6 |
Maximum output current |
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int. limit. |
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V6-V5 |
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V12-V11 |
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14 |
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V |
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V6 |
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V12 |
Bootstrap voltage |
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70 |
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V |
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V7 |
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V13 |
Analogs input voltage (VCC = 24V |
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12 |
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V |
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V2 |
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V3 |
Analogs input voltage (VCC = 24V) |
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13 |
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V |
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V8 |
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V14 |
(VCC = 20V) |
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6 |
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V |
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-0.3 |
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V |
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Ptot |
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Power dissipation a Tamb ≤60°C |
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DIP8 |
1 |
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W |
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SO16 |
0.8 |
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W |
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Tj,Tstg |
Junction and storage temperature |
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-40 to 150 |
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°C |
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Table 4. Thermal Data |
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Symbol |
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Parameter |
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DIP8 |
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SO16 |
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Unit |
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Rth(j-amb) |
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Thermal Resistance Junction to ambient |
Max. |
90 (*) |
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110 (*) |
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°C/W |
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(*) Package mounted on board.
3 ELECTRICAL CHARACTERISTCS
Table 5. (Tj = 25°C, Cosc = 2.7nF, Rosc = 20kΩ, VCC = 24V, unless otherwise specified.) * Specification Refered to Tj from 0 to 125°C
Symbol |
Parameter |
Test Condition |
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Min. |
Typ. |
Max. |
Unit |
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DYNAMIC CHARACTERISTIC |
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VI |
Operating input voltage range |
Vo = 3.3 to 50V; Io = 1.5A |
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8 |
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55 |
V |
Vo |
Output voltage |
Io = 0.5A |
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3.33 |
3.36 |
3.39 |
V |
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Io = 0.2 to 1.5A |
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3.292 |
3.36 |
3.427 |
V |
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Vcc = 8 to 55V |
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3.22 |
3.36 |
3.5 |
V |
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Vd |
Dropout voltage |
Vcc = 10V; Io = 1.5A |
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0.44 |
0.55 |
V |
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* |
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0.88 |
V |
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Il |
Maximum limiting current |
Vcc = 8 to 55V |
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2 |
2.5 |
3 |
A |
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Efficiency |
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Vo = 3.3V; Io = 1.5A |
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85 |
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% |
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fs |
Switching frequency |
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90 |
100 |
110 |
KHz |
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SVRR |
Supply voltage ripple rejection |
Vi = Vcc+2VRMS; Vo = Vref; |
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60 |
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dB |
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Io = 1.5A; f ripple = 100Hz |
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Voltage stability of switching |
Vcc = 8 to 55V |
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3 |
6 |
% |
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frequency |
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Temp. stability of switching |
Tj = 0 to 125°C |
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4 |
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frequency |
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3/13 |
L4971
Table 5. (Tj = 25°C, Cosc = 2.7nF, Rosc = 20kΩ, VCC = 24V, unless otherwise specified.) * Specification Refered to Tj from 0 to 125°C
Soft Start
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Soft start charge current |
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30 |
40 |
50 |
µA |
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Soft start discharge current |
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6 |
10 |
14 |
µA |
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Inhibit |
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VLL |
Low level voltage |
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0.9 |
V |
IsLL |
Isource Low level |
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5 |
15 |
µA |
DC Characteristics |
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Iqop |
Total operating quiescent |
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4 |
6 |
mA |
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current |
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Iq |
Quiescent current |
Duty Cycle = 0; VFB = 3.8V |
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2.5 |
3.5 |
mA |
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Iqst-by |
Total stand-by quiescent |
Vinh <0.9V |
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100 |
200 |
µA |
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current |
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Vcc = 55V; Vinh<0.9V |
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150 |
300 |
µA |
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Error Amplifier |
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VFB |
Voltage Feedback Input |
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3.33 |
3.36 |
3.39 |
V |
RL |
Line regulation |
Vcc = 8 to 55V |
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5 |
10 |
mV |
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Ref. voltage stability vs |
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0.4 |
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mV/°C |
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temperature |
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VoH |
High level output voltage |
VFB = 2.5V |
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10.3 |
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V |
VoL |
Low level output voltage |
VFB = 3.8V |
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0.65 |
V |
Io source |
Source output current |
Vcomp = 6V; VFB = 2.5V |
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200 |
300 |
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µA |
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Io sink |
Sink output current |
Vcomp = 6V; VFB= 3.8V |
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200 |
300 |
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µA |
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Ib |
Source bias current |
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2 |
3 |
µA |
SVRR E/A |
Supply voltage ripple rejection |
Vcomp = Vfb; Vcc = 8 to 55V |
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60 |
80 |
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dB |
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DC open loop gain |
RL = ∞ |
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50 |
57 |
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dB |
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gm |
Transconductance |
Icomp = -0.1 to 0.1mA |
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2.5 |
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ms |
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Vcomp = 6V |
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Oscillator Section |
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Ramp Valley |
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0.78 |
0.85 |
0.92 |
V |
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Ramp peak |
Vcc = 8V |
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2 |
2.15 |
2.3 |
V |
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Vcc = 55V |
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9 |
9.6 |
10.2 |
V |
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Maximum duty cycle |
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95 |
97 |
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% |
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Maximum Frequency |
Duty Cycle = 0% ; |
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300 |
kHz |
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Rosc = 13kΩ, Cosc = 820pF |
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4/13
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