ST L296 Application Note

APPLICATION NOTE

DESIGNING WIT H THE L2 96 M ONO LIT HIC

POWER SWITCHING REGULATOR

A cost-effec tive repl acement for costly hybrids, t he L296 P ower Switc hing Regu lator d elivers 4A at an outpu t
voltage of 5.1V to 40V and includes many popular supply features. This comprehensive application guide
explains ho w t he de vi c e oper at e s an d how it is used. T y pic al application cir c uits ar e als o presented.

The SGS THOMSON L296 is the first monolithic
switching regulator in plastic package which inclu­des the power section. Moreover, the circuit inclu­des all the functions which make it specially suited
for microproc es s or su pply .

Before the introduction of L296, which realizes the
step down configuration, this function was imple­mented with discrete power components driven be
integrated PWM regulator circuits (giving a maxi­mum output curr ent of 300 to 400m A) or with h ybrid
circuits. B oth of these solutions are ch aracterized by
a low e fficienc y o f the powe r t ransis tor. For thi s rea ­son it is genera lly nec essary to oper at e at freq uen-

AN244/12 88

cies in the 20kHz to 40kHz range. Of the two alter­natives dis crete solutions are usually les s expensive
because they do not include as many functions as
the L296.

With the new L2 96 r egul at or the dr iv ing pro blem of
the power cont r ol s tage has been eliminated. B es i ­des a higher overall efficiency, it is therefore also
possible to op erate directly at f requencies as high as
100kHz. At 200 kHz the dev ice still op erates (fu rther
reducing the cost of the L and C external compo­nents) when a r eduction o f a few perc ent in effic ien­cy is acceptable.

1/43

APPLICATION NOTE

The device deliv ers a maximu m current of 4 A to the
load, at an output voltage adjustable from 5.1 to
40V ; the maximum operating input voltage is 46V.
The high vo ltage and the high cu rrent capab ilities of
the device are a result of the special technology
used and the spe cial care tak en in designi ng the po­wer transis tor. Essentia l requirements fo r a good po­wer transis tor are hi gh gain a nd high curr ent lev els,
low saturat ion volta ge and go od sec ond bre akdown
robustness . To achieve hig h gain at h igh c urrent le­vels, the po wer transis tor has to be de signed to ma­ximize the em itt er ’s per imet er /ar ea r at io.

In the L296 power transistor, realized with a high
voltage (50V) process, current densities in the ma­gnitude orde r of 10m A /M il

2

are achieve d.

In its most complete configuration, in which all the
available fu nc tions ar e being used, a si gnificant re­duction of the exter nal component count is achieved
compared w ith dis c r et e c om pone nt so lution.

The L296 is mounted in a MULTIWATT plastic
package with 15 pins, minimizing the cost per watt
and allowing a low therm al re sista nce of 3°C /W be ­tween junction and package and of 35°C/W be­tween junc tion and ambient. This thermal resi stance

Figure 1 :

The Basic Step-down Sw itc hing Regulato r C onfiguration.

(inclucing the contact resistance) is comparable to
that of the more c os tl y meta l T O- 3 pac k ages.

THE STEP-DOWN CONFIGURATION

Fig. 1 shows the sim plified blo ck di agram of the cir ­cuit realizing the step-down configuration. This cir­cuit operates as follow s : Q1 acts as a switc h at the
frequency f and the O N and O FF t im es a re s uitably
controlled by the pulse width modulator circuit.
When Q1 is satur ated , energy is a bsorbed fro m the
input which is transferred to the output through L.
The emitter v olt ag e of Q1, V
ON and -V

( with VF the forward volt age across the

F

, is Vi-Vsat when Q is

E

D diode as indicated) when Q1 is OFF. During this
second phase the current circulates again through
L and D. Consequently a rectangular shaped vol­tage appears on the emitter of Q1 and this is then
filtered by the L-C-D network and converted into a
continuou s mean value ac r os s the c apacitor C a nd
therefore across the load. The current through L
consists of a continuous component, I

LOAD

, and a

triangular-shaped component super-imposed on it,

∆

I

, due to the volt age a cr os s L.

L

2/43

APPLICATION NOTE

Figure 2 :

Princip al Ci rc ui t W av ef or ms of t he figure 1 Circuit .

3/43

APPLICATION NOTE

Fig. 2 shows the behaviour of the most significant
waveforms, in different points of the circuit, which
help to under stand better the o peration of the po wer
section of the switching regulator. For the sake of
simplicity , the ser ies r esist ance of the coi l ha s bee n
neglected. Fi g. 2a s hows the beha viour of the em it­ter voltage (which is practically the voltage across
the recircul ation diode), wh ere the p ower saturat ion
and the forwar d V

drop acro ss the diode e ra take n

F

into account .
The ON and OFF times are established by the fol-

lowing expression :

T

Vo = (Vi – V

sat

)

ON

+ T

T

ON

OFF

Fig. 2b shows the current acr oss the s witching tr an­sistor. Th e current sha pe is trapez oidal and the ope­ration is in continuous mode. At this stage, the
phenomena due to the catch diod e, that we consi der
as dynamically ideal, are neglected. Fig. 2c shows
the current cir culating in the reci rculation diod e. The
sum of the currents circulating in the power and in
the diode is the current circulating in the coil as
shown in fig . 2e. In balanced con ditions the ∆I
rent increase occuring during T
to the ∆I
mean value o f I

–

decrease occurring during T

L

correspond s to the charge c urrent.

L

has to be equal

ON

OFF

+

cur-

L

. The

The current ripple is given by the following formula :

(V

– V

i

IL+ = ∆IL

–

=T

V

+ V

o

=T

L

∆

It is a good rule to respect to Io

sat) – V

L

F

OFF

=

ON

≥ IL/2 relation-

MIN

ship, that implies good operation in continuous
mode. When this is not done, the regulator starts
operating in discontinuous mode. This operation is
still safe but variations of the switching frequency
may occur and th e output regulati on de cr ea se s.

Fig. 2d shows the behaviour of the voltage across
coil L. In balanced condit ions, the mean val ue of the
voltage acro ss the coil is z ero. Fig. 2f show s the cur­rent flowing through the capacitor, which is the dif­ference between I

and I

L

LOAD

.

In balanced conditions , the mean current is equal to
zero, and ∆I

= ∆IL. The current IC through the ca-

C

pacitor gives r is e to t he v oltage ripple.
This ripple c onsists of two co mponents : a capa citive
component, ∆V

∆

V

, due to the ESR eq uivalent se ries resi stance

ESR

, and a resistive component,

C

of the capacito r. F ig . 2g sh ows the capaciti ve c om -

ponent ∆V

of the voltage ripple, which is the inte-

C

gral of a triangular-shaped current as a function of
time. Moreover, it should be observed that v
in quadrature with i
age V

. The quantity of charge ∆Q+ supplied to

ESR

(t) and therefore with the volt-

C

(t) is

C

the capacitor is given by the area enclosed by the
ABC triang le in fig. 2f :

1T

∆

Q =

..

222

∆

I

L

which theref or e gi ve s :

∆

∆

V

Q

==

C

C8fc

Fig. 2h sh ows the vol tage ripple V

I

L

due to the r e-

ESR

sistive c omponen t of the c apacitor. Th is com ponent
is V
ple V

(t) = iC (t) ⋅ ESR. Fig. 2i s hows the overall ri p-

ESR

, which is the sum of the two pr evious co mpo-

o

nents. As t he frequenc y increas es (> 20kH z), whic h
is required to reduc e both t he c os t and t he siz e s of
L and C, the V

component becomes dominant.

ESR

Often it is necessary to use capacitors with greater
capacitanc e (or more capacitors connected in para l­lel to limit the v alue of ES R with in the requir ed level.

We will now exam ine the s tep down conf igur ation in
more detail, referring to fig. 1 and taking the beha­viour show n in fig . 2 int o ac c oun t.

Starting from the initial conditions, where Q = ON,
v

= Vo and iL = iD = 0, usi ng Kirckoff sec ond principle

C

we may wri te th e following expr es s ion :
V

= vL + vC (V

i

di

Vi = L + vC = L + V

L

dt dt

is neglected against Vi).

sat

di

L

o

(1)

which give s :

di

(Vi – Vo)

L

=(2)

dt L

The current t hr oug h th e ind uc t anc e is gi ve n by :

(V

– Vo)

I

L

When V

i

=t (3)

L

, Vo, and L are constant, IL varies linearly

i

with t. Therefore, it follows that :

(V

– Vo) T

i

+

∆

I

=(4)

L

ON

L

When Q is OFF t he curre nt throug h the co il has rea­ched its m aximum value, I

and because it cannot

peak

very instantaneously, the voltage across the coil is
inverted and the diode D becomes forward biased
to allow the recirculation of the current through the
load.

4/43

APPLICATION NOTE

When Q switches OFF, the following situation is pre­sent :

v

(t) = Vo, iL (t) = iD (t) = I

C

peak

And the equation associated to the following loop
may be written :

di

+ L + vC = 0 (5)

V

F

L

dt

where :
v

= V

C

o

dI

L

= – (VF + Vo)/L (6)

dt

It follows theref or e that :

V

+ V

F

iL (t) = – t (7)

o

L

The negativ e sign may be interpre tated with the fact
that the current is now decreasing. Assuming that V

F

may be neglected against Vo, during the OFF time
the following behaviour o ccur s :

V

o

IL =t (8)

L

therefore :

V

∆

I

– =T

L

o

OFF

L

(9)

But, because

+

∆

I

L

(V

which allows us to ca lc ula te V
Vo = V

–

= ∆I

if follows that :

L

– Vo) T

i

ONVo TOFF

=

LL

T

i

T

ON

ON

+ T

OFF

= V

:

o

T

ON

i

T

(10)

where T is the switching period.
Expressio n (10) l inks th e output voltage V

put voltage V

and to the d uty cycle. Th e relation-shi p

i

to the in-

o

between the cur r ents is th e following :

T

ON

I

iDC

= IoDC

.

T

EFFICIENCY

The system efficiency is expressed by the following
formula :

P

η

% = 100

where Po = VoI
is the output power to the load and P

wer absor be d by the system. P

o

P

i

o

(with Io = I

is th e input po -

i

is given by Po, plus

i

LOAD

)

all the other system losses. The expression of the ef­ficiency bec om es ther ef or e the following :

P

η

=(12)

P

+ P

o

o

+ PD + PL + Pq + p

sat

sw

DC LO SSES

P

: saturation losses of the power transistor Q.

sat

These losses increase as V

T

P

= V

sat

sat

where = and V

T

ON

. I

ON

TV

= V

o

V

sat Io

TV

o

i

decre ases.

i

V

o

i

is the power

sat

(13)

transistor s atur at ion at cu rrent Io.
P

: losses due to the recirculation diode. These

D

losses increase as V

increases, as in this

i

case the ON time of the diode is greater .

V

– Vo Vo

P

= VF I

D

where V
diode at curren t I

P

: losses due to th e se ri es resistance RS of the

L

coil

P

= RS I

L

P

: losses due t o t he s t an d-b y c ur r ent and to the

q

i

o

is the forward voltage of the recirculation

F

2

(15)

o

= VF Io (1 – ) (14)

Vi

V

i

.

o

power driv ing c ur r ent :

T

Pq = Vi I’3q + Vi I’’

3q

ON

T

(16)

where being :

T

Pq = Vi I’3q + Vo I’’
I’

3q

I’’

3q

V

ON

TV

= I

o

= it follows that :

i

in which :

3q (0 % d.c.)

3q

= I

3q(100 % d.c.)

3q

at 0 % duty cyc le

- I

SWITCHING LOSSES

P

: switching losses of the po wer t ra ns is tor :

sw

t

+ t

r

Psw = Vi I

o

f

2T

The switching losses of the recirculation diode are
neglected (which are a ny way n egli gible) as it i s as­sumed that diode is used with recovery time much
smaller than the rise time of the power transist or .

We can neglect loss es in the coil (it is assume d that

∆

I

is very small comp ared to Io) and in the output

L

capacitor, which is assu me d t o sh ow a low E S R .

5/43

APPLICATION NOTE

Calculation of the inductance value, L

Calculation T

ON

and T

through (4) and (9) re-

OFF

spectively it f ollo ws t hat :

L+

∆I

. L

=T

T

ON

Vi – V

o

OFF

∆

V

I

L

–

. L

o

But be c ause :

+

= ∆I

–

= ∆IL,

L

T

ON

+ T

= T and

OFF

∆

I

L

it follows that :

∆

V

I

L

– V

i

∆

. L

+ = T

IL . L

V

o

o

Calculatin g L, t he pr ev io us rel at ion bec om es :

(V

– Vo) V

i

L = T (18)

V

∆I

i

o

L

Fixing the current ripple in the coil required by the
design (for i ns t anc e 3 0% of I

), and introdu c ing th e

o

frequency in stead of the perio d, it follows that :

(V

– Vo) V

L = where L is in He nr y a nd f in Hz

i

. 0.3 . Io . f

V

i

o

Calculation of the output capacitor C

From the output node in fig. 3 it may be seen that
the current throug h the output capaci tor is given by :

i

(t) = iL (t) – I

c

Figure 3 :

o

Equivalent Circuit Showing Recircula­tion when Q1 is Turned Off.

From the beh av iour shown in f i g. 2 it may be calcu ­lated that the charge current of the o utput ca pacitor,
within a perio d, is ∆I

/4, whic h is su ppl ied for a time

L

T/2. It follows t her efor e t hat :

∆

I

∆

V

C

L

== = (19)

4C 2 8C 8fC

T

∆

IL T∆I

L

but, re membering e xpress ion (4) :

– Vo) T

(V

i

+

∆

I

= and TON =T

L

ON

LV

Vo

i

therefore equation (19) becomes :

(V

– Vo) V

=

i

8 V

∆

V

C

f2 L C

i

o

Finally, ca lc ula ti ng C it fol lows that :

(V

– Vo) V

8 V

i

∆VC f2 L

i

C = (20)

o

where : L is in Henrys

C is in Farads
f is in Hz

Finally, the f ollo wing express ion should be tru e :

∆

V

ESR

=(21)

max

Cmax

∆

I

L

It may happen tha t to s atis f y rel ation (21) a capaci­tance value m uch gr eater tha n the v alue c alc ulated
through (20) must be used.

TRANSIENT RESPONSE

Sudden variations of the load current give rise to
overvoltage s and undervol tages on the output volt­age. Since i
instantaneous variation of the load current ∆I

= C (dvc/dt) (22), where dvc = ∆Vo, the

c

o

is
supplied dur ing the transien t by the output capacitor.
During the transient, also current through the coil
tends to chang e its va lue.
Moreover, the fo llow ing is true :

di

vL = L (23) where diL = ∆Io.
v

= Vi – V

L

v

= V

L

L

dt

o

o

for a load incr eas e

for a load de crease

Calculating dt from (22) and (23) and equalizing, it
follows that :

di

L= C

v

L

dv

L

c

i

c

Calculating dvc and equalizing it to ∆Vo, it follows
that :

2

L∆I

∆

V

= (24) for + ∆I

o

∆

Vo = (25) for – ∆I

o

C(Vi – Vo)

2

L∆I

o

CV

o

o

o

From these two expressions the dependence of
overshoots and under shoo ts on the L and C val ues
may be observed. To minim ize ∆V

it is therefor e ne-

o

cessary to redu ce the ind ucta nce value L and to in ­crease the capacitance value C. Should other
auxiliary functions be r equired in the circuit l ike reset
or crowbar pro tecti ons and very v ariable lo ads m ay
be present, it is worthwhile to take special care for
minimizing these overshoots, which could cause
spurious operation of the crowbar, and the under­shoot, whic h co uld trigger the rese t fun ctio n.

6/43

APPLICATION NOTE

DEVICE DESCRIPTION

Fig. 4 shows the package in which the device is
mounted and the pin f unc tion assignments.

The internal structure of the device is shown in fig. 5.
Each block will now be exa m ined.

Power supply

The device is provid ed with an i nternal st abilized po ­wer supply that, besides supplying the reference

Figure 4 :

Pin Assignments of the L296.

voltage of 5 .1 V for th e w hole system, a ls o s upplied
the internal an alog blocks.

Special fe atur es of the v o lt age r ef er enc e are its ac ­curacy, tem perature stability a nd high line r ejection.
Through zenze-zap trimming, the voltage is within

±

2% limits.

Figure 5 :

Block Di agr am of th e L29 6. In Ad dit io n t o the B as ic Regulation L oop the Device incl udes Func­tions such a s R es et , Cro wbar and Current Li mi ting.

7/43

APPLICATION NOTE

OSCILLATOR

The oscillator bloc k generates th e s a w- toot h w av e ­form that s ets the switchin g frequency of the system.
This signal , compar ed with the o utput volta ge of the
error ampl ifier, gener ates the PWM signal to b e sent
to the power output stage. The saw-tooth, whose
amplitude is between 1.2V and 3.2V, is generated
by chargi ng rapidly the C
scharges across the R

capacitor whi ch then di-

osc

resistance. As shown in

osc

fig. 6, the os cillator is realiz ed by a comparator (with
grounded compatible input) with hysteresis whose
thresholds are 1.2V and 3.2V respectively . The C
capacitor and the R

resis-tance ar e connecte d to

osc

osc

the non-in ve rtin g input of the com pa ra to r whi ch s et
the oscillating freque nc y is fix ed . W hen the voltage
on pin 11 is less than 3.2V, the switch S
and the c ur ren t generator ch ar ges the C
tor rapidly ; in t his phase S

is also closed. As soon

2

is closed

1

capaci-

osc

as 3.2V is r eache d the com para tor outpu t dri ves S
open (theref ore opening S1, too) ; the inver ting input
voltage is reduc ed to about 1.2V and the cap ac it or

Figure 6 :

Internal Schematic of the Osc i llat or .

starts to disc harge itself ac ross the R
I

effect is n eglected). W hen t he v ol t age rea c hes

bias

1.2V, S

and S1 close agai n and a n ew cycle star ts.

2

osc

The generated wav ef or m is sh own in f ig. 7.
To achieve a good accuracy of the switching fre-

quency it is es sentia l to have a c hargin g time of the
capacitor which is much smaller than the dischar­ging time. In t his w ay, the o sci llatio n frequ ency only
depends on the ext ernal components C
For this reas on the capacitor charging curre nt (when
S

is ON) is typically around 10mA. For example,

1

with a 2.2nF capacitor to switch from 1.2V to 3.2V
about 400ns is requi red, whic h is neglig ible c ompa ­red to the 10µs period that occ ur s when the opera­tion is performed at 100kHz. The diagrams shown
in fig. 8 all ow the ca lcula tion of the R
fig. 8) with C

as a parameter (C3 in fig. 8) when

osc

osc

the oscillat ion frequency requir ed for operation has

2

been previous l y fix ed.

resistor (the

and R

osc

osc

value (R1 in

.

8/43

APPLICATION NOTE

Figure 7a :

Figure 7b :

Figure 8 :

Oscillator Waveform at Pin 11 with
f = 100Khz (R
C

= 2.2nF).

osc

= 4.3KΩ,

osc

Oscillator Waveform at Pin 11 with
f = 50Khz (R
C

= 2.2nF).

osc

= 9.1KΩ,

osc

Nomogram for the Choice of Osc il lat or
Component s.

Fig. 8 shows two s uggested v alues for the C

osc

ca­pacitance . Exce ssive ly low ca pacit an ce value may
give ris e to an inacc uracy of th e upper thr eshold due
to the switch ing delays of the comparator . This inac­curacy in caused by an excessively short rise time
of the voltage. A capacitance value too high gives
rise to a charging time which is too com pared to the
discharging time. An additional inaccuracy cause
would be therefore present for the switching fre­quency, now due to spread of t he c ha rg e cu rr en t.

The oscillation frequency is given by the following
formula :

f

= (26)

osc

1

R

osc Cosc

PWM (se e fig. 9)
The PWM signal is generated on the comparator

output ; the triangular-shaped waveform and the
continuous signal coming from the output of the
transconductance error amplifier are sent to its in­puts. The PWM s ign al is then transfer re d t o th e dr i­ving stage of the out p ut powe r tr ans is t or .

SOFT START (see fig. 9)
Soft start is an essential function for co rrect start-up,

to prevent stresses and possible breakdown from
occurring in the power tra nsistor and to ob tain a mo­notonical ly inc r eas ing out pu t voltage.
In particul ar, the L296, as it does not have any du ty
cycle li mitation a nd due to t he ty pe of curre nt l imita­tion does n ot allow the output to be for ced to a s tea­dy state without the aid of the soft-start facility.
Soft-start operates at the sta rt-up of the s yste m, af­ter the inhi bit ha s b een activated, a fte r a n interven­tion of the current limitatio n and after the intervention
of the thermal p rotection.

The soft-s tart f unc tion is realized through a cap ac i­tor connec te d to pin 5 whic h is c har ged at cons t ant
current (≅ 100µA) up to a value of about V

REF

. Du­ring the charging time, through PNP transist or Q58,
the voltage on pin 9 is forced to increase with the
same rising speed as on pin 5. S t ar ting f ro m the di­scharged capacitor condition (pin 5 voltage = 0V)
the power transistor is in the OFF condition, as the
voltage on pin 9 is smaller than the minimum level
of the ramp vol tage. As the c apacitor is cha rged, the
PWM sign al begins to be ge nerated as soon as the
error amplif ier output v oltage cr osses t he ramp ; t he
power stage starts t o switc h with stea dily in creasing
duty cycle. This behaviour is shown in fig. 10. As
soon as the steady conditi on is reac hed the duty cy ­cle sets itself to the right value due to the effect of
the feedback network while the soft-start capacitor
completes its charging to a value very close to V

REF

.

9/43

APPLICATION NOTE

The soft-start effect is determined, apart from the
switch-on tim e, when the curre nt limitation operat es,
due to either an overload or a short circuit, to keep
the mean value of the current absorbed by the po­wer supply low.

Moreover f rom f ig. 11 i t m ay be obs erved that s inc e
the voltage on pin 9 can decrease under the mini-

Figure 9 :

Partial Inte rna l S c hem at ic S how ing PWM and Sof t S t ar t Blo ck s .

mum ramp lev el and incre ase over the max imum le­vel no limitat ions have been provide d on the duty cy­cle, whi ch there fore may vary bet ween 0 and 10 0%.

Figure 10 :

10/43

Soft Start Wav eforms. When power is applied, or after an inhi bit , t he L2 96’s output curren t
rises slowly under cont r ol of t he s oft start ci rcuit.

APPLICATION NOTE

Figure 11 :

Waveform f or Calc ul at ion of Duty Cy c le an d S of t Star t Tim e.

CALCULATING THE DUTY CYCLE AND
SOFT-START TIME

Assume, for simplicity, that the rising edge of the
ramp is instantan eous ; V
error amplifie r and V
The PWM c om pa ra to r bl oc k s witches w he n V

is the ou tput voltage of the

r

the ramp voltage (see fig . 11).

c

= V

r

; therefore :

V

= Vc = E e R

r

–

t

osc Cosc

Consequent ly :
t = R

osc Cosc

The time obtained from this expression is the T

In

E

V

r

OFF

time of the pow er transistor. Th e duty cyc le d is given
by :

T

d = = =

= 1 – In =

T – R

ON

osc Cosc

TT

EVo

V

V

r

i

In

E

V

r

(27)

Consequently, starting with the capacitor dischar­ged, the outp ut of the regu lator will be at the nom inal
level when the voltage at the terminal of the capa­citor (which is charged by a constant current) has
reached V

t

start-up

=

– 0.5V.

r

C

ss

(Vr – 0.5V)

I

5so

where Css is the soft-start capacitor and I
charging c ur re nt.

Consider ing as the soft-star t tim e the t im e r eq uir ed
for the soft-start capacitor to charge from
(1.2 V – 0.5V) to V

c

t

=

ss

C

(Vr – 1.2)

ss

I

sso

– 0.5V, gives :

r

substituting Vr from (27) gives :

V

o

– ( 1 –

Vr = E e

)

V

i

substitu ting into (28) giv es :

V

o

C
I

ss

sso

tss = (E e – 1. 2)

(

– 1

V

i

)

SYNCHRONIZATION

The synchronization function is available on pin 7,
this function allows the device to be swi t ch ed at an
externally generated frequency (leaving pin 11
open), or to mutually synchronize several devices,
using one of them as mas ter and the o thers as slav e
(fig. 12).

This allows several devices to be operated at the
same frequen cy, avoiding un desirable interm odula­tion pheno mena. T he number if mutua lly syn chroni­zable devices is obviously much greater than the
three devic es s hown in the figure. It is a ny way diffi-

5so

is the

11/43

APPLICATION NOTE

cult to establish an exact maximum number of de­vices, as it depends on diff er ent co nditions.

The first consideration concerns the accuracy which
must be achieved a nd maintained on the oscillation
frequency. Since the bias current on pin 7 is an output
current, the sum of all the bias currents must be much
smaller than the capacitor discharge current in close
proximity to the lower discharge threshold. Therefore,
assuming C

= 2.2nF and R

osc

= 4.3KΩ, it follows

osc

that :

1.2V

4.3K

Ω

= 280µA

Assuming that a 10% variation may be accepted, it
follows therefor e th at the num ber of sync hroni zable
devices is giv en b y :

N =
This means t hat if the overall I

28µA

I

bias max

is too high it m ay

bias

modify the dis c har gi ng t im e of t he c apa ci t or.
The second consideration concerns the layout de-

sign.
In the presence of a gre at num ber of devic es to be
synchronized, the leng ht of the paths ma y bec o me
significant and therefore the distributed inductance
introduced alo ng the pat hs may begi n to modify the
triangular shaped waveform, particularly the rising
edge which is very stee p. This effect would affec t the
devices that are physical ly located mo re distant from
the master d evice .

The ampli tude of the saw-too th to be externally con­nected must be wit h i n 0. 5V and 3. 5V , va lues also
represe nting the maximum swing o f the error a mpli­fier output.

CURRENT LIMITATION

The current limitation function has been realized in
a rather innova t iv e way to av oid overlo ad c on dit io n
during the short ci rcuit operation . In fact, while for al l
the other devices a constant current limitation is im­plemented b y acti ng on the d uty cycle (therefo re, i n
short circuit conditi ons an output curr ent is equal t o
the maximum limitation current), the new control ap­proach allows operation in short circuit conditions
with a mean curren t much sm aller tha n the all owed
4A value. Ope ration of the curr ent limiter will n ow be
described .
Refer to the bloc k d iagr am , fig. 13.

The curre nt which is de liv er ed from the output tr an­sistor to the load flows throu gh the cu rr en t sens ing
resistor R

. When the voltage drop on RS is equal

S

to the offset voltage of the current comparator, the
comparator generates a set pulse for the flip-flop,
with a delay of about 1µsec. The pu rpose of this de­lay is to avoid triggering of the protection circuit on
the curren t pe ak tha t o ccurs dur ing the recir culatio n
phase. There fore, the output

Q goes low and the po­wer stage is immed iately switch ed off, while the o ut­put

Q goes high and acts directly on the soft-start
capacitor dischargng the soft-start capacitor at a
constant curr en t (about 50µA).

When the voltage on pin 5 reaches 0.4V the com­parator triggers, supplying a reset pulse to the flip­flop ; from now on, the power stage is enable and
the soft-start phas e starts again. When the limit ation
cause, eit her overlo ad or s hort circu it, is stil l pres ent
the cycle rep eats again. The waveform of the ou tput
current on pin 2 is s ho wn in fig. 14.

Figure 12 :

12/43

In multiple su ppl ies se v era l l296’s can be sync hr onized as show n her e.

APPLICATION NOTE

From fig. 14 it m ay be observed how this curren t li­mitation techn ique allows the sh ort circuit operation
with a very lo w output curren t value.

It is possible to reduce the maximum current value
by acting o n pin 4. On this p in a voltage of about 3.3V

Figure 13 :

Partial S ch em at ic S how ing the Current Lim iter Circuit .

is present ; by connecting a resistance a constant
current, giv en by 3.3/R, is se nt to gro und. T h is cu r­rent reduces the offset voltage of the current com­parator, therefore anticipating its triggering
threshold.

Figure 14a :

Current Limiter Waveforms.

13/43