ST AN4030 APPLICATION NOTE

AN4030

Application note

Gate to cathode capacitor, impact on Triac immunity and reliability

Introduction

Triacs and SCRs are power semiconductors which are usually directly connected to the grid line. As is well known, the AC grid voltage can be highly perturbed by important voltage variation during very short times, for example, mechanical relay contact bounce, universal motor disturbances. Several electromagnetic standards describe how appliances have to be tested to check their immunity to such events. For example, the IEC 61000-4-4 standard gives the test procedures and immunity requirements respectively for fast transient voltages.

To increase power-semiconductor device immunity, most designers add a capacitor across the power device control terminal (the gate for SCRs or Triacs) and its reference terminal (K or A1 respectively for SCRs and Triacs). This capacitor helps stabilize the control terminal potential and so is believed to help increase resistance to fast voltage rises (dV/dt). As this capacitor is also placed between the power device and the control circuit, which could be a logic gate or a microcontroller unit (MCU), it acts as a filter on the path from the line to the sensitive control circuit, and helps filter the noise coming from line disturbances.

This paper demonstrates why a gate to cathode capacitor is not efficient to improve Triac immunity to fast voltage transients, especially for non-sensitive devices. This Application note demonstrates that such capacitors can increase the risk of failure for repetitive or accidentally high dI/dt.

The results presented in this Application note have been produced over a considerable period of time. Some products, which are used as examples to present these results, may no longer be available. However, the results presented apply to classes and types of product, and thus are equally applicable to similar products available in the market.

March 2012

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Contents	AN4030

Contents

1	Gate to cathode capacitor, impact on dV/dt immunity . . . . . . . . . . . .		. 3
	1.1	dV/dt test method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3
	1.2	dV/dt improvement for SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	1.3	Behavior of Triacs regarding dV/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	1.4	Behavior of Triacs to EFT (electrical fast transient) . . . . . . . . . . . . . . . . . .	8
2	Gate to cathode capacitor, impact on dI/dt capability . . . . . . . . . . . . .		11
3	Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
4	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14

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AN4030	Gate to cathode capacitor, impact on dV/dt immunity

1 Gate to cathode capacitor, impact on dV/dt immunity

1.1dV/dt test method

To characterize device immunity, semiconductor companies give the maximum dV/dt rate which can be applied across a device without a risk of triggering it.

The test schematic features a dV/dt generator which applies a voltage-versus-time linear slope (see Figure 1). The test equipment detects if the voltage across the DUT (device under test) decreases below a given threshold. For a given dV/dt level, if the device voltage drops below this threshold, this means that the device has switched on. The DUT capability is then lower than this dV/dt rate. The dV/dt parameter specified in the device datasheet is then the minimum rate that all devices were able to withstand during the tests.

Figure 1. dV/dt test simplified schematic

		20 Ω
		dV/dt generator
		(LEMSYS 50)		Device	Triac
		V			or
	+		VT	under test
		-	< VDRM		SCR
		Vpeak			Gate to
		(Fixed value: usually 67% x VDRM		IT
		dV/dt			cathode
		t			capacitor

The dV/dt parameter is usually measured under the following conditions:

●Peak applied voltage = 67% of VDRM

●Maximum junction temperature (125 °C most of the time)

●Gate open

These test conditions are the worst case, as the dV/dt immunity decreases if both the junction temperature and the impedance between G and K increase.

The following figures give an example of a 600 V SCR dV/dt measurement. A 402 V peak voltage is applied, as it represents 67% of the specified VDRM. In Figure 2, the device remains off. There is no current increase. In Figure 3, the same device switches on approximately 2 µs after the voltage reaches its peak and stable level. According to these two results, it could be said that the tested SCR is able to withstand a 150 V/µs rate.

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Figure 2. c test with a 150 V/µs slope

VT

402 V

I T

Figure 3. 600 V SCR test with a 160 V/µs slope

VT

I T

402 V

1.2dV/dt improvement for SCR

To understand why a semiconductor can be triggered by a dV/dt slope applied across its terminals, it should be kept in mind that semiconductor devices are composed of several silicon layers. An SCR features four layers, alternatively doped by holes (P area) or by electrons (N area). Each PN junction presents a spurious capacitance (see Figure 4). When a voltage slope is applied, a spurious capacitive current (ICAP) is induced by these capacitances. This current can then flow to the cathode through the P1-N1 junction and cause device switch-on. To solve this issue, an impedance, for example a resistor (refer to gate to cathode resistor in Figure 4), could be added between the gate and cathode terminals. The spurious capacitive current is then shunted and avoids the device being triggered.

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AN4030	Gate to cathode capacitor, impact on dV/dt immunity

Figure 4. SCR simplified silicon structure and spurious capacitive current

	ICAP
	Cathode (K)
N1	RGK
	C N1/P1
P1
	C P1/N2
	Gate (G)
N2
	C N2/P2
P2
	Anode (A)

A better solution could be found if a capacitor is used instead of a resistor. A high-voltage gate to cathode capacitor is not necessary because only a low voltage (VGK is around 1 V typically) is applied across this capacitor.

Figure 5 shows the typical relative dV/dt increase versus gate-cathode capacitance for an 8 A sensitive SCR series (IGT max = 0.2 mA). The SCR dV/dt could be improved more than ten times with a 100 nF gate to cathode capacitor.

It should be noted that a gate to cathode resistor is still used in parallel with the gate to cathode capacitor to discharge it after gate current removal.

For non–sensitive SCRs (IGT above around 5 mA), a gate to cathode capacitor does not improve dV/dt immunity a lot. Indeed, these devices already feature a very low internal gate to cathode resistor. So adding any external component is not very efficient to shunt the spurious capacitive current.

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