ST AN3994 Application note

AN3994

Application note

Managing the best in class MDmesh™ V and MDmesh™ II super junction technologies: driving and layout key notes

Introduction

One of the bigger challenges of the 21st century is to deal with the growing need for power and, at the same time, the necessity of product compactness.

The new MDmesh™ V series from STMicroelectronics, based on the super junction

concept, meets these targets by offering an extremely low RDS(on) value in a given package, unobtainable in standard HV MOSFETs.

In addition to the dramatic reduction of RDS(on), super junction MOSFETs are extremely fast in transients and this may lead to some issues when a better performing technology

replaces an older version on the same board with the same driving network.

The two main components in the ST super junction MOSFET family (MDmesh™ II and MDmesh™ V) are analyzed and compared in terms of energy losses, voltage, and current rates. It is shown how the external driving network impacts on their performances. Furthermore, a separate section is dedicated to the layout parasitic effects and their impact on MOSFET behavior.

It is clear in the end that layout can be crucial, especially when managing very fast transients, and it must be carefully planned in order to help the MOSFET exploit its best potential.

December 2011

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Contents	AN3994

Contents

1	ST multidrain technology evolution . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Parasitic capacitances overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
3	MOSFET standard turn-on and turn-off analysis . . . . . . . . . . . . . . . . .		11
4	Gate charge curve impact on dynamic responses . . . . . . . . . . . . . . .		15
5	Latest ST MD II and MD V technology at a glance . . . . . . . . . . . . . . . .		20
6	MD II and MD V: which is the lowest loss one? . . . . . . . . . . . . . . . . . .		21
	6.1	STB42N65M5 vs. STW48NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	6.2	STP35N65M5 vs. STB36NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	6.3	STP21N65M5 vs. STP24NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	6.4	STP16N65M5 vs. STP18NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	6.5	Comments about energy ON comparison . . . . . . . . . . . . . . . . . . . . . . . .	33
	6.6	Comments about energy OFF comparison . . . . . . . . . . . . . . . . . . . . . . .	33
7	MOSFET critical parameters in high switching environments . . . . . .		36
	7.1	Parasitic inductance influence on switching losses . . . . . . . . . . . . . . . . .	36
	7.2	Common source inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37

7.3Minimizing common source inductance: layout optimization and Kelvin

source connection on STW77N65M5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.4Minimizing common source inductance impact at turn-off: negative

		VGMoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	7.5	Switching loop inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		52

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AN3994	List of figures

List of figures

Figure 1. Standard HV MOSFET device cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. MD device cross section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Silicon ideal limit, SJ limit and ST MD V position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. ST’s HV technology evolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. N-channel Power MOSFET structure and intrinsic capacitances . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Equivalent model of Power MOSFET intrinsic capacitances . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Clamped inductive load test circuit used to carry out the dynamic tests on the MOSFETs 10 Figure 8. Turn-on of a MOSFET in a clamped inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. Equivalent capacitive model of a MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10. Turn-off of a MOSFET in a clamped inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Vg(t) curve measured on STB42NM60N @16 A, 400 V, IG=1.5 mA . . . . . . . . . . . . . . . . . 17 Figure 12. Vg(t) curve measured on STW48NM60N @16 A, 400 V, IG=1.5 mA . . . . . . . . . . . . . . . . 17 Figure 13. Turn-on of STB42N65M5 @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14. Turn-on of STW48NM60N @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15. Turn-off of STB42N65M5 @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Turn-off of STW48NM60N @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. Minimum RDS(on) per package achievable by MD II and MD V . . . . . . . . . . . . . . . . . . . . 20 Figure 18. STB42N65M5 vs. STW48NM60N Eon @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. STB42N65M5 vs. STW48NM60N di/dt at turn-on @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . 21 Figure 20. STB42N65M5 vs. STW48NM60N dv/dt at turn-on @ 8 A/16 A 400 V . . . . . . . . . . . . . . . . 22 Figure 21. STB42N65M5 vs. STW48NM60N zoom of dv/dt at turn-on @ 8 A/16 A 400 V . . . . . . . . . 22 Figure 22. STB42N65M5 vs. STW48NM60N Eoff @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 23. STB42N65M5 vs. STW48NM60N di/dt at turn-off @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . 23 Figure 24. STB42N65M5 vs. STW48NM60N dv/dt at turn-off @ 8 A/ 16 A, 400 V . . . . . . . . . . . . . . . 24 Figure 25. STP35N65M5 vs. STB36NM60N Eon @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 26. STP35N65M5 vs. STB36NM60N di/dt at turn-on @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . 25 Figure 27. STP35N65M5 vs. STB36NM60N dv/dt at turn-on @ 7.5 A/15 A 400 V . . . . . . . . . . . . . . . 25 Figure 28. STP35N65M5 vs. STB36NM60N Eoff @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 29. STP35N65M5 vs. STB36NM60N di/dt at turn-off @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . 26 Figure 30. STP35N65M5 vs. STB36NM60N dv/dt at turn-off @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . 27 Figure 31. STP21N65M5 vs. STP24NM60N Eon @ 4 A/ 8 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 32. STP21N65M5 vs. STP24NM60N di/dt at turn-on @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 28 Figure 33. STP21N65M5 vs. STP24NM60N dv/dt at turn-on @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 28 Figure 34. STP21N65M5 vs. STP24NM60N Eoff @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 35. STP21N65M5 vs. STP24NM60N di/dt at turn-off @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 29 Figure 36. STP21N65M5 vs. STP24NM60N dv/dt at turn-off @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 30 Figure 37. STP16N65M5 vs. STP18NM60N Eon @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 38. STP16N65M5 vs. STP18NM60N di/dt at turn-on @ 3 A/ 6 A, 400 V . . . . . . . . . . . . . . . . . 31 Figure 39. STP16N65M5 vs. STP18NM60N dv/dt at turn-on @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . 31 Figure 40. STP16N65M5 vs. STP18NM60N Eoff @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 41. STP16N65M5 vs. STP18NM60N di/dt at turn-off @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . 32 Figure 42. STP16N65M5 vs. STP18NM60N dv/dt at turn-off @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . 33 Figure 43. Equivalent capacitive model of a MOSFET with parasitic inductances at turn-on . . . . . . . 36 Figure 44. Turn-on of STW77N65M5@400 V, 13 A, 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 45. Equivalent driving circuit of a MOSFET at turn-on with parasitic source inductance . . . . . 38 Figure 46. Simplified equivalent series resonant model of the driving circuit of a MOSFET . . . . . . . . 39 Figure 47. Gate driving and main switching loops for a MOSFET in a BOOST-like topology . . . . . . . 40 Figure 48. STW77 energy ON difference between the standard layout and the optimized layout . . . 41 Figure 49. STW77 energy OFF difference between the standard layout and the optimized layout. . . 41

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List of figures		AN3994
Figure 50. STW77N65M5 Eoff @ 20 A, 2.2 W with non-optimized common path. . . . . . . . . . .		. . . . . 42
Figure 51. STW77N65M5 Eoff @ 20 A, 2.2 W with non-optimized common path. . . . . . . . . . . .		. . . . 42
Figure 52. STW77N65M5 Eoff @ 20 A, 2.2 W with optimized common path . . . . . . . . . . . . . . .		. . . . 42
Figure 53. STW77N65M5 Eoff @ 40 A, 2.2 W with non-optimized common path. . . . . . . . . . . .		. . . . 43
Figure 54. STW77N65M5 Eoff @ 40 A, 2.2 W with non-optimized common path. . . . . . . . . . . .		. . . . 43
Figure 55. STW77N65M5 Eoff @ 40 A, 2.2 W, 400 V with optimized common path . . . . . . . . .		. . . . 43
Figure 56. STW77N65M5 Eon@20 A, 2.2 W with no n-optimized common path . . . . . . . . . . . .		. . . . 44
Figure 57. STW77N65M5 Eon@20 A, 2.2 W with non-optimized common path. . . . . . . . . . . . .		. . . . 44
Figure 58. STW77N65M5 Eon@20 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . .		. . . . 44
Figure 59. STW77N65M5 Eon@20 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . .		. . . . 44
Figure 60. STW77N65M5 Eon@40 A, 2.2 W with non-optimized common path. . . . . . . . . . . . .		. . . . 45
Figure 61. STW77N65M5 Eon@40 A, 2.2 W with non-optimized common path. . . . . . . . . . . . .		. . . . 45
Figure 62. STW77N65M5 Eon@40 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . .		. . . . 45
Figure 63.	STW77N65M5 Eon@40 A, 2.2 W with optimized common path. . . . . . . . . . . . . .	. . . . 45
Figure 64. Schematic of 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 46
Figure 65. STW77N65M5 energy ON difference between the optimized layout (3-pin) and 4-pin
	solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 46
Figure 66. STW77N65M5 energy ON difference between the optimized layout (3-pin) and 4-pin
	solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 47
Figure 67. STW77N65M5 energy OFF difference between the optimized layout (3-pin) and 4-pin
	solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 47
Figure 68. STW77N65M5 Eoff@20 A, 2.2 W, 400 V 4-pin solution. . . . . . . . . . . . . . . . . . . . . . .		. . . . 48
Figure 69. STW77N65M5 Eon@20 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 48
Figure 70. STW77N65M5 Eon @20 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 48
Figure 71. STW77N65M5 Eon@40 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 49
Figure 72. STW77N65M5 Eon@40 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 49
Figure 73. Basic driving stage of a Power MOSFET at turn-off with negative VGM . . . . . . . . . .		. . . . 49
Figure 74. STW77N65M5 Eoff@52 A, 4.7 W, 400 V, VGMoff=-5 V . . . . . . . . . . . . . . . . . . . . . .		. . . . 50
Figure 75.	STW77N65M5 Eoff@52 A, 4.7 W, 400 V, VGMoff=-5 V . . . . . . . . . . . . . . . . . . . . . .	. . . . 50

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AN3994	ST multidrain technology evolution

1 ST multidrain technology evolution

At the beginning of 2000, STMicroelectronics introduced the super junction MOSFET technology to the market, the basic structure of which is clear from Figure 1:

Figure 1. Standard HV MOSFET device cross section

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Figure 2. MD device cross section

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As concerns standard MOSFET technology, designers understand that RDS(on) * area and breakdown voltage are associated with a theoretical limit which strictly depends on the material and can not be overcome. Development efforts of the major suppliers have mainly

focused on making the RDS(on)* area as close as possible to this physical limit, by reducing the most important contributions of a high voltage Power MOSFET to the total RDS(on).

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Figure 3.

ST multidrain technology evolution	AN3994

Silicon ideal limit, SJ limit and ST MD V position

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			6L ,*%7
22 AREA
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RJFET and RCHANNEL were significantly lowered by increasing the cell density and optimizing their structure, and by also reducing, at the same time, the channel length.

Thanks to the continuos optimization of resistivity and the thickness of N-Drift, the REPY contribution has been lowered, but the need to guarantee the same breakdown voltage and avalanche capability establishes the well known “Silicon Ideal limit”, as shown in Figure 3.

The MD concept, based on SJ technology, has overcome this limit: through the p-doped column insertion under the device strips, it has been possible to significantly lower the resistivity of the epitaxial N region without compromising the breakdown capability and

enabling a dramatic reduction in RDS(on): the particular p-column geometry and the alternating of p regions with n regions allows a constant electric field in the whole drain

volume despite the low resistivity in the conducting region: as a direct consequence, it was possible to achieve an RDS(on) * area reduction, previously not possible, by keeping the same voltage capability.

From this starting point, MD technology moved towards RDS(on) continuous optimization, as seen in Figure 4.

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AN3994	ST multidrain technology evolution

Figure 4. ST’s HV technology evolution

		-$MESH
				-$MESH ))
CMM/HM					-$MESH 6
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The MD II generation has already optimized the RDS(on) * area of about 40% compared to the first MD version, with an average value of about 30 mΩ*cm2.

The excellent achievement of the MD II enabled STMicroelectronics to establish a new milestone in the power switch arena with the last MD V generation.

Thanks to a proprietary ST technology, an extremely low value of p-column distance has been reached, therefore overcoming the physical limit imposed by the diffusion process. Additionally, the geometry of the p-columns was also optimized by a more effective diffusion

process which enabled up to 40% reduction of RDS(on) * area if compared to the previous MD II generation.

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Parasitic capacitances overview	AN3994

2 Parasitic capacitances overview

When dealing with high speed switching applications, the most critical MOSFET parameters limiting its dynamic response are the parasitic capacitances.

Figure 5 shows the physical origin of the parasitic component in an N-channel Power MOSFET:

Figure 5. N-channel Power MOSFET structure and intrinsic capacitances

			Source metal
Intermediate dielectric
Polysilicon gate			4
Gate oxide	1	6	3
N++ source	2	5	N++ source
P/P+ Body			P/P+ Body

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Figure 6. Equivalent model of Power MOSFET intrinsic capacitances

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Cgs is mainly due to the overlap between the gate and the source metallization (“3” and “4” components in Figure 5 and 6). Capacitors “5” and “6” are MIS (metal-insulator- semiconductor) capacitors between the gate and the p-body. The Cgs value is linked to the geometry of the device and it's almost independent of the voltage applied.

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AN3994	Parasitic capacitances overview

Cgd is the sum of two contributions: the first one is related to the overlap of the JFET region and the gate electrode (“1” component in Figure 5 and 6). The second component is the capacitance of the depletion region under the gate (“2” component in Figure 5 and 6).

The equivalent capacitance Cgd decreases as the drain source voltage applied increases.

Cds capacitance is the junction capacitance of the body-drain diode (“7” components in Figure 5 and 6). Its value varies as the p-body / n-drift junction thickness changes with the VDS applied, according to the following formula:

Equation 1

C ds ( VDS )

The relevant datasheets report the static equivalent capacitance values in the electrical characteristics as the following:

Equation 2
Ciss = Cgs C gd	measured @ VGS=0 V, VDS=25 V
Equation 3
Crss =Cgd	measured @ VGS=0 V, VDS=25 V
Equation 4
Coss = Cds Cgd	measured @ VGS=0 V, VDS=25 V

Cgd is also called “Miller capacitance”, as it’s placed in the feedback loop between the input and the output of the device. It's value can be much larger in switching operations, contributing to the achievement of a dynamic input capacitance of the MOSFET larger than the sum of the static capacitances.

In order to simplify the switching performance comparison among MOSFETs from different manufacturers or even different MOSFET technologies of the same brand, it can be useful to consider the gate charge parameters instead of capacitances. Figure 7 shows a clamped inductive load switching test circuit which helps to analyze the parasitic capacitance behavior during the MOSFET switching. The considerations reported in the following sections are valid if the driving source is supposed to provide any Ig current to the MOSFET input capacitances and the circuit is ideal with no stray inductances.

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Parasitic capacitances overview	AN3994

Figure 7. Clamped inductive load test circuit used to carry out the dynamic tests on the MOSFETs

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AN3994	MOSFET standard turn-on and turn-off analysis

3 MOSFET standard turn-on and turn-off analysis

The turn-on event of the MOSFET can be split into four time intervals, as Figure 8 shows. The analysis starts from the hypothesis of a constant load current IL flowing through the inductor L and the diode D before the commutation (turn-on) process.

After the MOSFET input has been connected to the voltage source (VSOURCE=VGM), the VGS voltage starts to increase (PHASE “1”), but no drain current can flow till the VGS

reaches the Vth value. The MOSFET is still in OFF state, while the diode is conducting the load current. The gate current IGon is charging the Ciss capacitance.

The ON gate current during the t0 to t2 time interval follows the exponential trend of

Equation 5:

Equation 5

					VGM	−	t
	I	,t	2 )	(t) =		e RGtotCiss
	Gon(t0				RGtot

RGtot theoretically includes the RGon value (see Figure 7) and the other resistive components of the driving circuit.

Equation 6 assumes that the Ciss (VDS) is constant during this time interval, which is a correct hypothesis, due to a very low dependence of the input capacitances on the VDS applied.

Phase “2” is the phase of ID rise. When VGS reaches the threshold value, ID begins to rise and at the same time, the load current begins to be shared between the diode and the MOSFET. Until the ID is lower than the load current and the diode is in an ON state, the VDS stays constant at the maximum value except for a little drop in the real voltage waveform due to the stray inductances along the switching circuit. The IGon current is still charging the Cgs+Cgd capacitances. At t2 instant the VGS reaches the plateau value.

The rate of ID current during the t1 to t2 time interval satisfies Equation 6:

Equation 6

dID = gmIGon(t1,t2 )

dt Ciss

During phase “3” and phase “4” VGS is at a constant value, ID has reached the full load condition and the diode is turned off. This enables the VDS to decrease. The MOSFET is in the active region and the IG current is now flowing only through the Cgd capacitance that’s discharging from a starting value of (VDS-VPL), while the Cds capacitance is discharging from VDS down to the VDS(on) value.

The ON gate current during the time interval (t2 to t4) is a fixed value and it satisfies

Equation 7:

Equation 7

IGon(t2 ,t4 ) = VGM − VPL

RGtot

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MOSFET standard turn-on and turn-off analysis	AN3994
Figure 8. Turn-on of a MOSFET in a clamped inductive load

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Figure 9. Equivalent capacitive model of a MOSFET

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Falling rate of VDS during the (t2 to t4) time interval is shown in Equation 8:

Equation 8

dV		IGon( t	,t	)		V	− V
DS	=	2	4		=	GM	PL
dt		Cgd				RGtot	Cgd

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AN3994	MOSFET standard turn-on and turn-off analysis

During phase “4” the voltage across the MOSFET has reached the ID*RDS(on)=VDS(on) value, and the device has entered the ohmic region. The VGS increases up to the maximum

value VGM.

Figure 10. Turn-off of a MOSFET in a clamped inductive load

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Similarly, the turn-off event can be split into four time intervals, as shown in Figure 10.

Phase “1” is the time interval needed to discharge the input capacitance Ciss from its initial value (+VGM) down to the plateau level. The gate current is supplied by both Cgs and Cgd capacitors.

The IGoff current during the time interval (t'0 to t'1) follows the same exponential trend of the turn-on during the (t0, t2) time interval according to Equation 9:

Equation 9

IGoff(t'0 ,t1' ) = −IGon(t0 ,t2 )

During phase “2” the gate voltage has reached a fixed value (the plateau level) and the VDS

rises from ID*RDS(on)=VDS(on) up to the final value, where it is clamped by the diode. As VGS is constant in this time interval, the OFF gate current flowing through the RGtot is the charging current of the Cgd that is charging from a negative starting voltage value (see

Figure 8 for reference) up to the VDS value, while the Cds capacitor is charging up to VDS.

IGoff current during this phase follows Equation 10:

Equation 10

IGoff(t' ,t' ) = VPL

1 3 R

Gtot

Phase “3” is the phase of the diode turn-on: load current begins to be shared between the MOSFET and the diode while the VGS decreases from the plateau down to the Vth value.

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MOSFET standard turn-on and turn-off analysis	AN3994

This causes the lowering of the drain current down to zero. During this time interval, the gate current is mainly coming from the Cgs capacitor.

IGoff current during this phase has the following expression:

Equation 11

							VPL	−	t−t	3'
	I	'	,t	'	)	(t) =		e RGtotCiss			t>t‘3
	Goff( t			4			RGtot
		3

During phase “4”, the Ciss fully discharges and the VGS reaches the zero value.

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AN3994	Gate charge curve impact on dynamic responses

4 Gate charge curve impact on dynamic responses

When generally dealing with MOSFET turn-on and turn-off, it implies the charging or discharging of its input capacitances. The charge transfer needed to change the voltage across these capacitors leads to unavoidable power losses which are dissipated on the gate resistors in the driving path during each switching cycle. A second but not less significant aspect is that the amount of charge directly impacts how fast the MOSFET response is during transients. For this reason, the gate charge curve analysis displayed in the datasheet is quite important in order to obtain a first outlook of the MOSFET dynamics.

As for the turn-on event, the Qth charge supplied during the t0 to t1 (Figure 8) time interval is approximately:

Equation 12

Qth = Ciss Vth

As VGS reaches the threshold value, Vth and ID start to flow. The charge to be provided

during the (t1 to t2) time interval can be calculated by integrating the IGon (t1 to t2) current as follows:

Equation 13

t	2	Vgm	−		t
				R		C
Q12 = ∫			e		GTOT		iss dt
		RGtot
t1
if we assume:
Equation 14
	t2 = t1 +				t

Equation 13 can be solved and the value of T can be calculated as:

Equation 15

t = t2 −t1 = −RGtot Ciss ln(1− Q12 )

Qth

The total charge supplied to the gate during the time interval (t2 to t3) can be easily calculated by multiplying the constant IGon value with the time interval (t2 to t3) as follows:

Equation 16

Q

23

=I

,t3 )

(t

3

− t

2

) =

VGM −VPL

(t

3

− t

2

)

Gon(t2

RGtot

Equation 17

t3 − t2	=	Q23			RGtot
		(V	−V )
		GM	PL

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Gate charge curve impact on dynamic responses	AN3994

Time intervals (t2 - t1) and (t3 - t2) theoretically calculated by Equation 5 and 17 are the two ones mainly involved in the turn-on event.

As similarly done for the turn-on, once the Q'23+Q'34 = Q23+Q12 (if referred to the turn-off, see Figure 10) portion of the gate charge has been read from the gate charge curve, the two time intervals (t'3 - t'2) and (t'4 - t'3) which are mainly involved in the turn-off event can be theoretically calculated as follows:

Equation 18

(t'3 − t'2) = Q'23 *RGtot

VPL

Equation 19

		'		'		Q'34
	(t	4	−t	3) = −RGtot	* Ciss * ln(1−		)
						VPL * Ciss

Time intervals of Equation 15, 17 and Equation 18, 19 have been calculated by assuming that the MOSFET works at Tj=25 °C. If the MOSFET is supposed to work in a real application, the Vth dependence ON temperature must be considered.

Having read the total gate charge Qg=Qth+Q12+Q23+Q34+Q4 (value at the VGM voltage level which is usually 10 V) (the curve VGS vs. Qg is displayed in the MOSFET datasheet), the total power loss needed to charge the gate is:

Equation 20

PGATE = Qg * VGM * fsw

So, by comparing the total gate charge of two MOSFETs, measured under the same test conditions of ID, VDS, IG, it is possible to understand which of them requires the lowest driving energy if the same VGM and fsw is considered.

Table 1 shows the total Qg values of four couples of MD V/MD II Power MOSFETs with

similar RDS(on). The Qg value of each device has been calculated from the VGS(t) curve of each device (see Figure 11 and 12 for reference) and measured on bench at the same ID

and VDS levels at Tc=25 °C. The newest MD V guarantees a lower Qg value than its equivalent MD II part, this leads to less effort in terms of driving energy requirements.

Table 1.	Experimentally measured Qg of four couples of MD V/MD II
Part number		RDS(on)max@10 V, 25°C	Qg@400 V, ID(A)
STP16N65M5		279 mΩ	28.4 nC@6 A
STP18NM60N		285 mΩ	31.2 nC@6 A
STP21N65M5		179 mΩ	40.4 nC@8 A
STP24NM60N		190 mΩ	42.3 nC@8 A
STP35N65M5		98 mΩ	77.4 nC@15 A
STB36NM60N		105 mΩ	80.1 nC@15 A
STB42N65M5		79 mΩ	96 nC@16 A
STW48NM60N		70 mΩ	122 nC@16 A

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