ST AN3988 Application note

AN3988

Application note

Clock configuration tool for STM32F40x/41x microcontrollers

Introduction

This application note presents the clock system configuration tool for the STM32F4xx microcontroller family.

The purpose of this tool is to help the user configure the microcontroller clocks, taking into consideration product parameters such as power supply and Flash access mode.

The configuration tool is implemented in the “STM32F4xx_Clock_Configuration_VX.Y.Z.xls” file which is supplied with the STM32F4xx Standard Peripherals Library and can be downloaded from www.st.com.

This tool supports the following functionalities for the STM32F4xx:

●Configuration of the system clock, HCLK source and output frequency

●Configuration of the Flash latency (number of wait states depending on the HCLK frequency).

●Setting of the PCLK1, PCLK2, TIMCLK (timer clocks), USBCLK, and I2SCLK frequencies.

●Generation of a ready-to-use system_stm32f4xx.c file with all the above settings (STM32F4xx CMSIS Cortex-M4 Device Peripheral Access Layer System Source File).

	The STM32F4xx_Clock_Configuration_VX.Y.Z.xls is referred to as “clock tool” throughout
	this document.
	Before using the clock tool, it is essential to read the STM32F4xx microcontroller reference
	manual (RM0090). This application note is not a substitute for the reference manual.
	This tool supports only revision A of the STM32F4xx.
Note:	For VX.Y.Z, please refer to the tool version, example V1.0.0

October 2011

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www.st.com

Contents	AN3988

Contents

1	Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
2	Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	2.1	Software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.2	Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.2 Clock scheme for STM32F4xx microcontrollers . . . . . . . . . . . . . . . . . . . 7 2.2.3 I2S clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3	Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	3.1 Wizard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

3.1.1 Step-by-step procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Expert mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4	Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
5	Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

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AN3988	List of tables

List of tables

Table 1. Definition of terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . . 9 Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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List of figures	AN3988

List of figures

Figure 1. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. Wizard mode user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. HSE value out of range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. VDD out of range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. HCLK error message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Select the clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. No possible configuration error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. File generation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10. Expert mode user interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. System clock frequency is exceeded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12. The PLL input frequency is exceeded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. The I2S frequency is out of range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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AN3988	Glossary

1 Glossary

Table 1.	Definition of terms
	Term	Description
HCLK		AHB clock
PCLK1		APB1 clock
PCLK2		APB2 clock
TIMCLK		Timer clock
USB OTG FS		USB on-the-go at full-speed
FCPU		Cortex-M4 clock
Ext.Clock		External clock
VDD		Power supply
HSI		High-speed internal clock
HSE		High-speed external clock
MCLK		Master clock
I2S		Integrated interchip sound
Fs		Sampling frequency
I2SCLK		I2S clock
RNG		Random number generator
SDIO		Secure digital input/output interface

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Getting started	AN3988

2 Getting started

This section describes the requirements and procedures needed to start using the clock tool.

2.1Software requirements

To use the clock tool with Windows operating system, a recent version of Windows®, such

as Windows XP, Vista or Windows 7 must be installed on the PC with at least

256 Mbytes of RAM.

Before starting to use the clock tool, make sure that Microsoft® Office is installed on your machine and then follow these steps:

	●	Download the latest version of the clock tool for the STM32F4xx product from
		www.st.com.
	●	Enable macros and ActiveX controls:
	Excel® 1997-2003 version
	1.	Click Tools in the menu bar
	2.	Click Macro
	3.	Click Security
	4.	Click Low (not recommended)
Note:	If ActiveX controls are not enabled, a warning message is displayed asking you to enable
	ActiveX. In this case, you should click “OK” to enable it.
	Excel 2007 version
	1.	Click the Microsoft Office button and then click Excel options.
	2.	Click Trust Center, click Trust center settings, and then click Macro settings.
	3.	Click Enable all macros (not recommended, potentially dangerous code can run).
	4.	Click Trust Center, click Trust center settings, and then click ActiveX settings.
	5.	Click Enable all controls without restrictions and without prompting (not
		recommended; potentiality dangerous controls can run).
	6.	Click OK.
Note:	For more information about how to enable macros and ActiveX controls please refer to the
	Microsoft Office website.

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AN3988	Getting started

2.2Hardware requirements

2.2.1Introduction

The clock tool is designed to configure the system clocks and generate the system_stm32f4xx.c file for STM32F4xx microcontrollers.

The system_stm32f4xx.c file is provided as a template system clock configuration file which can be easily modified to select the corresponding system clock frequency and to configure the Flash latency.

2.2.2Clock scheme for STM32F4xx microcontrollers

This section describes the system clock scheme that is dependent on the voltage requirements (VDD ) versus the system clock frequency and Flash latency versus the system clock frequency.

Three different clock sources can be used to drive the system clock (SYSCLK):

1.HSI (16 MHz) oscillator clock

2.HSE (4 MHz to 26 MHz) oscillator clock

3.Main phase-locked loop (PLL) clock with a PLL voltage-controlled oscillator (PLLVCO) input frequency which must be between1 and 2 MHz (2 MHz is recommended to limit the PLL jitter) and with division factors M, N, P, and Q.

All peripheral clocks are derived from the SYSCLK except for:

1.The USB OTG FS clock (48 MHz), the RNG clock (48 MHz), and the SDIO clock (48 MHz) which come from a specific output of PLL (PLL48CLK).

2.The I2S clock. To achieve high-quality audio performance, the I2S clock can be derived either from a specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin.

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