ST AN394 Application note

AN394

APPLICATION NOTE

MICROWIRE EEPROM COMMON I/O OPERATION

Within STMicroelectronics’ broad spectrum of different types of serial access EEPROM product, the MICROWIRE® family is based on a 4-wire interface. The four lines consist of: the Clock Input (C), the Chip Select Input (S), the Serial Data Input (D), and the Serial Data Output (Q).

Some microprocessor chips, such as ST’s microcontroller series, include an on-chip Serial Peripheral Interface (SPI). The MICROWIRE interface is ideally suited to use with these devices. However, the MICROWIRE EEPROM devices can also be used with any general purpose microcontroller, provided that care is taken not to allow signal conflicts to res ult. This document discusses how to avoid such conf licts when tying the D and Q lines together as a single bus.

While commands, addresses or data are being shifted into the D serial input of the EEPROM device, the Q output is h eld in t he high impedance state. It sho uld b e pos sibl e, th erefore, to tie the D and Q pi ns to gether to provide a common D/Q bus , as depic ted in Figu re 1. The dev ice can, indeed , opera te correctly in this configuration, provided that appropriate design rules are followed.

The potentially troublesome situations are during commands which activate the Q output (such as READ,WRITE, ERASE, WRAL and ERAL). This document considers these cases, and recommends the most conservative solution to each problem. In order to provide the designer with a safe design guide, all calculations are based on worst case values, as found in the data sheets for these EEPROM devices.

Figure 1. Typical Application of the Common-D/Q Approach

D Driver

Common D/Q Bus

Data In

Driver Enable

(active low)

Q Receiver

Data Out

Clock In

Chip Select In

EEPROM Device

D Q

Ai02419

READ INSTRUCTION

The D driver and the Q receiver, in Figure 1, can be discrete logic, or part of a microcontroller I/O port, or any equivalent circuit ry. The READ command and its address bits are clocked into the chi p, th rough the D pin, on the rising edges of the C clock. Each bit must be kept valid for a minimum hold time (tDVCH) as specified in the data sheet for the memory device. The device holds the Q pin in the high impedance state during most of the input operation. However, as Figure 2 shows, the Q pin is taken out of this state at the

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AN394 - APPLICATION NOTE

start of the last address bit (A0) of the instruction (signalle d by t he rising edge of C ), and starts to output the leading zero that precedes the 16-bit data string. The data sheets specify the maximum delay (tCHQL) between the rising edge of C and the leading zero data bit.

Figure 2. Timing Sequence for a Read Instruction

1 0 A5 A4 A3 A2 A1 A0

High Impedance

Bus Conflict

D15 D14 D13 D12 D11 D10 D9

Ai02420

Since the D driver must remain ena bled with the A0 bit for a minimum of tDVCH (t he hold time), a bus

conflict occurs whenever the A0 bit is a “1”, as it would be for all odd addressed registers). The consequences are:

– A low impedance path is created between Vcc and ground through the D driver and the on-chip Q output

buffer (as depicted in Figure 3). This short-circuit may produce glitches on the power supply which can disturb all the circuits on the board.

– The logic level on the D/Q bus is not well-defi ned: the potent ial divider chain, so created, can end up

producing a voltage level anywhere between Vcc and 0 V. Thus access to the odd addressed registers will probably be impossible.

Figure 3. Short-Circuit Created Between Vcc and Ground

D Driver

Common D/Q Bus

A0="1"

EEPROM Device

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Low Impedance Path

Output Buffer

Ai02424

AN394 - APPLICATION NOTE

This problem can be avoided by inserting a current limiting resistor in the current sink path. Figure 4 shows some possible locations for this resistor. However, the best location is between the Q output and the D/Q bus for the following reasons:

– During the overlap time, only the D driver is providing useful information. The Q driver simply outputs a

constant zero. By p lacing th e resist or i n this position, the D driver overrides t he Q driver at setting the logic level on the D/Q bus, thereby allowing the last address bit to be presented on the D p in for the specified hold time (tDVCH).

– The R resistor slows down the propagat ion time of the Q output signals on the D/Q bus, as discussed

later in this document. In this position, the resistor only slows down the transmission of the 16 bits of data during a READ operation. If R were in series with the D drive r, all operations would be slowed down.

Figure 4. Possible Locations for the Current Limiting Resistor

(If D driver is an open collector type)

Recommended

Location

EEPROM Device

Output Buffer

Ai02421

A0="1"

D Driver

Not Recommended

Locations

The R resistor does not have any effect as long as Q is in its high impedance state. During the execution of a READ instruc tion, R s in ks s ome current f rom th e D driver during the short overlap time. Then t he D driver is disabled and Q output takes control of the D/Q bus through the R resistor.

Because of the bus capacitance, C, the signals are distorted, as shown in Figure 5 (on the next page): the rising and falling edges of the Q output are transformed into exponential curves whose shape depends on the time constant RC.

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