ST AN3427 APPLICATION NOTE
1 Introduction
For designers of STM32 microcontroller applications, it is important to be able to easily
replace one microcontroller type by another one in the same product family. Migrating an
application to a different microcontroller is often needed, when product requirements grow,
putting extra demands on memory size, or increasing the number of I/Os. On the other
hand, cost reduction objectives may force you to switch to smaller components and shrink
the PCB area.
This application note is written to help you and analyze the steps you need to migrate from
an existing STM32F1 devices based design to STM32F2 devices. It groups together all the
most important information and lists the vital aspects that you need to address.
To migrate your application from STM32 F1 series to F2 series, you have to analyze the
hardware migration, the peripheral migration and the firmware migration.
AN3427
Application note
Migrating a microcontroller application
from STM32F1 to STM32F2 series
To benefit fully from the information in this application note, the user should be familiar with
the STM32 microcontroller family. Available from www.st.com.
● The STM32F1 family reference manuals (RM0008 and RM0041), the STM32F1
datasheets, and the STM32F1 Flash programming manuals (PM0075, PM0063 and
PM0068).
● The STM32F2 family reference manual (RM0033), the STM32F2 datasheets, and the
STM32F2 Flash programming manual (PM0059).
For an overview of the whole STM32 series and a comparision of the different features of
each STM32 product series, please refer to AN3364 'Migration and compatibility guidelines
for STM32 microcontroller applications'
July 2011 Doc ID 019001 Rev 1 1/52
www.st.com
Contents AN3427
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 32-bit multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 12
3.2.3 Dual SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 RCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6.1 Alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7 EXTI source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 PWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.11 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.12 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.12.1 Ethernet PHY interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.12.2 TIM2 internal trigger 1 (ITR1) remapping . . . . . . . . . . . . . . . . . . . . . . . 37
4 Firmware migration using the library . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1 Migration steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 RCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4.1 Output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4.2 Input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4.3 Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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AN3427 Contents
4.4.4 Alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5 EXTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.7 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.8 Backup data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.9.1 Ethernet PHY interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.9.2 TIM2 internal trigger 1 (ITR1) remapping . . . . . . . . . . . . . . . . . . . . . . . 50
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 019001 Rev 1 3/52
List of tables AN3427
List of tables
Table 1. STM32 F1 series and STM32 F2 series pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. STM32 peripheral compatibility analysis F1 versus F2 series . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. IP bus mapping differences between STM32 F1 and STM32 F2 series. . . . . . . . . . . . . . . 13
Table 4. RCC differences between STM32 F1 and STM32 F2 series . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Example of migrating system clock configuration code from F1 to F2 series . . . . . . . . . . . 20
Table 6. RCC registers used for peripheral access configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. DMA request differences between STM32 F1 series and STM32 F2 series . . . . . . . . . . . 23
Table 8. Interrupt vector differences between STM32 F1 series and STM32 F2 series . . . . . . . . . . 27
Table 9. GPIO differences between STM32 F1 series and STM32 F2 series . . . . . . . . . . . . . . . . . 30
Table 10. FLASH differences between STM32 F1 series and STM32 F2 series . . . . . . . . . . . . . . . . 32
Table 11. ADC differences between STM32 F1 series and STM32 F2 series . . . . . . . . . . . . . . . . . . 33
Table 12. PWR differences between STM32 F1 series and STM32 F2 series. . . . . . . . . . . . . . . . . . 35
Table 13. STM32F10x and STM32F2xx FLASH driver API correspondence . . . . . . . . . . . . . . . . . . . 41
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4/52 Doc ID 019001 Rev 1
AN3427 List of figures
List of figures
Figure 1. Compatible board design: LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Compatible board design: LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Compatible board design: LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. STM32 F2 series system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Doc ID 019001 Rev 1 5/52
Hardware migration AN3427
2 Hardware migration
All peripherals shares the same pins in the two families, but there are some minor
differences between packages.
In fact, the STM32 F2 series maintains a close compatibility with the whole STM32 F1
series. All functional pins are pin-to-pin compatible. The STM32 F2 series, however, are not
drop-in replacements for the STM32 F1 series: the two families do not have the same power
scheme, and so their power pins are different. Nonetheless, transition from the STM32 F1
series to the STM32 F2 series remains simple as only a few pins are impacted (impacted
pins are in bold in the table below).
Table 1. STM32 F1 series and STM32 F2 series pinout differences
QFP64 QFP100 QFP144 Pinout QFP64 QFP100 QFP144 Pinout
51223PD0 - OSC_IN 5 12 23 PH0 - O SC_ IN
61324PD1 - OSC_OUT 6 13 24 PH1 - O S C _ O U T
12 19 30 VSSA 19 30 VDD
STM32 F1 series STM32 F2 series
20 31 VREF- 12 20 31 VSSA
31 49 71 VSS_1 31 49 71 VCAP1
73 106 NC 47 73 106 VCAP2
47 74 107 VSS_2 74 107 VSS2
63 99 143 VSS_3 63 VSS_3
The figures below show examples of board designs that are compatible with both the F1 and
the F2 series.
6/52 Doc ID 019001 Rev 1
AN3427 Hardware migration
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Figure 1. Compatible board design: LQFP144
Figure 2. Compatible board design: LQFP100
Doc ID 019001 Rev 1 7/52
Hardware migration AN3427
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8/52 Doc ID 019001 Rev 1
AN3427 Peripheral migration
3 Peripheral migration
As shown in Table 2 on page 9, there are three categories of peripherals. The common
peripherals are supported with the dedicated firmware library without any modification,
except if the peripheral instance is no longer present, you can change the instance and of
course all the related features (clock configuration, pin configuration, interrupt/DMA
request).
The modified peripherals such as: FLASH, ADC, RCC, DMA, GPIO and RTC are different
from the F1 series ones and should be updated to take advantage of the enhancements and
the new features in F2 series.
All these modified peripherals in the F2 series are enhancements in performance and
features designed to meet new market requirements and to fix some limitations present in
the F1 series.
3.1 STM32 product cross-compatibility
The STM32 series embeds a set of peripherals which can be classed in three categories:
● The first category is for the peripherals which are by definition common to all products.
Those peripherals are identical, so they have the same structure, registers and control
bits. There is no need to perform any firmware change to keep the same functionality at
the application level after migration. All the features and behavior remain the same.
● The second category is for the peripherals which are shared by all products but have
only minor differences (in general to support new features), so migration from one
product to another is very easy and does not need any significant new development
effort.
● The third category is for peripherals which have been considerably changed from one
product to another (new architecture, new features...). For this category of peripherals,
migration will require new development at application level.
Ta bl e 2 below gives a general overview of this classification:
Table 2. STM32 peripheral compatibility analysis F1 versus F2 series
Peripheral F1 series F2 series
FSMC Yes Yes Same features Identical Full compatibility
WWDG
IWDG
DBGMCU
CRC
EXTI
CAN
Compatibility
Comments Pinout SW compatibility
Ye s Yes Same features NA Full compatibility
Ye s Yes Same features NA Full compatibility
Ye s Yes Same features NA Full compatibility
Ye s Yes Same features NA Full compatibility
Ye s Yes Same features Identical Full compatibility
Ye s Yes Same features Identical Full compatibility
Doc ID 019001 Rev 1 9/52
Peripheral migration AN3427
Table 2. STM32 peripheral compatibility analysis F1 versus F2 series (continued)
Compatibility
Peripheral F1 series F2 series
Comments Pinout SW compatibility
PWR Ye s Ye s + Enhancement NA
RCC
SPI
USART Ye s Ye s +
I2C
TIM
DAC
Ethernet
SDIO Ye s Ye s + Limitation fix Identical
USB OTG FS Ye s Ye s +
RTC
ADC
Ye s Ye s + Enhancement NA Partial compatibility
Ye s Ye s + TI mode / Max baudrate Identical
Limitation fix / Max baudrate /
One Sample Bit / Oversampling
by 8
Ye s Ye s + Limitation fix Identical
Ye s Ye s +
Ye s Ye s + DMA underrun interrupt Identical
Ye s Ye s +
Ye s Yes++ New peripheral
Ye s Yes++ New peripheral
32-bit Counter in TIM2 and
TIM5
IEEE1588 v2 / Enhanced DMA
descriptor
- Dynamic trimming capability of
SOF framing period in Host
mode
- Embeds a VBUS sensing
control
Identical
Identical
Identical
Identical
Identical for the
same feature
Identical for the
same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Full compatibility for
the same feature
Not compatible
Partial compatibility
FLASH
DMA
GPIO
CEC
USB FS
Device
Crypto/hash
processor
RNG
DCMI
10/52 Doc ID 019001 Rev 1
Ye s Yes++ New peripheral NA Not compatible
Ye s Yes++ New peripheral NA Not compatible
Ye s Yes++ New peripheral Identical Not compatible
Ye s NA NA NA NA
Ye s NA NA NA NA
NA Ye s NA NA NA
NA Ye s NA NA NA
NA Ye s NA NA NA
AN3427 Peripheral migration
Color key:
= New feature or new architecture (Yes++)
= Same feature, but specification change or enhancement (Yes+)
= Feature not available (NA)
Table 2. STM32 peripheral compatibility analysis F1 versus F2 series (continued)
Compatibility
Peripheral F1 series F2 series
Comments Pinout SW compatibility
USB OTG HS NA Ye s NA NA NA
SYSCFG
NA Ye s NA NA NA
Doc ID 019001 Rev 1 11/52
Peripheral migration AN3427
3.2 System architecture
STM32 F2 series are a new generation on STM32 with significant improvement in features
and performance with outstanding results: 150DMIPS at 120MHz and execution from Flash
equivalent to 0-wait state performance.
3.2.1 32-bit multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all masters (CPU, DMA controllers, Ethernet,
USB HS) and slaves (Flash memory, 2 blocks of RAM, FSMC, AHB and APB peripherals)
and ensures seamless and efficient operation even when several high-speed peripherals
are working simultaneously. For instance, the core can access the Flash through the ART
Accelerator and the 112-Kbyte SRAM, while the DMA2 controller is transferring data from
the camera interface located on the AHB2 peripheral bus to an LCD connected to the
FSMC, and while the USB OTG High Speed interface is storing received data in the 16Kbyte SRAM block.
Figure 4. STM32 F2 series system architecture
3.2.2 Adaptive real-time memory accelerator (ART Accelerator™)
To free the full performance of the Cortex-M3 core, ST has developed a leading-edge 90 nm
process and a unique technology, the adaptive real-time ART Accelerator™. To release the
processor full 150 DMIPS performance at this frequency, the accelerator implements an
instruction prefetch queue and branch cache which increases program execution speed
from the 128-bit Flash memory. Based on the CoreMark benchmark, the performance
achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from
Flash memory at a CPU frequency up to 120 MHz.
By default (after each device reset) the prefetch queue and branch cache are disabled, the
user can enable them using the PRFTEN, ICEN and DCEN bits in the FLASH_ACR register.
12/52 Doc ID 019001 Rev 1
AN3427 Peripheral migration
3.2.3 Dual SRAM
The 128KB of SRAM is made of 2 blocks; one 112KB and one 16KB. Both can be accessed
simultaneously by 2 masters in 0 WS (CPU, DMAs, Ethernet, USB HS).
The 16KB SRAM can be used as a buffer for high speed peripherals like USB-HS, Ethernet,
Camera, without impacting the CPU performance.
3.3 Memory mapping
The peripheral address mapping has been changed in the F2 series vs. F1 series, the main
change concerns the GPIOs which have been moved to the AHB bus instead of the APB
bus to allow them to operate at maximum speed.
The tables below provide the peripheral address mapping correspondence between F2 and
F1 series.
Table 3. IP bus mapping differences between STM32 F1 and STM32 F2 series
STM32 F2 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
FSMC Registers AHB3 0xA0000000 AHB 0xA0000000
RNG
0x50060800
NA NA
HASH 0x50060400
CRYP 0x50060000
DCMI 0x50050000
USB OTG FS 0x50000000 AHB 0x50000000
AHB2
NA NA
NA NA
NA NA
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Peripheral migration AN3427
Table 3. IP bus mapping differences between STM32 F1 and STM32 F2 series
STM32 F2 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
USB OTG HS
ETHERNET MAC 0x40028000
DMA2 0x40026400 0x40020400
DMA1 0x40026000 0x40020000
BKPSRAM 0x40024000
Flash interface 0x40023C00
RCC 0x40023800 0x40021000
CRC 0x40023000 0x40023000
GPIO I 0x40022000
GPIO H 0x40021C00
GPIO G 0x40021800
GPIO F 0x40021400 0x40011C00
GPIO E 0x40021000 0x40011800
GPIO D 0x40020C00 0x40011400
GPIO C 0x40020800 0x40011000
GPIO B 0x40020400 0x40010C00
GPIO A 0x40020000 0x40010800
TIM11
TIM10 0x40014400 0x40015000
TIM9 0x40014000 0x40014C00
EXTI 0x40013C00 0x40010400
AHB1
APB2
0x40040000 NA NA
0x40028000
AHB
NA NA
0x40022000
AHB
NA NA
NA NA
0x40012000
APB2
0x40014800 0x40015400
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AN3427 Peripheral migration
Table 3. IP bus mapping differences between STM32 F1 and STM32 F2 series
STM32 F2 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
SYSCFG
SPI1 0x40013000 APB2 0x40013000
SDIO 0x40012C00 AHB 0x40018000
ADC1 - ADC2 - ADC3 0x40012000 APB2
APB2
USART6 0x40011400
USART1 0x40011000
TIM8 0x40010400 0x40013400
TIM1 0x40010000 0x40012C00
DAC 0x40007400
PWR
CAN2 0x40006800 0x40006800
CAN1 0x40006400 0x40006400
I2C3 0x40005C00
I2C2 0x40005800
I2C1 0x40005400 0x40005400
UART5 0x40005000 0x40005000
UART4 0x40004C00 0x40004C00
0x40013800
0x40007000 0x40007000
NA NA
NA NA
APB2
APB1
NA NA
ADC3 - 0x40013C00
ADC2 - 0x40012800
ADC1 - 0x40012400
0x40013800
0x40007400
0x40005800
USART3 0x40004800 0x40004800
USART2 0x40004400 0x40004400
SPI3 / I2S3 0x40003C00 0x40003C00
SPI2 / I2S2 0x40003800 0x40003800
IWDG 0x40003000 0x40003000
WWDG 0x40002C00 0x40002C00
RTC
TIM14 0x40002000 0x40002000
TIM13 0x40001C00 0x40001C00
TIM12 0x40001800 0x40001800
TIM7 0x40001400 0x40001400
TIM6 0x40001000 0x40001000
TIM5 0x40000C00 0x40000C00
TIM4 0x40000800 0x40000800
APB1
APB1
0x40002800
(inc. BKP registers)
Doc ID 019001 Rev 1 15/52
0x40002800
Peripheral migration AN3427
Color key:
= Same feature, but base address change
= Feature not available (NA)
Table 3. IP bus mapping differences between STM32 F1 and STM32 F2 series
STM32 F2 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
TIM3
0x40000400
APB1
TIM2 0x40000000 0x40000000
APB1
BKP registers NA NA 0x40006C00
USB device FS
AFIO
NA NA 0x40005C00
NA NA APB2 0x40001000
3.4 RCC
The main differences related to the RCC (Reset and Clock Controller) in the STM32 F2
series vs. STM32 F1 series are presented in the table below.
Table 4. RCC differences between STM32 F1 and STM32 F2 series
RCC main
features
STM32 F1 series STM32 F2 series Comments
0x40000400
HSI 8 MHz RC factory-trimmed
LSI 40 KHz RC
16 MHz RC factory-trimmed
32 KHz RC
3 - 25 MHz
HSE
Depending on the product line
4 - 26MHz
used
LSE 32.768 KHz 32.768 kHz
No change to SW configuration:
– Enable/disable
RCC_CR[HSION]
– Status flag RCC_CR[HSIRDY]
No change to SW configuration:
– Enable/disable
RCC_CSR[LSION]
– Status flag
RCC_CSR[LSIRDY]
No change to SW configuration:
– Enable/disable
RCC_CR[HSEON]
– Status flag
RCC_CR[HSERDY]
No change to SW configuration:
– Enable/disable
RCC_BDCR[LSEON]
– Status flag
RCC_BDCR[LSERDY]
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