AN3424
Application note
STEVAL-ILL042V1: high power factor flyback LED driver
based on the L6562A and TSM101
Introduction
The high-PF flyback configuration, used to drive a new design of the 60 W LED array, is
based on the L6562A and the TSM101 controller (Figure 1).
This configuration uses an isolated feedback with an optocoupler and a secondary side
r e fe r e n c e/ e r ro r a m p l if i e r, t h e T S M 1 0 1, fo r vo l ta g e an d cu r r en t re g u la t i on .
T h e T S M 1 0 1 i n c l u d e s t w o o p a m p s : o n e o p a m p i s u s e d f o r c o n s t a n t v o l t a g e c o n t r o l
and the other for constant current control. A precise internal current generator, available,
can be used to offset the intervention threshold of the constant current regulation.
The L6562A is a PFC controller operating in transition-mode. The highly linear multiplier
includes a special circuit, able to reduce AC input current distortion, that allows wide-rangemains operation with an extremely low THD, even over a large load range.
The TSM101 compares the DC voltage and current level of a switching power supply to an
internal reference. It provides a feedback through an optocoupler to the L6562A controller in
the primary side.
This system, designed by using the L6562A and the TSM101 controller, offers more
advantages in terms of output current and voltage stability.
The input capacitance is so small here that the input voltage is very close to a rectified
sinewave. Besides, the control loop has a narrow bandwidth so as to be little sensitive to the
twice-mains frequency ripple appearing at the output.
Efficiency is high at heavy load, more than 90% is achievable: TM operation ensures slow
turn-on losses in the MOSFET and the high PF reduces dissipation in the bridge rectifier.
The output voltage exhibits a considerable twice-mains frequency ripple, unavoidable if a
high PF is desired. Speeding up the control loop may lead to a compromise between a
reasonably low output ripple and a reasonably high PF. To keep the ripple low, a large output
capacitance (in the thousand F) is anyway required.
Figure 1. Board image
November 2011 Doc ID 018991 Rev 1 1/22
www.st.com
Contents AN3424
Contents
1 Board block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Electrical schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Design and calculation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 EMC tests results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22 Doc ID 018991 Rev 1
AN3424 List of figures
List of figures
Figure 1. Board image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 60 W LED driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. High-PF flyback characteristic functions: F1(x) diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. High-PF flyback characteristic functions: F2(x) diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Flyback characteristic functions: F3(x) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. 60 W high-PF with L6562 and TSM101: electrical schematic. . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Pin vs. Vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. THD vs. Vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. PF vs. Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Efficiency vs. Vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Startup @ 230 V L6562A Vcc (red) MOSFET drain voltage (brown) . . . . . . . . . . . . . . . . . 15
Figure 13. Startup 230 V - Iout (green), Vout (blue), L6562A Vcc (red) . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Vin, Iin. PFC @ 185 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Vin, Iin. PFC @ 230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Vin, Iin. PFC @ 265 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Peak measure: line wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Peak measure: neutral wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 018991 Rev 1 3/22
Board block diagram AN3424
1 Board block diagram
Figure 2 shows a block diagram of the system. The complete circuit is made up of two
stages:
● The flyback converter which regulates the output voltage and performs the power factor
correction.
● The current and voltage controller stage which regulates the current and voltage output
feedback.
This topology, thanks to STMicroelectronics ICs L6265A and TSM101, realizes a high-PF
flyback converter with voltage and current output regulation.
Figure 2. 60 W LED driver block diagram
Filter
Mains
+
Bridge
LED
L6562A
TSM101
AM10530v1
4/22 Doc ID 018991 Rev 1
AN3424 Electrical schematic and bill of material
5
D5
1MOhm
5
D5
1MOhm
L6562AT
L6562AT
2 Electrical schematic and bill of material
Figure 3. Electrical schematic
J1
CON2
Vout=130 Vac, Iout=0.462A
1
2
R39
18 Ohm
C22
4.7 uF 160V
R37
R19
20 kOhm
68 kOhm
R32
68 kOhm
C13
100 nF
100 Ohm
C24
330uF, 160V
C10
330uF, 160V
R33
12 kOhm
R14
C9
12 kOhm
330uF, 160V
R16
12 kOhm
R15
C25
100 nF 25V
R41
10 kOhm
R42
D9
18V 0.5W
2 kOhm
C27
1uF 50V
D8
D7
TMMBAT46
R17
R43
R40
1.2 Ohm, 1%
1.2 Ohm, 1%
TMMBAT46
1.5 kOhm
C26
C16
2A 1000V
2
L3
2x47mH, 1.5A
F1
3
J3
T1
2.2n-Y1- 250V
2.2n-Y1- 250V
C20
2200nF- 630VDC
1
3
BR1
-+
4
C1B
100nF X2 Cap
43
12
C1A
100nF X2 Cap
FUSE 1A
1
2
CON3
C28
1uF 50V
Vref
VCC
1
8
Csense
Vrin
2
7
Crref
R18
15 kOhm
R38
10KOhm
C19
1uF
STTH2L06
12
10
9
TRAFO
2
4
3
D6
1.5KE350A
D1
C21
1n-Y1- 250V
7
6
D3
TMMBAT46
10 Ohm
R4
C18
100 nF, 50V
C15
STTH1L06
47uF, 35V
Q1
STP7N95K3
R35
D4
TMMBAT46
R29
R30
1 MOhm
R5
68 kOhm
R25
1.1Ohm 0.25W
R44
1.1Ohm 0.25W
R31
100 kOhm
100 kOhm
R34
C14
1nF 25V
R22
82 kOhm
R21
INV
1
0 Ohm
COMP
2
MULT
3
CS
4
C17
2.2nF
8.2 kOhm
R26
R27
1 MOhm
1 2
4 3
ISO1
OPTO ISOLATOR-A
R28
100 kOhm
R36
680k
VCC
8
GD
7
GND
6
ZCD
5
U3
R23
C23
150 pF 25V
Output
3
6
Gnd4Crin
5
U5
TSM101
R24
30 kOhm
2.2kOhm
R20
47kOhm
C29
1uF 50V
Vin=185 to 265 Vac
AM10531v1
Doc ID 018991 Rev 1 5/22
Electrical schematic and bill of material AN3424
Table 1. Bill of material
Reference Value Rated Type Manufacturer
BR1 2 A/1000 V
C1A, C1B 100 nF 275 Vac
C9, C10, C24 330 µF 160 Vdc Electrolytic capacitor
C13 100 nF 250 Vdc
C14 1 nF 25 Vdc
C15 47 µF 35 Vdc Electrolytic capacitor
C16, C26 2.2 nF 250 Vac Y1 capacitor
C17 2.2 nF
C18 100 nF 50 Vdc
C19, R38 220 nF, 100 kΩ
C20 220 nF 630 Vdc
C21 1 nF 250 Vac Y1 capacitor
C22 4.7 µF 160 Vdc Electrolytic capacitor
C23 150 pF 25 V Capacitor
C25 100 nF 25 Vdc
C27, C29 1 µF 50 Vdc Ceramic capacitor
Polypropylene film
capacitor X2
Polyester
capacitor
COG ceramic
capacitor
X7R ceramic
capacitor
X7R ceramic
capacitor
Polypropylene film
capacitor
X7R ceramic
capacitor
C28 10 nF 50 Vdc
D1 STTH1R06 1 A/600 V Ultrafast diode STMicroelectronics
D3, D4 TMMBAT 46 100 V STMicroelectronics
D5 STTH2L06 2 A/600 V Ultrafast diode STMicroelectronics
D6 1.5KE350A 350 V/1.5 kW Transil STMicroelectronics
D7, D8 TMMBAT 46 150 mA/100 V STMicroelectronics
D9 18 V/0.5 W Zener diode
F1 1 A/250 V Fuse
ISO1 PC817
J1 CON2
J3 CON3
L3 2 x 47 mH 1.1 A
6/22 Doc ID 018991 Rev 1
X7R ceramic
capacitor
OPTO
ISOLATOR-A
Common mode
choke
AN3424 Electrical schematic and bill of material
Table 1. Bill of material (continued)
Reference Value Rated Type Manufacturer
Q1 STP7N95K3 950 V/1.1 Ω SuperMESH™III STMicroelectronics
R4, R35 10 Ω 0.25 W
R5, R19, R32 68 kΩ 0.25 W, 1%
R14, R16, R33 12 kΩ 0.25 W
R15 100 Ω 0.25 W
R17 1.5 kΩ 0.25 W
R18 15 kΩ 0.25 W
R20 47 kΩ 0.25 W
R22 82 kΩ
R23 30 kΩ
R24 2.2 kΩ 1%
R25, R44 1.1 Ω 0.25 W, 1% Metal film resistor
R26, R29, R30 1 MΩ 0.25 W, 1%
R27 8.2 kΩ 0.25 W, 1%
R28, R31, R34 100 kΩ 0.25 W
R36 680 kΩ 0.25 W, 1%
R37 20 kΩ 0.25 W
R39 18 Ω 0.25 W
R40, R43 1.2 Ω 0.25 W, 1% Metal film resistor
R41 10 kΩ 1%
R42 2 kΩ 1%
T1 TRAFO 0.9 mH
U3 L6562A TM, PFC controller STMicroelectronics
U5 TSM101
Voltage and current
controller
STMicroelectronics
Doc ID 018991 Rev 1 7/22
Design and calculation parameters AN3424
3 Design and calculation parameters
Figure 4. High-PF flyback characteristic functions: F1(x) diagram
Figure 5. High-PF flyback characteristic functions: F2(x) diagram
The following is a step-by-step design of the L6562A-based high-PF flyback converter:
1. Design specifications:
– Mains voltage range: V
– Minimum mains frequency: f
– DC output voltage: V
out
= 185 Vac, V
ACmin
= 47 Hz
L
= 130 V
– Maximum output current: Iout = 0.462 A
– Maximum 2fL output ripple: ΔV
% = 1.0%
O
2. Pre-design choices:
– Minimum switching frequency: f
– Reflected voltage: V
= 195 V
R
SWmin
= 57 Kz
– Leakage inductance spike: Vspike; 100 V
– Expected efficiency: 92%
3. Preliminary calculations:
– Minimum input peak voltage: (4 V
total drop on R
8/22 Doc ID 018991 Rev 1
DS(ON, RS, …)
V
PKminVACmin
ACmax
= 265 Vac
2 185 2 4V–⋅=⋅ 257V==
AN3424 Design and calculation parameters
– Maximum input peak voltage:
– Maximum output power:
– Maximum input power:
– Peak-to-reflected voltage ratio:
P
V
PKmin
P
OUTVoutIout
P
out
= 10 0
in
η
K
100
V
60
92
V
V
V
ACmax
2 265 2 4V–⋅=⋅ 371V==
130 0.462⋅=⋅ 60W==
65.2W
=⋅=⋅
257
minPK
R
=1.32
==
195
– Characteristic functions value: F1(1.32) = 0.35, F2(1.32) = 0.24, F3(1.32) = 0.20
4. Operating conditions:
– Peak primary current: I
– RMS primary current: I
– Peak secondary current: I
– RMS secondary current: I
PKp
RMSp
PKs
RMSs
=
=
⋅
P2
in
⋅
I
PKp
=
⋅
⋅
=
)K(2FV
Vmi nPK
)K(2F
V
3
I2
out
=
)K(2FK
VV
KI
VPKs
⋅
2.652
=
11.2
⋅
462.02
⋅
)K(3F
V
3
=
24.06,257
24.0
3
=
2.11A
0.595A
=⋅=⋅
2.916A
32.1916.2
3
⋅
24.032.1
Figure 6. Flyback characteristic functions: F3(x) diagram
2.0
0.865A
=⋅⋅=⋅⋅
5. Primary inductance: Lp=
– Primary-to-secondary turns ratio:
– Minimum area product calculation:
Pmin
⎡
=
⎢
⎢
⎣
⋅
P460
in
⋅+⋅
Doc ID 018991 Rev 1 9/22
A
V
mi nPK
316.1
⎤
⎥
⎥
)K(2F)K1(f
VVminSW
⎦
=
⋅⋅+
If)K1(
PKpminSWV
V
n
R
=
⎡
=
⎢
⎢
⎣
=
+
)VV(
fout
3
6.257
3
195
+
⋅
2.65460
⋅+⋅⋅
=
11.21057)32.11(
⋅⋅⋅+
1.49
=
)6.0130(
316.1
⎤
⎥
24.0)32.11(1057
⎥
⎦
mH922.0
=0.363cm
4
Design and calculation parameters AN3424
This calculation highlights that the minimum AP required is about 0.36 cm4. An ETD34 core
(AP = 1.1175 cm
simultaneously L
4
) is used. This value of APmin reduces the number of turns N and
is reduced (leakage inductance) as reported in the following formulas:
lk
Equation 1
Ll
AAAAAP
=⋅=⋅=
weNminmin
⋅
e
N
⋅μ⋅μ
oe
so, with primary and secondary inductance in the transformer fixed, the AP
L
=
22
Nk
⋅
is inversely
min
proportional to the square of the turns N.
This reduces strongly the power dissipation in the clamp network by increasing the system
efficiency.
The ferrite used is N87, which guarantees low losses and high saturation.
Table 2. Gapped
Material g (mm) AL value approx. nH µ
0.20 ± 0.02
N87
0.50 ± 0.05
1.00 ± 0.05
In this specific design g =
≈1 mm, A
482
251
153
is the inductance referred to number of turns = 1:
L
310
161
98
e
Equation 2
where:
● µ
● A
, µ0 are respectively effective permeability and magnetic field constant
e
is effective magnetic cross section
e
Table 3. Calculation factors
Relationship between air
Material
N87 153 -0.713 240 -0.796 222 -0.873
gap - A
K1 (25 °C) K2 (25 °C) K3 (25 °C) K4 (25 °C) K3 (25 °C) K4 (25 °C)
value
L
Note: K1, K2:0.10 mm<s<2.50 mm.
K3, K4: 80 nH<A
<780 nH.
L
L
A
L
2
N
μ⋅μ
==
oe
l
e
A
e
Calculation of saturation current
10/22 Doc ID 018991 Rev 1
AN3424 Design and calculation parameters
6. MOSFET selection:
Maximum drain voltage: V
DSmax
= V
PKmax+VR
+ΔV = 372 + 195 + 100 = 667 V
There is some margin to select a 950 V device. This minimizes gate drive and
capacitive losses. Assuming that the MOSFET dissipates 5% of the input power, that
losses are due to conduction only, and that R
R
at 25 °C should be about 2 Ω. An STP7N95K3 (R
DS(on)
doubles at working temperature, the
DS(on)
1.35 Ω max.) in TO-220
DS(on)
Zener-protected SuperMESH3 is selected.
7. Catch diode selection:
V
Maximum drain voltage: .
V
maxREV
maxPK
V
n
out
371
493.1
378V
=+=+= 130
A suitable device is an STTH3L06, a TURBO 2 ultrafast high voltage rectifier with
I
= 3 A (minimum current rating is 1.166 A), V
F
= 600 V (V
RRM
RRM>VREVmax
).
From the relevant datasheet the power dissipation is estimated as:
Equation 3
2
IRIVP
RMSsthou tfout
=⋅+⋅=
0.89 0.462 0.055 0.8620.45W=⋅+⋅
This means , acceptable value.
T
jTambRthPout
75 75 0.45⋅+=⋅+ 108.75°C==
8. Output capacitor selection:
The minimum capacitance value that meets the specification on the 100/120 Hz ripple
is:
Equation 4
I
C
mi nout
1
=
f
⋅π
L
)K(2H
out
V
)K(2F
V
=
⋅⋅
V
Δ
o
462.0*
124.04714.3
⋅⋅⋅
F1025
μ=
Three 330 µF electrolytic capacitors have an ESR low enough (max. 446 mΩ) to consider
the high frequency ripple negligible as well as sufficient AC capability.
9. Clamp network:
With a proper construction technique, the leakage inductance can be reduced less than
1% of the primary inductance, which it is in the present case. A Transil clamp is
selected.
The clamp voltage is V
= VR+ΔV = 195 + 100 = 295 V. The steady-state power
CL
dissipation is estimated to be about 1 W. A 1.5KE350A Transil is selected. The blocking
diode is an STTH1L06.
10. Multiplier bias and sense resistor selection:
Assuming a peak value of 2.6 (@ V
peak value at minimum line voltage is V
= 265 V) on the multiplier input (MULT, 3) the
AC
185
--------- -
MULTpkmin
2.6
= which,
265
1.81V=⋅
multiplied by the maximum slope of the multiplier, 1, gives 1.81 V peak voltage on
current sense (CS, pin 4).
Since the linearity limit (3 V) is not exceeded, this is acceptable. The driver ratio is
then . Considering 260 µA for the divider, the lower resistor
2.6
-------------------------- 6.93 10
2265⋅()
3–
⋅=
Doc ID 018991 Rev 1 11/22
Design and calculation parameters AN3424
is 10 kΩ, and the upper one 1 MΩ. Choose the sense resistor 0.5 Ω, while its
power rating is .
PS0.5 I
2
RMSp
0.5 0.5952177m W=⋅=⋅=
11. Feedback and control loop:
The selected optocoupler is an ISO1-CNY-17.
The TSM101 is a voltage and current controller that regulates the output and current
voltage provided to the LED.
By considering V
V band-gap voltage reference, the V
= 130 V and that the value at pin 7 is compared to the internal 1.24
out
pin7
is:
Equation 5
VV
R
6
130
⋅=
out7pin
RR
+
76
⋅=
k5.1
k156k5.1
+
V24.1
=
with R6 = 1.5 kΩ, R7 = 156 kΩ.
= 0.6 Ω is the sense resistor used for current measurement. The current regulation
R
5
is effective when the voltage drop across it is equal to the voltage on pin 5 of TSM101.
For medium currents (<1 A), a voltage drop across R
R
can be realized with standard low cost 0.4 W resistors in parallel.
5
of 200 mV = VR5 is a good value,
5
Equation 6
V
R
5R
5
Ich
(two 1.2 Ω resistors in parallel)
Ω== 57.0
R2 and R3 can be chosen using the following formula:
Equation 7
⎛
⎜
RR
⋅=
32
⎜
⎝
Fixed R3 = 2 kΩ, we can have R2 = 10 kΩ.
⎞
VV
−
5Rref
⎟
V
⎟
5R
⎠
12/22 Doc ID 018991 Rev 1
AN3424 Design and calculation parameters
The complete electrical schematic of this application is illustrated in Figure 7.
Figure 7. 60 W high-PF with L6562 and TSM101: electrical schematic
Vout
2.2uF
18O
3x330uF
36kO
1.5KE350A
STTH1L06
10O
18kO
10O
100nF
47uF
18V
R7=156kO
0.5W
R5
2x1.2O
LL4148
LL4148
R6=1.5kO
5
3
8
TSM101
6
4
R2=10kO R3=2kO
1
7
47kO
68kO
100nF
1uF
0.5O
STP7N95K3
1N4148
1MO
2.2nF
100nF
+
Filter
Bridge
Mains
10O
10kO
3
7
4
150pF
L6562
8
2
300kO
1nF
750kO
65
1
0O
30kO
2.2kO
AM10535v1
Doc ID 018991 Rev 1 13/22
Design and calculation parameters AN3424
12. Experimental results:
These results have been obtained at input voltage between 185 and 265 V.
Ambient temperature: 23 °C
–V
–I
–P
= 118.7 V
OUT
= 358 mA
OUT
= 42.5 W
OUT
Figure 8. Pin vs. Vin
Figure 9. THD vs. Vin
14/22 Doc ID 018991 Rev 1
AN3424 Design and calculation parameters
Figure 10. PF vs. Vin
Figure 11. Efficiency vs. Vin
Figure 12. Startup @ 230 V L6562A Vcc (red) MOSFET drain voltage (brown)
Doc ID 018991 Rev 1 15/22
Design and calculation parameters AN3424
Figure 13. Startup 230 V - Iout (green), Vout (blue), L6562A Vcc (red)
Figure 14. Vin, Iin. PFC @ 185 V
Figure 15. Vin, Iin. PFC @ 230
16/22 Doc ID 018991 Rev 1
AN3424 Design and calculation parameters
Figure 16. Vin, Iin. PFC @ 265 V
Doc ID 018991 Rev 1 17/22
Thermal measurements AN3424
4 Thermal measurements
These measurements were performed at ambient temperature of 25 °C and at minimum
input voltage (185 V, worst case for PFC section).
Thermal measurement on the power device was performed on the board using infrared
thermocamera FLUKE.
For the PFC section, the temperature was measured on the power MOSFET and on the
diode.
On the power MOSFET with a mounted heatsink, having thermal resistance R
°C/W, the temperature on the top of the package was 40 °C. On the top of the Transil diode
the temperature was 35 °C, for the clamp diode 35 °C, for the IC driver 47 °C, and for the
output diode 55 °C.
= 11.40
th
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AN3424 EMC tests results
5 EMC tests results
EMC test was conducted according to the EN55015A standard.
The test was performed using the following apparatus:
● EMC ANALYZER Agilent E7401A
● LISN EMCO model 3825/2, 50 Ω, 10 kHz - 100 MHz.
The test was performed using peak detector and the limits of average and quasi peak of EN
55015A standard in the range 150 kHz - 30 MHz at 230 V 50 Hz input voltage.
Figure 17. Peak measure: line wire
In Figure 17 it is possible to observe that the conduced emissions are out of the limits in the
range 5 - 6 MHz.
Figure 18. Peak measure: neutral wire
Doc ID 018991 Rev 1 19/22
Conclusions AN3424
6 Conclusions
The high-PF flyback configuration used to drive a new design of the 60 W LED array and
based on the PFC L6562A and on the voltage and current TSM101 controller works
correctly in a single range [185 - 265] V. In the same range the efficiency is very high, more
than 92% (
Thermal measurements show that the power MOSFET reaches T = 40 °C.
Thanks to the TSM101, the system offers an excellent LED current regulation in terms of
current precision and works properly in all input conditions and output load, by offering high
performance with a simple and reliable design.
Figure 11).
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AN3424 Revision history
7 Revision history
Table 4. Document revision history
Date Revision Changes
08-Nov-2011 1 Initial release.
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AN3424
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