ST AN3422 APPLICATION NOTE

1 Introduction

For designers of STM32 microcontroller applications, it is important to be able to easily replace one microcontroller type by another one in the same product family. Migrating an application to a different microcontroller is often needed, when product requirements grow, putting extra demands on memory size, or increasing the number of I/Os. On the other hand, cost reduction objectives may force you to switch to smaller components and shrink the PCB area.

This application note is written to help you and analyze the steps you need to migrate from an existing STM32F1 devices based design to STM32L1 devices. It groups together all the most important information and lists the vital aspects that you need to address.

To migrate your application from STM32F1 series to STM32L1 series, you have to analyze the hardware migration, the peripheral migration and the firmware migration.

AN3422

Application note

Migration of microcontroller applications

from STM32F1 to STM32L1 series

To benefit fully from the information in this application note, the user should be familiar with the STM32 microcontroller family. You can refer to the following documents that are available from www.st.com.

● The STM32F1 family reference manuals (RM0008 and RM0041), the STM32F1

datasheets, and the STM32F1 Flash programming manuals (PM0075, PM0063 and PM0068).

● The STM32L1 family reference manual (RM0038), the STM32L1 datasheets, and the

STM32F1 Flash and EEPROM programming manual (PM0062).

For an overview of the whole STM32 series and a comparison of the different features of each STM32 product series, please refer to AN3364 Migration and compatibility guidelines for STM32 microcontroller applications.

March 2012 Doc ID 018976 Rev 2 1/52

www.st.com

Contents AN3422

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 STM32L1 family overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 RCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.7 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.8 EXTI source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.9 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.10 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.11 PWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.12 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5 Firmware migration using the library . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1 Migration steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2 RCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.1 Output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.2 Input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.3 Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.4 Alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.5 EXTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.6 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.7 PWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2/52 Doc ID 018976 Rev 2

AN3422 Contents

5.8 Backup data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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List of tables AN3422

List of tables

Table 1. STM32L1 peripherals compatibility analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. STM32F1 series and STM32L1 series pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. STM32 peripheral compatibility analysis F1 versus L1 series . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. IP bus mapping differences between STM32F1 and STM32L1 series. . . . . . . . . . . . . . . . 15

Table 5. RCC differences between STM32F1 and STM32L1 series . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Performance versus VCORE ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Example of migrating system clock configuration code from F1 to L1 . . . . . . . . . . . . . . . . 22

Table 8. RCC registers used for peripheral access configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 9. DMA request differences between STM32F1 series and STM32L1 series . . . . . . . . . . . . 24

Table 10. Interrupt vector differences between STM32F1 series and STM32L1 series. . . . . . . . . . . 26

Table 11. GPIO differences between STM32F1 series and STM32L1 series . . . . . . . . . . . . . . . . . . 29

Table 12. FLASH differences between STM32F1 series and STM32L1 series . . . . . . . . . . . . . . . . . 31

Table 13. ADC differences between STM32F1 series and STM32L1 series . . . . . . . . . . . . . . . . . . . 32

Table 14. PWR differences between STM32F1 series and STM32L1 series. . . . . . . . . . . . . . . . . . . 34

Table 15. STM32F10x and STM32L1xx FLASH driver API correspondence. . . . . . . . . . . . . . . . . . . 39

Table 16. STM32F10x and STM32L1xx PWR driver API correspondence . . . . . . . . . . . . . . . . . . . . 48

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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AN3422 List of figures

List of figures

Figure 1. Compatible board design: LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Compatible board design: LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3. Compatible board design: LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Compatible board design: LQFP48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Doc ID 018976 Rev 2 5/52

STM32L1 family overview AN3422

2 STM32L1 family overview

The STM32L1 platform forms a strong foundation with a broad and growing portfolio. With new products addressing new applications, the complete STM32L product series now comprises three series, STM32L1 Medium-density, STM32L1 Medium-density+ and STM32L1 High-density, all dedicated to ultra low power and low voltage applications.

● STM32L1: Designed for ultra-low-power applications that are energy-aware and seek

to achieve the absolute lowest power consumption. The L1 series maintains compatibility with the F1 series.

– Medium-density devices are STM32L151xx and STM32L152xx microcontrollers

where the Flash memory density ranges between 64 and 128 Kbyte

– Medium-density+ devices are STM32L151xx, STM32L152xx and STM32L162xx

microcontrollers where the Flash memory density is 256 Kbyte

– High-density devices are STM32L151xx, STM32L152xx and STM32L162xx

microcontrollers where the Flash memory density is 384 Kbyte

The ultralow power STM32L1 Medium-density, STM32L1 Medium-density+ and STM32L1 High-density are fully pin-to-pin, software and feature compatible.

Table 1. STM32L1 peripherals compatibility analysis

Peripheral

SPI

WWDG

IWDG

DBGMCU

CRC

EXTI

USB FS Device

DMA

TIM

SDIO

FSMC

PWR

Medium-

density

Ye s Ye s Ye s

Ye s Ye s Yes Same features

No No Yes Same features

Ye s Ye s Ye s Same features

Mediumdensity+

High-

density

No I2S in L1 Medium-density series

Compatibility

Comments

RCC

USART

6/52 Doc ID 018976 Rev 2

Ye s Ye s Ye s Same features

Ye s Ye s Ye s

Same features (UART4/5 are available only on High-density)

AN3422 STM32L1 family overview

Table 1. STM32L1 peripherals compatibility analysis (continued)

Peripheral

I2C Ye s Ye s Ye s Same features

DAC

ADC

RTC

FLASH

GPIO

LCD glass Ye s Ye s Ye s

COMP Ye s Ye s Ye s

SYSCFG Yes Yes Yes Same features

AES Yes Ye s Ye s

OPAMP Yes Yes Yes Same features

Medium-

density

Ye s Ye s Ye s Same features

Mediumdensity+

High-

density

Same features

Compatibility

Comments

Doc ID 018976 Rev 2 7/52

Hardware migration AN3422

3 Hardware migration

The ultralow power STM32L and general-purpose STM32F1xxx families are pin-to-pin compatible. All peripherals shares the same pins in the two families, but there are some minor differences between packages.

In fact, the STM32L1 series maintains a close compatibility with the whole STM32F1 series. All power and functional pins are pin-to-pin compatible. The transition from the STM32F1 series to the STM32L1 series is simple as only a few pins are impacted (impacted pins are in bold in the table below).

Table 2. STM32F1 series and STM32L1 series pinout differences

QFP48 QFP64 QFP100 QFP144 Pinout QFP48 QFP64 QFP100 QFP144 Pinout

5 5 12 23 PD0 - OSC_IN 5 5 12 23 PH0 - O S C _ I N

6 6 13 24 PD1 - OSC_OUT 6 6 13 24 PH1 - O S C _ O U T

11 6 6VBAT 11 6 6VLCD

- - 73 106 NC - - 73 106 PH2

STM32F1 series STM32L1 series

The figures below show examples of board designs that are compatible with both the F1 and the L1 series.

8/52 Doc ID 018976 Rev 2

AN3422 Hardware migration

Figure 1. Compatible board design: LQFP144

Doc ID 018976 Rev 2 9/52

Hardware migration AN3422

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Figure 2. Compatible board design: LQFP100

10/52 Doc ID 018976 Rev 2

AN3422 Hardware migration

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Figure 3. Compatible board design: LQFP64

Figure 4. Compatible board design: LQFP48

Doc ID 018976 Rev 2 11/52

Peripheral migration AN3422

4 Peripheral migration

As shown in Table 3 on page 13, there are three categories of peripherals. The common peripherals are supported with the dedicated firmware library without any modification, except if the peripheral instance is no longer present, you can change the instance and of course all the related features (clock configuration, pin configuration, interrupt/DMA request).

The modified peripherals such as: FLASH, ADC, RCC, PWR, GPIO and RTC are different from the F1 series ones and should be updated to take advantage of the enhancements and the new features in L1 series.

All these modified peripherals in the L1 series are enhanced to obtain lower power consumption, with features designed to meet new market requirements and to fix some limitations present in the F1 series.

4.1 STM32 product cross-compatibility

The STM32 series embeds a set of peripherals which can be classed in three categories:

● The first category is for the peripherals which are by definition common to all products.

Those peripherals are identical, so they have the same structure, registers and control bits. There is no need to perform any firmware change to keep the same functionality at the application level after migration. All the features and behavior remain the same.

● The second category is for the peripherals which are shared by all products but have

only minor differences (in general to support new features), so migration from one product to another is very easy and does not need any significant new development effort.

● The third category is for peripherals which have been considerably changed from one

product to another (new architecture, new features...). For this category of peripherals, migration will require new development at application level.

Ta bl e 3 gives a general overview of this classification.

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AN3422 Peripheral migration

Table 3. STM32 peripheral compatibility analysis F1 versus L1 series

Compatibility

Peripheral F1 series L1 series

Comments Pinout SW compatibility

No I2S in L1 Medium-density

SPI Ye s

Ye s

series

Identical Full compatibility

L1 vs. F1: limitation fix

WWDG

IWDG

DBGMCU

CRC

EXTI

USB FS Device

DMA

TIM

Ye s Yes Same features NA Full compatibility

Ye s Yes Same features Identical Full compatibility

Ye s Yes Same features NA Full compatibility

Ye s Yes Same features Identical Full compatibility

Same features (No SDIO in

SDIO

Ye s Ye s

L1 Medium-density and

Identical Full compatibility

Medium-density+ series)

Same features but only SRAM/NOR memories are

FSMC

Ye s Ye s

supported (No FSMC in L1

Identical Full compatibility Medium-density and Mediumdensity+ series)

PWR

RCC

Ye s Ye s + Enhancement NA

Ye s Ye s + Enhancement NA Partial compatibility

Full compatibility for the same feature

Limitation fix / One Sample

USART

I2C

DAC

ADC

RTC

Ye s Ye s +

Bit method / Oversampling by 8Identical Full compatibility

Ye s Ye s + Limitation fix Identical Full compatibility

Ye s Ye s + DMA underrun interrupt Identical Full compatibility

Ye s Yes++ New peripheral Identical Partial compatibility

Ye s Yes++ New peripheral

Identical for the

same feature

Not compatible

FLASH Ye s Yes++ New peripheral NA Not compatible

GPIO

CAN

Ye s Yes++ New peripheral Identical Not compatible

Ye s NA NA NA NA

Doc ID 018976 Rev 2 13/52

Peripheral migration AN3422

Color key:

= New feature or new architecture (Yes++)

= Same feature, but specification change or enhancement (Yes+)

= Feature not available (NA)

Table 3. STM32 peripheral compatibility analysis F1 versus L1 series (continued)

Compatibility

Peripheral F1 series L1 series

Comments Pinout SW compatibility

CEC Ye s NA NA NA NA

Ethernet

LCD glass

COMP

SYSCFG

AES

OPAMP

Ye s NA NA NA NA

NA Yes NA NA NA

4.2 System architecture

The STM32L MCU family, based on the Cortex-M3 core, extends ST’s ultra-low-power portfolio in performance, features, memory size and package pin count. It combines very high performance and ultra-low power consumption, through the use of an optimized architecture and ST’s proprietary ultra-low leakage process, that is also used in the STM8L family. The STM32L family offers three different product lines (STM32L Medium-density, STM32L Medium-density+ and STM32L High-density).

4.3 Memory mapping

The peripheral address mapping has been changed in the L1 series vs. F1 series, the main change concerns the GPIOs which have been moved from the APB bus to the AHB bus to allow them to operate at maximum speed.

The tables below provide the peripheral address mapping correspondence between L1 and F1 series.

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AN3422 Peripheral migration

Table 4. IP bus mapping differences between STM32F1 and STM32L1 series

STM32L1 series STM32F1 series

Peripheral

Bus Base address Bus Base address

FSMC

AES 0x50060000

DMA2 0x40026400

0xA0000000 AHB 0xA0000000

NA NA

0x40020400

DMA1 0x40026000 0x40020000

Flash Interface 0x40023C00 0x40022000

AHB

RCC 0x40023800 0x40021000

CRC 0x40023000

GPIOG 0x40021C00

AHB

0x40023000

0x40012000

APB2

GPIOF 0x40021800 0x40011C00

GPIOH 0x40021400

GPIOE 0x40021000

NA NA

0x40011800

GPIOD 0x40020C00 0x40011400

GPIOC 0x40020800 0x40011000

APB2

GPIOB 0x40020400 0x40010C00

GPIOA 0x40020000 0x40010800

USART1

0x40013800

APB2

SP1 0x40013000 0x40013000

SDIO 0x40012C00 AHB 0x40018000

ADC1 0x40012400

TIM11 0x40011000 0x40015400

TIM10 0x40010C00 0x40015000

APB2

0x40012400

TIM9 0x40010800 0x40014C00

EXTI 0x40010400 0x40010400

SYSCFG 0x40010000 NA NA

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Peripheral migration AN3422

Table 4. IP bus mapping differences between STM32F1 and STM32L1 series

STM32L1 series STM32F1 series

Peripheral

Bus Base address Bus Base address

OPAMP

COMP+RI 0x40007C00

DAC 0x40007400

PWR 0x40007000 0x40007000

USB device FS SRAM 0x40006000 0x40006000

USB device FS 0x40005C00 0x40005C00

I2C2 0x40005800 0x40005800

I2C1 0x40005400 0x40005400

UART5 0x40005000 0x40005000

UART4 0x40004C00 0x40004C00

USART3 0x40004800 0x40004800

USART2 0x40004400 0x40004400

SPI3 0x40003C00 0x40003C00

SPI2 0x40003800

IWDG 0x40003000 0x40003000

WWDG 0x40002C00 0x40002C00

RTC

APB1

0x40007C5C NA NA

NA NA

APB1

0x40002800

(inc. BKP registers)

0x40007400

0x40003800

0x40002800

LCD 0x40002400 NA NA

TIM7 0x40001400

TIM6 0x40001000 0x40001000

TIM5 0x40000C00 0x40000C00

TIM4 0x40000800 0x40000800

TIM3 0x40000400 0x40000400

TIM2 0x40000000 0x40000000

USB OTG FS

ETHERNET MAC

ADC2

ADC3

TIM8

TIM1

16/52 Doc ID 018976 Rev 2

NA NA

NA NA 0x40028000

NA NA

NA NA 0x40013C00

NA NA 0x40013400

NA NA 0x40012C00

0x40001400

APB1

0x50000000

AHB

0x40012800

APB2

AN3422 Peripheral migration

Color key:

= Same feature, but base address change

= Feature not available (NA)

Table 4. IP bus mapping differences between STM32F1 and STM32L1 series

STM32L1 series STM32F1 series

Peripheral

Bus Base address Bus Base address

CAN2 NA NA

CAN1

TIM14

TIM13

TIM12

TIM5

BKP registers

AFIO

NA NA 0x40006400

NA NA 0x40002000

NA NA 0x40001C00

NA NA 0x40001800

NA NA 0x40000C00

NA NA 0x40006C00

NA NA APB2 0x40010000

4.4 RCC

The main differences related to the RCC (Reset and Clock Controller) in the STM32L1 series vs. STM32F1 series are presented in the table below.

Table 5. RCC differences between STM32F1 and STM32L1 series

0x40006800

APB1

RCC main

features

MSI

STM32F1 series STM32L1 series Comments

HSI 8 MHz RC factory-trimmed

LSI 40 KHz RC

Multi Speed RC factorytrimmed (64 kHz /128 kHz / 256 kHz / 512 kHz / 1.02 MHz / 2.05 MHz / 4.1 MHz)

– Enable/disable

RCC_CR[MSION]

– Status flag RCC_CR[MSIRDY]

No change to SW configuration:

16 MHz RC factory-trimmed

– Enable/disable

RCC_CR[HSION]

– Status flag RCC_CR[HSIRDY]

No change to SW configuration: – Enable/disable

37 KHz RC

RCC_CSR[LSION]

– Status flag

RCC_CSR[LSIRDY]

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Peripheral migration AN3422

Table 5. RCC differences between STM32F1 and STM32L1 series (continued)

RCC main

features

HSE

LSE 32.768 kHz 32.768 kHz

PLL

System clock source

STM32F1 series STM32L1 series Comments

3 - 25 MHz Depending on the product line

used

– Connectivity line:

2 PLLs for I2S, Ethernet and OTG FS clock

– Other product lines:

PLL

HSI, HSE or PLL

main PLL +

main

1 - 24 MHz

– Main PLL for system

MSI, HSI, HSE or PLL

No change to SW configuration: – Enable/disable

RCC_CR[HSEON]

– Status flag

RCC_CR[HSERDY]

LSE configuration/status bits are now in RCC_CSR register.

– Enable/disable

RCC_CSR[LSEON]

– Status flag

RCC_CSR[LSERDY]

In L1 series the LSEON and LSERDY bits occupy bits RCC_CSR[9:8] respectively instead of bit RCC_BDCR[1:0] in F1 series.

There is no change to PLL enable/disable RCC_CR[PLLON] and status flag RCC_CR[PLLRDY].

However, PLL configuration (clock source selection, multiplication/division factors) are different. In L1 series dedicated bits RCC_CFGR[PLLDIV] are used to configure the PLL divider parameters and the PLL multiplication factors are different. The PLL sources are only HSI and HSE.

No change to SW configuration: – Selection bits

RCC_CFGR[SW] – Status flag RCC_CFGR[SWS] However there is one more

source, MSI, and the selection bit meanings are different.

System clock frequency

AHB frequency

18/52 Doc ID 018976 Rev 2

up to 72 MHz depending on the product line used

8 MHz after reset using HSI

up to 72 MHz

32 MHz 2 MHz after reset using MSI

up to 32 MHz

For STM32L1 Flash wait states should be adapted according to the system frequency, the product voltage range V and the supply voltage range VDD.

No change to SW configuration: configuration bits

RCC_CFGR[HPRE]

CORE

AN3422 Peripheral migration

Table 5. RCC differences between STM32F1 and STM32L1 series (continued)

RCC main

features

APB1 frequency

APB2 frequency

RTC clock source

MCO clock source

STM32F1 series STM32L1 series Comments

No change to SW configuration:

up to 36 MHz up to 32 MHz

up to 72 MHz

LSI, LSE or HSE/128

– MCO pin (PA8) – Connectivity Line:

PLL/2, SYSCLK, PLL2, PLL3 or XT1

– Other product lines:

HSE, PLL/2 or SYSCLK

HSI, HSE,

HSI,

up to 32 MHz

LSI, LSE or HSE clock divided by 2, 4, 8 or 16

–MCO pin (PA8): SYSCLK,

HSI, HSE, PLLCLK, MSI, LSE or LSI

With configurable prescaler, 1, 2, 4, 8 or 16 for each output.

configuration bits RCC_CFGR[PPRE1].

No change to SW configuration: configuration bits

RCC_CFGR[PPRE2].

RTC clock source configuration is done through the same bits (RTCSE[1:0] and RTCEN) but they are located in a different register.

In L1 series the RTCSEL[1:0] bits occupy bits RCC_CSR[17:16] instead of bits RCC_BDCR[9:8] in F1 series.

In L1 series the RTCEN bit occupies bit RCC_CSR[22] instead of bit RCC_BDCR[15] in F1 series.

However, in L1 series when HSE is selected as RTC clock source, additional bits are used in CR register, RCC_CR[RTCPRE], to select the division factor to be applied to HSE clock.

MCO configuration in L1 series is different from F1:

– For MCO, the prescaler is

configured through bits

RCC_CFGR[MCOPRE] and

the selection of the clock to

output through bits

RCC_CFGR[MCOSEL]

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Peripheral migration AN3422

Table 5. RCC differences between STM32F1 and STM32L1 series (continued)

RCC main

features

Internal

oscillator

measurement

/ calibration

Interrupt

STM32F1 series STM32L1 series Comments

– LSI connected to TIM10

CH1 IC: can measure LSI w/ respect to HSI/HSE clock

– LSE connected to TIM10

CH1 IC: can measure LSE

– LSI connected to TIM5 CH4

IC: can measure LSI w/ respect to HSI/HSE clock

– CSS (linked to NMI IRQ) – LSIRDY, LSERDY, HSIRDY,

HSERDY, PLLRDY,

PLL2RDY

(linked to RCC global IRQ)

and PLL3RDY

w/ respect to HSI/HSE clock

– HSE connected to TIM11

CH1 IC: can measure HSE w/ respect to LSE/HSI clock

– MSI connected to TIM11

CH1 IC: can measure MSI range w/ respect to HSI/HSE clock

– CSS (linked to IRQ) – LSIRDY, LSERDY,

MSIRDY, HSIRDY, HSERDY and PLLRDY (linked to RCC global IRQ)

There is no configuration to perform in RCC registers.

No change to SW configuration: interrupt enable, disable and pending bits clear are done in RCC_CIR register.

In addition to the differences described in the table above, the following additional adaptation steps may be needed for the migration:

Performance versus V

wait state depends on the selected voltage range V

ranges: The maximum system clock frequency and FLASH

CORE

and also on VDD. The

CORE

following table gives the different clock source frequencies depending on the product voltage range.

Table 6. Performance versus V

CPU

performance

High Low 1 1.8 32 16 2.0 - 3.6

Medium Medium 2 1.5 16 8

Low High 3 1.2 4 2

Power

performance

CORE

range

CORE

ranges

Typica l

Val ue ( V)

Max frequency

(MHz)

1 WS 0 WS

range

1.65 - 3.6

2. System clock configuration: when moving from F1 series to L1 series only a few settings need to be updated in the system clock configuration code; mainly the Flash settings (configure the right wait states for the system frequency, prefetch

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AN3422 Peripheral migration

enable/disable, 64-bit access enable/disable...) or/and the PLL parameters configuration:

a) If the HSE or HSI is used directly as system clock source, in this case only the

Flash parameters should be modified.

b) If PLL (clocked by HSE or HSI) is used as system clock source, in this case the

Flash parameters and PLL configuration need to be updated.

Ta bl e 7 below provides an example of porting a system clock configuration from F1 to L1

series:

– STM32F105/7 Connectivity Line running at maximum performance: system clock

at 72 MHz (PLL, clocked by the HSE, used as system clock source), Flash with 2 wait states and Flash prefetch queue enabled.

– L1 series running at maximum performance: system clock at 32 MHz (PLL,

clocked by the HSE, used as system clock source), Flash with 1 wait state, Flash prefetch and 64-bit access enabled.

As shown in the table below, only the Flash settings and PLL parameters (code in Bold Italic) need to be rewritten to run on L1 series. However, HSE, AHB prescaler and system clock source configuration are left unchanged, and APB prescalers are adapted to the maximum APB frequency in the L1 series.

Note: 1 The source code presented in the table below is intentionally simplified (time-out in wait loop

removed) and is based on the assumption that the RCC and Flash registers are at their reset values.

2 For STM32L1xx you can use the clock configuration tool,

STM32L1xx_Clock_Configuration.xls, to generate a customized system_stm32l1xx.c file containing a system clock configuration routine, depending on your application requirements. For more information, refer to AN3309 “Clock configuration tool for STM32L1xx microcontrollers”

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Peripheral migration AN3422

Table 7. Example of migrating system clock configuration code from F1 to L1

STM32F105/7 running at 72 MHz (PLL as clock

/* Enable HSE ----------------------------*/ RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */ while((RCC->CR & RCC_CR_HSERDY) == 0) { }

/* Flash configuration -------------------*/ /* Prefetch ON, Flash 2 wait states */ FLASH->ACR |= FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2;

/* AHB and APB prescaler configuration --*/ /* HCLK = SYSCLK */ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

/* PLL configuration -------------------*/ /* PLL2CLK = (HSE / 5) * 8 = 40 MHz PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 |= RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5; /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLLCLK = PREDIV1 * 9 = 72 MHz */ RCC->CFGR |= RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9;

/* Enable the main PLL */

RCC->CR |= RCC_CR_PLLON; /* Wait till the main PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { }

/* Main PLL used as system clock source --*/ RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {

}

source) with 2 wait states

STM32L1xx running at 22 MHz (PLL as clock source)

with 1 wait state

/* Enable HSE ----------------------------*/ RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */ while((RCC->CR & RCC_CR_HSERDY) == 0) { }

/* Flash configuration -------------------*/ /* Flash prefetch and 64-bit access ON, Flash 1 wait state */ FLASH->ACR |= FLASH_ACR_ACC64;

FLASH->ACR |= FLASH_ACR_PRFTEN;

FLASH->ACR |= FLASH_ACR_LATENCY;

/* Power enable */ RCC->APB1ENR |= RCC_APB1ENR_PWREN;

/* Select the Voltage Range 1 (1.8 V) */ PWR->CR = PWR_CR_VOS_0;

/* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != RESET) { }

/* AHB and APB prescaler configuration --*/ /* HCLK = SYSCLK */ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK / 1*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK / 1*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV1;

/* PLL configuration ---------------------*/ /* PLLCLK = (HSE * PLL_MUL) / PLL_DIV = (8 MHz * 12) / 3 = 32MHz */ RCC->CFGR = RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3;

/* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till the main PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { }

/* Main PLL used as system clock source --*/ RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ while ((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); {

}

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AN3422 Peripheral migration

3. Peripheral access configuration: since the address mapping of some peripherals has been changed in L1 series vs. F1 series, you need to use different registers to [enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode].

Table 8. RCC registers used for peripheral access configuration

Bus Register Comments

RCC_AHBRSTR Used to [enter/exit] the AHB peripheral from reset

AHB

APB1

APB2

RCC_AHBENR Used to [enable/disable] the AHB peripheral clock

RCC_AHBLPENR

RCC_APB1RSTR Used to [enter/exit] the APB1 peripheral from reset

RCC_APB1ENR Used to [enable/disable] the APB1 peripheral clock

RCC_APB1LPENR

RCC_APB2RSTR Used to [enter/exit] the APB2 peripheral from reset

RCC_APB2ENR Used to [enable/disable] the APB2 peripheral clock

RCC_APB2LPENR

Used to [enable/disable] the AHB peripheral clock in low power Sleep mode

Used to [enable/disable] the APB1 peripheral clock in low power Sleep mode

Used to [enable/disable] the APB2 peripheral clock in low power Sleep mode

To configure the access to a given peripheral you have first to know to which bus this peripheral is connected, refer to Table 4 on page 15, then depending on the action needed you have to program the right register as described in Ta b le 8 above. For example, USART1 is connected to APB2 bus, to enable the USART1 clock you have to configure APB2ENR register as follows:

RCC->APB2ENR |= RCC_APB2ENR_USART1EN;

to disable USART1 clock during Sleep mode (to reduce power consumption) you have to configure APB2LPENR register as follows:

RCC->APB2LPENR |= RCC_APB2LPENR_USART1LPEN;

4. Peripheral clock configuration: some peripherals have a dedicated clock source independent from the system clock, and used to generate the clock required for their operation:

a) USB

: The USB 48 MHz clock is derived from the PLL VCO clock which should be

at 96MHz

b) SIDO

: The SDIO clock (SDIOCLK) is derived from the PLL VCO clock and is equal

to PLLVCO / 2

c) LCD:

d) ADC:

The LCD Glass clock shares the same clock source as the RTC

in STM32L1 series the ADC features two clock schemes:

– Clock for the analog circuitry: ADCCLK. This clock is always the HSI oscillator

clock. A divider by 1, 2 or 4 allows to adapt the clock frequency to the device operating conditions. This configuration is done using ADC_CCR[ADCPRE] bits. The ADC Clock depends also on the voltage range V

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. When product voltage

CORE

Peripheral migration AN3422

range 3 is selected (V

= 1.2 V), the ADC is low speed (ADCCLK = 4 MHz,

CORE

250 Ksps).

– Clock for the digital interface (used for register read/write access). This clock is the

APB2 clock. The digital interface clock can be enabled/disabled through the RCC_APB2ENR register (ADC1EN bit) and there is a bit to reset the ADC through RCC_APB2RSTR[ADCRST] bit.

4.5 DMA

STM32F1 and STM32L1 series uses the same DMA controller fully compatible.

STM32F1 and STM32L1 series embeds two DMA controllers, each controller has up to 7 channels. Each channel is dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.

The table below presents the correspondence between the DMA requests of the peripherals in STM32F1 series and STM32L1 series.

Table 9. DMA request differences between STM32F1 series and STM32L1 series

Peripheral DMA request STM32F1 series STM32L1 series

ADC1 ADC1 DMA1_Channel1 DMA1_Channel1

ADC2 ADC2

NA NA

ADC3 ADC3 DMA2_Channel5

DAC

SPI1

SPI2

SPI3

USART1

USART2

USART3

UART4

UART5

I2C1

DAC_Channel1 DAC_Channel2

SPI1_Rx SPI1_Tx

SPI2_Rx SPI2_Tx

SPI3_Rx SPI3_Tx

USART1_Rx USART1_Tx

USART2_Rx USART2_Tx

USART3_Rx USART3_Tx

UART4_Rx UART4_Tx

UART5_Rx UART5_Tx

I2C1_Rx I2C1_Tx

DMA2_Channel3 / DMA1_Channel3 DMA2_Channel4 / DMA1_Channel4

DMA1_Channel2 DMA1_Channel3

DMA1_Channel4 DMA1_Channel5

DMA2_Channel1 DMA2_Channel2

DMA1_Channel5 DMA1_Channel4

DMA1_Channel6 DMA1_Channel7

DMA1_Channel3 DMA1_Channel2

DMA2_Channel3 DMA2_Channel5

DMA2_Channel4 DMA2_Channel1

DMA1_Channel7 DMA1_Channel6

(1)

DMA1_Channel2

(1)

DMA1_Channel3

DMA1_Channel2 DMA1_Channel3

DMA1_Channel4 DMA1_Channel5

DMA2_Channel1 DMA2_Channel2

DMA1_Channel5 DMA1_Channel4

DMA1_Channel6 DMA1_Channel7

DMA1_Channel3 DMA1_Channel2

DMA2_Channel3 DMA2_Channel5

DMA2_Channel2 DMA2_Channel1

DMA1_Channel7 DMA1_Channel6

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AN3422 Peripheral migration

Table 9. DMA request differences between STM32F1 series and STM32L1 series (continued)

Peripheral DMA request STM32F1 series STM32L1 series

I2C2

I2C2_Rx I2C2_Tx

DMA1_Channel5 DMA1_Channel4

SDIO SDIO DMA2_Channel4 DMA2_Channel4

TIM1

TIM8

TIM2

TIM1_UP TIM1_CH1 TIM1_CH2 TIM1_CH3 TIM1_CH4 TIM1_TRIG TIM1_COM

TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 TIM8_CH4 TIM8_TRIG TIM8_COM

TIM2_UP TIM2_CH1 TIM2_CH2 TIM2_CH3 TIM2_CH4

DMA1_Channel5 DMA1_Channel2 DMA1_Channel3 DMA1_Channel6 DMA1_Channel4 DMA1_Channel4 DMA1_Channel4

DMA2_Channel1 DMA2_Channel3 DMA2_Channel5 DMA2_Channel1 DMA2_Channel2 DMA2_Channel2 DMA2_Channel2

DMA1_Channel2 DMA1_Channel5 DMA1_Channel7 DMA1_Channel1 DMA1_Channel7

TIM3

TIM4

TIM5

TIM3_UP TIM3_CH1 TIM3_TRIG TIM3_CH3 TIM3_CH4

TIM4_UP TIM4_CH1 TIM4_CH2 TIM4_CH3

TIM5_UP TIM5_CH1 TIM5_CH2 TIM5_CH3 TIM5_CH4 TIM5_TRIG TIM5_COM

DMA1_Channel3 DMA1_Channel6 DMA1_Channel6 DMA1_Channel2 DMA1_Channel3

DMA1_Channel7 DMA1_Channel1 DMA1_Channel4 DMA1_Channel5

DMA2_Channel2 DMA2_Channel5 DMA2_Channel4 DMA2_Channel2 DMA2_Channel1 DMA2_Channel1 NA

TIM6 TIM6_UP DMA2_Channel3 / DMA1_Channel3

TIM7 TIM7_UP DMA2_Channe4 / DMA1_Channel4

DMA1_Channel3 DMA1_Channel6 DMA1_Channel6 DMA1_Channel2 DMA1_Channel3

DMA1_Channel7 DMA1_Channel1 DMA1_Channel4 DMA1_Channel5

DMA2_Channel2 DMA2_Channel5 DMA2_Channel4 DMA2_Channel2 DMA2_Channel1 DMA2_Channel1 DMA2_Channel1

(1)

DMA1_Channel2

(1)

DMA1_Channel3

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Peripheral migration AN3422

Table 9. DMA request differences between STM32F1 series and STM32L1 series (continued)

Peripheral DMA request STM32F1 series STM32L1 series

TIM15_UP

TIM15

TIM16

TIM17

AES

1. For High-density value line devices, the DAC DMA requests are mapped respectively on DMA1 Channel 3 and DMA1 Channel 4

TIM15_CH1 TIM15_TRIG TIM15_COM

TIM16_UP TIM16_CH1

TIM17_UP TIM17_CH1

AES_OUT AES_IN

DMA1_Channel5 DMA1_Channel5 DMA1_Channel5 DMA1_Channel5

DMA1_Channel6 DMA1_Channel6

DMA1_Channel7 DMA1_Channel7

DMA2_Channel3 DMA2_Channel5

4.6 Interrupts

The table below presents the interrupt vectors in STM32L1 series vs. STM32F1 series.

The changes in the interrupt vectors impact only a few peripherals:

1. ADC: in the F1 series there are two interrupt vectors for the ADCs; ADC1_2 and ADC3. However in L1 series there is a single interrupt vector for ADC1; ADC1_IRQ.

2. As in STM32L1 series there are no CAN or TIM1 peripherals, their corresponding IRQs are now mapped to new peripherals: COMP, DAC, TIM9, TIM10, TIM11 and LCD.

Table 10. Interrupt vector differences between STM32F1 series and STM32L1 series

Position STM32F1 series STM32L1 series

0 WWDG WWDG

1 PVD PVD

2 TAMPER TAMPER_ STAMP

3RTC

4 FLASH FLASH

5RCC RCC

6 EXTI0 EXTI0

7 EXTI1 EXTI1

8 EXTI2 EXTI2

9 EXTI3 EXTI3

10 EXTI4 EXTI4

11 DMA1_Channel1 DMA1_Channel1

12 DMA1_Channel2 DMA1_Channel2

13 DMA1_Channel3 DMA1_Channel3

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RTC_WKUP

AN3422 Peripheral migration

Table 10. Interrupt vector differences between STM32F1 series and STM32L1 series

(continued)

Position STM32F1 series STM32L1 series

14 DMA1_Channel4 DMA1_Channel4

15 DMA1_Channel5 DMA1_Channel5

16 DMA1_Channel6 DMA1_Channel6

17 DMA1_Channel7 DMA1_Channel7

18 ADC1_2

CAN1_TX / USB_HP_CAN_TX (

CAN1_RX0 / USB_LP_CAN_RX0

21 CAN1_RX1

22 CAN1_SCE

(1)

ADC1

USB_HP

USB_LP

DAC

COMP

23 EXTI9_5 EXTI9_5

(1)

TIM9

TIM10

TIM11

24 TIM1_BRK / TIM1_BRK _TIM9

25 TIM1_UP / TIM1_UP_TIM10

TIM1_TRG_COM / TIM1_TRG_COM_TIM11

27 TIM1_CC LCD

28 TIM2 TIM2

29 TIM3 TIM3

30 TIM4 TIM4

31 I2C1_EV I2C1_EV

32 I2C1_ER I2C1_ER

33 I2C2_EV I2C2_EV

34 I2C2_ER I2C2_ER

35 SPI1 SPI1

36 SPI2 SPI2

37 USART1 USART1

38 USART2 USART2

39 USART3 USART3

40 EXTI15_10 EXTI15_10

41 RTC_Alarm RTC_Alarm

42 OTG_FS_WKUP / USBWakeUp

TIM8_BRK / TIM8_BRK_TIM12

TIM8_UP / TIM8_UP_TIM13

TIM8_TRG_COM / TIM8_TRG_COM_TIM14

(1)

USB_FS_WKUP

TIM6

TIM7

SDIO

46 TIM8_CC TIM5

Doc ID 018976 Rev 2 27/52

Peripheral migration AN3422

Color key:

= Different Interrupt vector

= Interrupt Vector name changed but F1 peripheral still mapped on the same Interrupt Vector position in L1 series

= Feature not available (NA)

Table 10. Interrupt vector differences between STM32F1 series and STM32L1 series

(continued)

Position STM32F1 series STM32L1 series

47 ADC3 SPI3

48 FSMC

49 SDIO

50 TIM5

51 SPI3

52 UART4

53 UART5

54 TIM6 / TIM6_DAC

(1)

55 TIM7

56 DMA2_Channel1

57 DMA2_Channel2

58 DMA2_Channel3

DMA2_Channel4 / DMA2_Channel4_5

DMA2_Channel5 NA

ETH NA

ETH_WKUP NA

CAN2_TX NA

CAN2_RX0 NA

CAN2_RX1 NA

CAN2_SCE NA

OTG_FS NA

(1)

UART4

UART5

DMA2_Channel1

DMA2_Channel2

DMA2_Channel3

DMA2_Channel4

DMA2_Channel5

AES

COMP_ACQ

1. Depending on the product line used.

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AN3422 Peripheral migration

4.7 GPIO

The STM32L1 GPIO peripheral embeds new features compared to F1 series, below the main features:

● GPIO mapped on AHB bus for better performance

● I/O pin multiplexer and mapping: pins are connected to on-chip peripherals/modules

through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.

● More possibilities and features for I/O configuration

The L1 GPIO peripheral is a new design and thus the architecture, features and registers are different from the GPIO peripheral in the F1 series, so any code written for the F1 series using the GPIO needs to be rewritten to run on L1 series.

For more information about STM32L1’s GPIO programming and usage, please refer to the "I/O pin multiplexer and mapping" section in the GPIO chapter of the STM32L1xx Reference Manual (RM0038).

The table below presents the differences between GPIOs in the STM32F1 series and STM32L1 series.

Table 11. GPIO differences between STM32F1 series and STM32L1 series

GPIO STM32F1 series STM32L1 series

Floating

Input mode

General purpose

output

Alternate Function

output

Input / Output Analog Analog

Output speed

PU PD

PP OD

2 MHz 10 MHz 50 MHz

Floating PU PD

PP PP + PU PP + PD OD OD + PU OD + PD

400KHz 2 MHz 10 MHz 40 MHz

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Peripheral migration AN3422

Table 11. GPIO differences between STM32F1 series and STM32L1 series (continued)

GPIO STM32F1 series STM32L1 series

To optimize the number of peripheral I/O

Alternate function selection

Max IO toggle frequency 18 MHz 16 MHz

functions for different device packages, it is possible to remap some alternate functions to some other pins (software remap).

Highly flexible pin multiplexing allows no conflict between peripherals sharing the same I/O pin.

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AN3422 Peripheral migration

Alternate function mode

In STM32F1 series

1. The configuration to use an I/O as alternate function depends on the peripheral mode used, for example the USART Tx pin should be configured as alternate function pushpull while USART Rx pin should be configured as input floating or input pull-up.

2. To optimize the number of peripheral I/O functions for different device packages (especially with those with low pin count), it is possible to remap some alternate functions to other pins by software, for example the USART2_RX pin can be mapped on PA3 (default remap) or PD6 (by software remap).

In STM32L1 series

1. Whatever the peripheral mode used, the I/O must be configured as alternate function, then the system can use the I/O in the proper way (input or output).

2. The I/O pins are connected to on-chip peripherals/modules through a multiplexer that allows only one peripheral’s alternate function to be connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL and GPIOx_AFRH registers:

– After reset all I/Os are connected to the system’s alternate function 0 (AF0)

– The peripheral alternate functions are mapped by configuring AF1 to AF13

– Cortex-M3 EVENTOUT is mapped by configuring AF15

3. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped on different I/O pins to optimize the number of peripheral I/O functions for different device packages, for example the USART2_RX pin can be mapped on PA3 or PD6 pin

Note: Please refer to the “Alternate function mapping” table in the STM32L15x datasheet for the

detailed mapping of the system and the peripheral alternate function I/O pins.

4. Configuration procedure

– Configure the desired I/O as an alternate function in the GPIOx_MODER register

– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively

– Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

4.8 EXTI source selection

In STM32F1 the selection of EXTI line source is performed through EXTIx bits in AFIO_EXTICRx registers, while in L1 series this selection is done through EXTIx bits in SYSCFG_EXTICRx registers.

Only the mapping of the EXTICRx registers has been changed, without any changes to the meaning of the EXTIx bits. However, the maximum range of EXTIx bits values is 0b0101 as only 6 GPIO ports are supported in L1 (in F1 series the maximum value is 0b0110).

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Peripheral migration AN3422

4.9 FLASH

The table below presents the difference between the FLASH interface of STM32F1 series and STM32L1 series, which can be grouped as follows:

● New interface, new technology

● New architecture

● New read protection mechanism, 3 read protection levels with JTAG fuse

Consequently the L1 Flash programming procedures and registers are different from the F1 series, and any code written for the Flash interface in the F1 series needs to be rewritten to run on L1 series.

For more information on programming, erasing and protection of the L1 Flash memory, please refer to the STM32L1xx Flash programming manual (PM0062).

Table 12. FLASH differences between STM32F1 series and STM32L1 series

Feature STM32F1 series STM32L1 series

Wait State up to 2

Start Address 0x0800 0000 0x0800 0000

Main/Program

memory

EEPROM memory

System memory

Option Bytes

OTP

End Address up to 0x080F FFFF up to 0x0805 FFFF

Page size = 2 Kbytes

Granularity

Start Address

End Address

Start Address 0x1FFF F000

End Address 0x1FFF F7FF

Start Address 0x1FFF F800

End Address 0x1FFF F80F

Start Address

End Address

Start address 0x4002 2000

except for Low and Medium density page size = 1 Kbytes

Available through SW emulation

(1)

NA NA

up to 1 (depending on the supply voltage)

Sector size = 4 Kbytes: 16 Pages of 256 bytes

0x0808 0000

0x0808 2FFF

0x1FF0 0000

0x1FF0 1FFF

0x1FF8 0000/0x1FF8 0080

0x1FF8001F/0x1FF8 009F

0x4002 3C00

Flash interface

Erase granularity Page (1 or 2 Kbytes)

32/52 Doc ID 018976 Rev 2

Programming

procedure

Same for all product lines

Different from F1 series

Program memory: Page (256 bytes)

DATA EEPROM memory: halfword/ word / double word

byte/

AN3422 Peripheral migration

Color key:

= New feature or new architecture

= Same feature, but specification change or enhancement

= Feature not available (NA)

Table 12. FLASH differences between STM32F1 series and STM32L1 series (continued)

Feature STM32F1 series STM32L1 series

Program memory: word/ half

Program mode Half word

page DATA EEPROM memory:

byte /

half word / word / Double word

Read Protection

Unprotection

Protection

JTAG fuse

Read protection disable RDP = 0xA55A

Read protection enable RDP != 0xA55A

NA Level 2 RDP = 0xCC

Level 0 no protection RDP = 0xAA

Level 1 memory protection RDP != (Level 2 & Level 0)

(2)

Write protection granularity Protection by 4 Kbyte block Protection by sector

STOP STOP

STANDBY STANDBY

User Option bytes

WDG WDG

NA BOR level

NA BFB2

1. For more details refer to “EEPROM emulation in STM32F10x microcontrollers (AN2594)

2. Memory read protection Level 2 is an irreversible operation. When Level 2 is activated, the level of protection cannot be decreased to Level 0 or Level 1.

4.10 ADC

Table 13. ADC differences between STM32F1 series and STM32L1 series

ADC STM32F1 series STM32L1 series

ADC Type SAR structure SAR structure

Instances ADC1 / ADC2 / ADC3 ADC1

Max Sampling freq 1 MSPS

The table below presents the differences between the ADC interface of STM32F1 series and STM32L1 series, these differences are the following:

● New digital interface

● New architecture and new features

1 MSPS

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Color key:

= Same feature, but specification change or enhancement

Table 13. ADC differences between STM32F1 series and STM32L1 series (continued)

ADC STM32F1 series STM32L1 series

Number of channels

up to 21 channels

up to 42 Channels

Resolution 12-bit 12-bit

Conversion Modes

Single / continuous / Scan / Discontinuous / Dual Mode

Single / continuous / Scan / Discontinuous

DMA Ye s Ye s

Ye s Ye s

External Trigger

External event for regular group

For ADC1 and ADC2: TIM1 CC1 TIM1 CC2 TIM1 CC3 TIM2 CC2 TIM3 TRGO TIM4 CC4 EXTI line 11 / TIM8_TRGO For ADC3: TIM3 CC1 TIM2 CC3 TIM1 CC3 TIM8 CC1 TIM8 TRGO TIM5 CC1 TIM5 CC3

External event for injected group

For ADC1 and ADC2: TIM1 TRGO TIM1 CC4 TIM2 TRGO TIM2 CC1 TIM3 CC4 TIM4 TRGO EXTI line15 / TIM8_CC4 For ADC3: TIM1 TRGO TIM1 CC4 TIM4 CC3 TIM8 CC2 TIM8 CC4 TIM5 TRGO TIM5 CC4

External event for regular group

TIM9_CC2 TIM9_TRGO TIM2_CC3 TIM2_CC2 TIM3_TRGO TIM4_CC4 TIM2_TRGO TIM3_CC1 TIM3_CC3 TIM4_TRGO TIM6_TRGO EXTI line11

External event for injected group

TIM9_CC1 TIM9_TRGO TIM2_TRGO TIM2_CC1 TIM3_CC4 TIM4_TRGO TIM4_CC1 TIM4_CC2 TIM4_CC3 TIM10_CC1 TIM7_TRGO EXTI line15

Supply requirement 2.4 V to 3.6 V

Input range V

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<= VIN <= V

REF-

REF+

1.8 V to 3.6 V

<= VIN <= V

REF-

REF+

AN3422 Peripheral migration

4.11 PWR

In STM32L1 series the PWR controller presents some differences vs. F1 series, these differences are summarized in the table below. However, the programming interface is unchanged.

Table 14. PWR differences between STM32F1 series and STM32L1 series

PWR STM32F1 series STM32L1 series

Power supplies

1. V

= 2.0 to 3.6 V: external power

supply for I/Os and the internal regulator. Provided externally through

pins.

, V

2. V

SSA

= 2.0 to 3.6 V: external

DDA

analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA

when the ADC or DAC is used). V and V

must be connected to VDD

SSA

and VSS, respectively.

3. V

= 1.8 to 3.6 V: power supply for

BAT

RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

is 2.4 V

DDA

1. VDD = 1.8 V (at power on) or 1.65 V (at power down) to 3.6 V when the BOR is available. VDD = 1.65 V to

3.6 V, when BOR is not available. is the external power supply for I/Os and internal

regulator. It is provided externally through VDD pins.

2. V

CORE

and Flash memory. It is generated by a internal voltage regulator. Three V

= 1.2 to 1.8 V

CORE

is the power supply for digital peripherals, SRAM

ranges can be selected by

CORE

software depending on VDD.

, V

3. V

SSA

down) to 3.6 V, when BOR is available and V

= 1.8 V (at power on) or 1.65 V (at power

DDA

SSA

1.65 to 3.6 V, when BOR is not available.

is the external analog power supply for ADC, DAC,

DDA

reset blocks, RC oscillators and PLL. The minimum voltage to be applied to V

is 1.8 V when the ADC is

DDA

used.

, V

DDA

Battery backup domain

RTC domain

Power supply supervisor

4. V

= 2.5 to 3.6 V

LCD

The LCD controller can be powered either externally through the V

pin, or internally from an internal

LCD

voltage generated by the embedded step-up converter.

– Backup registers –RTC –LSE – PC13 to PC15 I/Os

Note: in F1 series the Backup registers are integrated in the BKP peripheral.

– RTC w/ backup registers –LSE

– PC13 to PC15 I/Os Note: in L1 series the backup registers are integrated in

the RTC peripheral

Integrated POR / PDR circuitry Programmable Voltage Detector (PVD)

Integrated POR / PDR circuitry Programmable voltage detector (PVD)

NA Brownout reset (BOR)

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= Same feature, but specification change or enhancement

Table 14. PWR differences between STM32F1 series and STM32L1 series (continued)

PWR STM32F1 series STM32L1 series

Low-power modes

Wake-up sources

Configuration

Sleep mode Stop mode Standby mode (1.8V domain powered-

off)

Sleep mode – Any peripheral interrupt/wakeup event Stop mode – Any EXTI line event/interrupt Standby mode – WKUP pin rising edge –RTC alarm – External reset in NRST pin – IWDG reset

RUN Low Power Sleep mode + peripherals automatic clock gating Sleep Low Power mode + peripherals automatic clock

gating Stop mode Standby mode (V

domain powered off)

CORE

Note: To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Sleep mode – Any peripheral interrupt/wakeup event Stop mode – Any EXTI line event/interrupt Standby mode – WKUP pin rising edge – RTC alarm A, RTC alarm B, RTC Wakeup, Tamper

event, TimeStamp event – External reset in NRST pin – IWDG reset

In L1 some additional bits were added: – PWR_CR[ULP] used to switch off the VREFINT in

STOP and STANDBY modes. – PWR_CR[FWU] used to ignore the VREFINT startup

time when exiting from low power modes. – PWR_CR[VOS] used to select the product voltage

range. – PWR_CR[LPRUN] used to select the RUN low power

mode. – PWR_CSR[VREFINTRDY]: VREFTINT ready status – PWR_CSR[VOSF]: Internal Regulator change status – PWR_CSR[REGLP]: MCU is in Low power run mode – PWR_CSR[EWUP2] and PWR_CSR[EWUP3]:

Wakeup Pin 2 and Wakeup Pin 3 Enable/Disable bits.

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4.12 RTC

The STM32L1 series embeds a new RTC peripheral vs. F1 series; the architecture, features and programming interface are different.

As consequence the L1 RTC programming procedures and registers are different from the the F1 series, so any code written for the F1 series using the RTC needs to be rewritten to run on L1 series.

The L1 RTC provides best-in-class features:

● BCD timer/counter

● Time-of-day clock/calendar with programmable daylight saving compensation

● Two programmable alarm interrupts

● Digital calibration circuit

● Time-stamp function for event saving

● Periodic programmable wakeup flag with interrupt capability

● Automatic wakeup unit to manage low power modes

● 32 backup registers (128 bytes) which are reset when a tamper detection event occurs

For more information about STM32L1’s RTC features, please refer to RTC chapter of STM32L1xx Reference Manual (RM0038).

For advanced information about the RTC programming, please refer to Application Note AN3371 Using the STM32 HW real-time clock (RTC).

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5 Firmware migration using the library

This section describes how to migrate an application based on STM32F1xx Standard Peripherals Library in order to use the STM32L1xx Standard Peripherals Library.

The STM32F1xx and STM32L1xx libraries have the same architecture and are CMSIS compliant, they use the same driver naming and the same APIs for all compatible peripheral.

Only a few peripheral drivers need to be updated to migrate the application from an F1 series to an L1 series product.

Note: In the rest of this chapter (unless otherwise specified), the term “STM32L1xx Library” is

used to refer to the STM32L1xx Standard Peripherals Library and the term of “STM32F10x Library” is used to refer to the STM32F10x Standard Peripherals Library.

5.1 Migration steps

To update your application code to run on STM32L1xx Library, you have to follow the steps listed below:

5. Update the toolchain startup files

a) Project files: device connections and Flash memory loader. These files are

provided with the latest version of your toolchain that supports STM32L1xxx devices. For more information please refer to your toolchain documentation.

b) Linker configuration and vector table location files: these files are developed

following the CMSIS standard and are included in the STM32L1xx Library install package under the following directory: Libraries\CMSIS\Device\ST\STM32L1xx.

6. Add STM32L1xx Library source files to the application sources

a) Replace the stm32f10x_conf.h file of your application with stm32l1xx_conf.h

provided in STM32L1xx Library.

b) Replace the existing stm32f10x_it.c/stm32f10x_it.h files in your application with

stm32l1xx_it.c/stm32l1xx_it.h provided in STM32L1xx Library.

7. Update the part of your application code that uses the RCC, PWR, GPIO, FLASH, ADC and RTC drivers. Further details are provided in the next section.

Note: The STM32L1xx Library comes with a rich set of examples (87 in total) demonstrating how

to use the different peripherals (under Project\STM32L1xx_StdPeriph_Examples\).

5.2 RCC

1. System clock configuration: as presented in section 4.4: RCC the STM32L1 and F1 series have the same clock sources and configuration procedures. However, there are some differences related to the product voltage range, PLL configuration, maximum frequency and Flash wait state configuration. Thanks to the CMSIS layer, these differences are hidden from the application code; you only have to replace the system_stm32f10x.c file by system_stm32l1xx.c file. This file provides an

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implementation of SystemInit() function used to configure the microcontroller system at start-up and before branching to the main() program.

Note: For STM32L1xx you can use the clock configuration tool,

STM32L1xx_Clock_Configuration.xls, to generate a customized SystemInit() function depending on your application requirements. For more information, refer to AN3309 “Clock configuration tool for STM32L1xx microcontrollers”

2. Peripheral access configuration

: as presented in section 4.4: RCC you need to call

different functions to [enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode]. For example, GPIOA is mapped on AHB bus on L1 series (APB2 bus on F1 series), to enable its clock you have to use the

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);

function instead of:

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

in the F1 series. Refer to Table4 on page15 for the peripheral bus mapping changes between L1 and F1 series.

Peripheral clock configuration

a) USB FS Device: in STM32L1 series the USB FS Device require a frequency of 48

MHz to work correctly. The following is an example of the main PLL configuration to obtain 32 MHz as system clock frequency and 48 MHz for the USB FS Device.

/* PLL_VCO = HSE_VALUE * PLL_MUL = 96 MHz */ /* USBCLK = PLL_VCO / 2= 48 MHz */ /* SYSCLK = PLL_VCO * PLL_DIV = 32 MHz */ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); /* Enable PLL */ RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { }

/* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) { } ... /* Enable USB FS Device's APB1 interface clock */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);

b) ADC: in STM32L1 series the ADC features two clock schemes:

– Clock for the analog circuitry: ADCCLK. This clock is generated always from the

HSI clock divided by a programmable prescaler that allows the ADC to work at f

/1, /2 or /4. This configuration is done using the ADC registers.

HSI

– Clock for the digital interface (used for register read/write access). This clock is

equal to the APB2 clock. The digital interface clock can be enabled/disabled through the RCC APB2 peripheral clock enable register (RCC_APB2ENR).

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/* Enable the HSI oscillator */ RCC_HSICmd(ENABLE);

/* Check that HSI oscillator is ready */ while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET) { } /* Enable ADC1 clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

5.3 FLASH

The table below presents the FLASH driver API correspondence between STM32F10x and STM32L1xx Libraries. You can easily update your application code by replacing STM32F10x functions by the corresponding function in STM32L1xx Library.

Table 15. STM32F10x and STM32L1xx FLASH driver API correspondence

STM32F10x Flash driver API STM32L1xx Flash driver API

void FLASH_SetLatency(uint32_t FLASH_Latency);

void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);

void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);

Interface configuration

void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);

void FLASH_SetLatency(uint32_t FLASH_Latency);

void FLASH_PrefetchBufferCmd(FunctionalState NewState);

void FLASH_ReadAccess64Cmd(FunctionalState NewState);

void FLASH_RUNPowerDownCmd(FunctionalState NewState);

void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);

void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);

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Table 15. STM32F10x and STM32L1xx FLASH driver API correspondence (continued)

STM32F10x Flash driver API STM32L1xx Flash driver API

void FLASH_Unlock(void); void FLASH_Unlock(void);

void FLASH_Lock(void); void FLASH_Lock(void);

FLASH_Status FLASH_ErasePage(uint32_t Page_Address);

FLASH_Status FLASH_EraseAllPages(void);

FLASH_Status FLASH_ErasePage(uint32_t Page_Address);

FLASH_Status FLASH_EraseOptionBytes(void);

FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);

FLASH_Status FLASH_ProgramHalfWord(uint32_t

Memory Programming

Address, uint16_t Data);

FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);

FLASH_Status FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);

FLASH_Status FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);

FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);

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Table 15. STM32F10x and STM32L1xx FLASH driver API correspondence (continued)

STM32F10x Flash driver API STM32L1xx Flash driver API

NA void FLASH_OB_Unlock(void);

NA void FLASH_OB_Lock(void);

FLASH_Status FLASH_ProgramOptionByteData(uint32 _t Address, uint8_t Data);

FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);

FLASH_Status FLASH_ReadOutProtection(FunctionalS tate NewState);

FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);

NA FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);

NA FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);

NA FLASH_Status FLASH_OB_Launch(void);

FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);

FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);

FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);

uint32_t FLASH_GetUserOptionByte(void);

Option Byte Programming

uint32_t FLASH_GetWriteProtectionOptionByte(v oid);

FlagStatus FLASH_GetReadOutProtectionStatus(v oid);

NA uint16_t FLASH_OB_GetWRP1(void);

NA uint16_t FLASH_OB_GetWRP2(void);

NA uint8_t FLASH_OB_GetBOR(void);

uint8_t FLASH_OB_GetUser(void);

uint16_t FLASH_OB_GetWRP(void);

FlagStatus FLASH_OB_GetRDP(void);

FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);

FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);

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Color key:

= New function

= Same function, but API was changed

= Function not available (NA)

Table 15. STM32F10x and STM32L1xx FLASH driver API correspondence (continued)

STM32F10x Flash driver API STM32L1xx Flash driver API

FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);

void FLASH_ClearFlag(uint32_t FLASH_FLAG);

FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_GetStatus(void);

FLASH_Status FLASH_WaitForLastOperation(uint32_t

FLAG management

Timeout);

FlagStatus FLASH_GetPrefetchBufferStatus(void);

NA void DATA_EEPROM_Unlock(void);

NA void DATA_EEPROM_Lock(void);

FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);

void FLASH_ClearFlag(uint32_t FLASH_FLAG);

FLASH_Status FLASH_WaitForLastOperation(void);

FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);

FLASH_Status DATA_EEPROM_EraseDoubleWord(uint32_t Address);

FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);

FLASH_Status

DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);

FLASH_Status

DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);

FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);

DATA EEPROM management

FLASH_Status

DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);

FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);

FLASH_Status

DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);

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5.4 GPIO

This section explains how to update the configuration of the various GPIO modes when porting the application code from STM32F1 series to STM32L1 series.

5.4.1 Output mode

The example below shows how to configure an I/O in output mode (for example to drive a led) in STM32F1 series:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_xxMHz; /* 2, 10 or 50 MHz */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; GPIO_Init(GPIOy, &GPIO_InitStructure);

In L1 series you have to update this code as follows:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; /* Push-pull or open drain */ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; /* None, Pull-up or pull-down */ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_xxMHz; /* 400 KHz, 2, 10 or 40MHz */ GPIO_Init(GPIOy, &GPIO_InitStructure);

5.4.2 Input mode

The example below shows how to configure an I/O in input mode (for example to be used as an EXTI line) in STM32F1 series:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOy, &GPIO_InitStructure);

In L1 series you have to update this code as follows:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; /* None, Pull-up or pull-down */ GPIO_Init(GPIOy, &GPIO_InitStructure);

5.4.3 Analog mode

The example below shows how to configure an I/O in analog mode (for example an ADC or DAC channel) in STM32F1 series:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; GPIO_Init(GPIOy, &GPIO_InitStructure);

In L1 series you have to update this code as follows:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x ; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; GPIO_Init(GPIOy, &GPIO_InitStructure);

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5.4.4 Alternate function mode

In STM32F1 series

1. The configuration to use an I/O as alternate function depends on the peripheral mode used, for example the USART Tx pin should be configured as alternate function pushpull while the USART Rx pin should be configured as input floating or input pull-up.

2. To optimize the number of peripheral I/O functions for different device packages, it is possible by software to remap some alternate functions to other pins, for example the USART2_RX pin can be mapped on PA3 (default remap) or PD6 (by software remap).

In STM32L1 series

1. Whatever the peripheral mode used, the I/O must be configured as alternate function, then the system can use the I/O in the proper way (input or output).

2. The I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function to be connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIO_PinAFConfig () function:

– After reset all I/Os are connected to the system’s alternate function 0 (AF0)

– The peripherals’ alternate functions are mapped by configuring AF1 to AF13

– Cortex-M3 EVENTOUT is mapped by configuring AF15

3. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripheral I/O functions for different device packages, for example the USART2_RX pin can be mapped on PA3 or PD6 pin

4. Configuration procedure

– Connect the pin to the desired peripherals' Alternate Function (AF) using

GPIO_PinAFConfig() function

– Use GPIO_Init() function to configure the I/O pin:

- Configure the desired pin in alternate function mode using GPIO_InitStructure->GPIO_Mode = GPIO_Mode_AF;

- Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members

The example below shows how to remap USART2 Tx/Rx I/Os on PD5/PD6 pins in STM32F1 series:

/* Enable APB2 interface clock for GPIOD and AFIO (AFIO peripheral is used to configure the I/Os software remapping) */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);

/* Enable USART2 I/Os software remapping [(USART2_Tx,USART2_Rx):(PD5,PD6)] */ GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);

/* Configure USART2_Tx as alternate function push-pull */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(GPIOD, &GPIO_InitStructure);

/* Configure USART2_Rx as input floating */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOD, &GPIO_InitStructure);

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In L1 series you have to update this code as follows:

/* Enable GPIOD's AHB interface clock */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);

/* Select USART2 I/Os mapping on PD5/6 pins [(USART2_TX,USART2_RX):(PD5,PD6)] */ /* Connect PD5 to USART2_Tx */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_USART2); /* Connect PD6 to USART2_Rx*/ GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_USART2);

/* Configure USART2_Tx and USART2_Rx as alternate function */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOD, &GPIO_InitStructure);

5.5 EXTI

The example below shows how to configure the PA0 pin to be used as EXTI Line0 in STM32F1 series:

/* Enable APB interface clock for GPIOA and AFIO */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);

/* Configure PA0 pin in input mode */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Connect EXTI Line0 to PA0 pin */ GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource0);

/* Configure EXTI line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure);

In L1 series the configuration of the EXTI line source pin is performed in the SYSCFG peripheral (instead of AFIO in F1 series). As result, the source code should be updated as follows:

/* Enable GPIOA's AHB interface clock */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); /* Enable SYSCFG's APB interface clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);

/* Configure PA0 pin in input mode */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Connect EXTI Line0 to PA0 pin */ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);

/* Configure EXTI line0 */

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EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure);

5.6 ADC

This section gives an example of how to port existing code from STM32F1 series to STM32L1 series.

The example below shows how to configure the ADC1 to convert continuously channel14 in STM32F1 series:

... /* ADCCLK = PCLK2/4 */ RCC_ADCCLKConfig(RCC_PCLK2_Div4);

/* Enable ADC's APB interface clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

/* Configure ADC1 to convert continously channel14 */ ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; ADC_InitStructure.ADC_ScanConvMode = ENABLE; ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; ADC_InitStructure.ADC_NbrOfChannel = 1; ADC_Init(ADC1, &ADC_InitStructure); /* ADC1 regular channel14 configuration */ ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5);

/* Enable ADC1's DMA interface */ ADC_DMACmd(ADC1, ENABLE);

/* Enable ADC1 */ ADC_Cmd(ADC1, ENABLE);

/* Enable ADC1 reset calibration register */ ADC_ResetCalibration(ADC1); /* Check the end of ADC1 reset calibration register */ while(ADC_GetResetCalibrationStatus(ADC1));

/* Start ADC1 calibration */ ADC_StartCalibration(ADC1); /* Check the end of ADC1 calibration */ while(ADC_GetCalibrationStatus(ADC1));

/* Start ADC1 Software Conversion */ ADC_SoftwareStartConvCmd(ADC1, ENABLE); ...

In L1 series you have to update this code as follows:

... /* Enable the HSI oscillator */ RCC_HSICmd(ENABLE);

/* Check that HSI oscillator is ready */ while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET) { }

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/* Enable ADC1 clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

/* Common configuration *****************************************************/ /* ADCCLK = HSI/1 */ ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div1; ADC_CommonInit(&ADC_CommonInitStructure);

/* ADC1 configuration */ ADC_InitStructure.ADC_ScanConvMode = ENABLE; ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConvEdge_None; ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; ADC_InitStructure.ADC_NbrOfConversion = 1; ADC_Init(ADC1, &ADC_InitStructure);

/* ADC1 regular channel14 configuration */ ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_4Cycles);

/* Enable the request after last transfer for DMA Circular mode */ ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE);

/* Enable ADC1 DMA */ ADC_DMACmd(ADC1, ENABLE);

/* Enable ADC1 */ ADC_Cmd(ADC1, ENABLE);

/* Wait until the ADC1 is ready */ while(ADC_GetFlagStatus(ADC1, ADC_FLAG_ADONS) == RESET) { }

/* Start ADC1 Software Conversion */ ADC_SoftwareStartConv(ADC1); ...

The main changes in the source code/procedure in L1 series vs. F1 are described below:

1. ADC configuration is made through two functions ADC_CommonInit() and ADC_Init(): ADC_CommonInit() function is used to configure the ADC analog clock prescaler.

2. To enable the generation of DMA requests continuously at the end of the last DMA transfer, the ADC_DMARequestAfterLastTransferCmd() function should be used.

3. No calibration is needed

5.7 PWR

The table below presents the PWR driver API correspondence between STM32F10x and STM32L1xx Libraries. You can easily update your application code by replacing STM32F10x functions by the corresponding function in STM32L1xx Library.

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Color key:

= New function

= Same function, but API was changed

= Function not available (NA)

Table 16. STM32F10x and STM32L1xx PWR driver API correspondence

STM32F10x PWR driver API STM32L1xx PWR driver API

void PWR_DeInit(void); void PWR_DeInit(void);

void PWR_BackupAccessCmd(FunctionalSta

void PWR_RTCAccessCmd(FunctionalState NewState);

te NewState);

Interface configuration

void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);

PVD

void PWR_PVDCmd(FunctionalState NewState);

void PWR_WakeUpPinCmd(FunctionalState NewState);

NA void PWR_FastWakeUpCmd(FunctionalState NewState);

Wakeup

void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);

void PWR_PVDCmd(FunctionalState NewState);

void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);

NA void PWR_UltraLowPowerCmd(FunctionalState NewState);

void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);

void PWR_EnterLowPowerRunMode(FunctionalState NewState);

void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t

Power Management

PWR_STOPEntry);

void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);

void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);

void PWR_EnterSTANDBYMode(void); void PWR_EnterSTANDBYMode(void);

FlagStatus PWR_GetFlagStatus(uint32_t

FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);

PWR_FLAG);

void PWR_ClearFlag(uint32_t PWR_FLAG);

FLAG management

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5.8 Backup data registers

In STM32F1 series the Backup data registers are managed through the BKP peripheral, while in L1 series they are a part of the RTC peripheral (there is no BKP peripheral).

The example below shows how to write to/read from Backup data registers in STM32F1 series:

uint16_t BKPdata = 0;

... /* Enable APB2 interface clock for PWR and BKP */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);

/* Enable write access to Backup domain */ PWR_BackupAccessCmd(ENABLE);

/* Write data to Backup data register 1 */ BKP_WriteBackupRegister(BKP_DR1, 0x3210);

/* Read data from Backup data register 1 */ BKPdata = BKP_ReadBackupRegister(BKP_DR1);

In L1 series you have to update this code as follows:

uint16_t BKPdata = 0;

... /* PWR Clock Enable */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);

/* Enable write access to RTC domain */ PWR_RTCAccessCmd(ENABLE);

/* Write data to Backup data register 1 */ RTC_WriteBackupRegister(RTC_BKP_DR1, 0x3220);

/* Read data from Backup data register 1 */ BKPdata = RTC_ReadBackupRegister(RTC_BKP_DR1);

The main changes in the source code in L1 series vs. F1 are described below:

1. There is no BKP peripheral

2. Write to/read from Backup data registers are done through RTC driver

3. Backup data registers naming changed from BKP_DRx to RTC_BKP_DRx, and numbering starts from 0 instead of 1

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6 Revision history

Table 17. Document revision history

Date Revision Changes

20-Jul-2011 1 Initial release

01-Mar-2012 2 Added support for medium+ and high-density STM32L1xxx

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AN3422

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ST AN3422 APPLICATION NOTE

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

2 STM32L1 family overview

3 Hardware migration

Table 2. STM32F1 series and STM32L1 series pinout differences

Figure 1. Compatible board design: LQFP144

Figure 2. Compatible board design: LQFP100

Figure 3. Compatible board design: LQFP64

Figure 4. Compatible board design: LQFP48

4 Peripheral migration

4.1 STM32 product cross-compatibility

Table 3. STM32 peripheral compatibility analysis F1 versus L1 series

4.2 System architecture

4.3 Memory mapping

Table 4. IP bus mapping differences between STM32F1 and STM32L1 series

4.4 RCC

Table 5. RCC differences between STM32F1 and STM32L1 series

Table 7. Example of migrating system clock configuration code from F1 to L1

Table 8. RCC registers used for peripheral access configuration

4.5 DMA

4.6 Interrupts

4.7 GPIO

Table 11. GPIO differences between STM32F1 series and STM32L1 series

4.8 EXTI source selection

4.9 FLASH

4.10 ADC

4.11 PWR

4.12 RTC

5 Firmware migration using the library

5.1 Migration steps

5.2 RCC

5.3 FLASH

5.4 GPIO

5.4.1 Output mode

5.4.2 Input mode

5.4.3 Analog mode

5.4.4 Alternate function mode

5.5 EXTI

5.6 ADC

5.7 PWR

Table 16. STM32F10x and STM32L1xx PWR driver API correspondence

5.8 Backup data registers

6 Revision history

Table 17. Document revision history