ST AN3393 APPLICATION NOTE

AN3393

Application note

L3G4200D: three axis digital output gyroscope

Introduction

This document is intended to provide usage information and application hints related to ST L3G4200D 3-axial digital gyroscope.

The L3G4200D is an is three-axis angular rate sensor, with a digital I2C/SPI serial interface standard output.

The device has a full scale of ±250/±500/ ±2000 dps and is capable of measuring rates with a user-selectable bandwidth.

The device may be configured to generate interrupt signals by an independent wake-up event. Thresholds and timing of the interrupt generator are programmable by the end user on the fly.

The L3G4200D has an integrated 32-level first in first out (FIFO) buffer allowing the user to store data for host processor intervention reduction.

The L3G4200D is available in a small thin plastic land grid array package (LGA 4x4x1.1) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

The ultra small size and weight of the SMD package make it an ideal choice for handheld portable applications such as cell phones and PDAs, or any other application where reduced package size and weight are required.

April 2011

Doc ID 018750 Rev 1

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www.st.com

Contents	AN3393

Contents

1	Registers table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.1	Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.2	Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.3	Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.4	Switch mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
3	Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	3.1	Reading angular rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		3.1.1 Using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		3.1.2 Using the data-ready (DRY) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		3.1.3 Using the block data update (BDU) feature . . . . . . . . . . . . . . . . . . . . . .	11
	3.2	Understanding angular rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12

3.2.1 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 Big-little endian selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.3 Example of angular rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4	Digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	4.1	Filters configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.2	Low pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	4.3	High Pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15

4.3.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.2 Reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.3 Autoreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5	Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	5.1	Interrupt pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.2	Interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	5.3	Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	5.4	Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	5.5	Selective axis movement and wake-up interrupts . . . . . . . . . . . . . . . . . .	22

5.5.1 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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AN3393	Contents

5.5.2 HP filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5.3 Using the HP filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.6 Selective axis movement detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6	First in first out (FIFO) buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			27
	6.1	FIFO description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	6.2	FIFO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
		6.2.1	Control register 5 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
		6.2.2	FIFO control register (0x2E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
		6.2.3	FIFO source register (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30

6.3 FIFO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3.5 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.4 Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7	Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

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List of tables	AN3393

List of tables

Table 1. Registers table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Output data registers content vs. angular rate (FS = 250 dps). . . . . . . . . . . . . . . . . . . . . . 12 Table 7. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Out_Sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. INT_SEL configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. Low pass filters cut-off frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 11. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12. High pass filter cut-off frequency [Hz]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. High pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 14. Reference mode LSB value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 15. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 16. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 17. INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 18. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 19. Interrupt mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 20. INT1_THS_xH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 21. INT1_THS_xL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 22. Threshold LSB value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 23. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 24. INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 25. Duration LSB value in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 26. FIFO buffer full representation (32nd sample set stored) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 27. FIFO overrun representation (33rd sample set stored and 1st sample discarded). . . . . . . 28 Table 28. FIFO enable bit in CTRL_REG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 29. FIFO_CTRL_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 30. FIFO_SRC_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 31. FIFO_SRC_REG behavior assuming FTH[4:0] = 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 32. CTRL_REG3 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 33. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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AN3393	List of figures

List of figures

Figure 1. Data ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. Low-pass/High-pass filter connections block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. HP_FILTER_RESET readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. Autoreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Interrupt signals and interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Wait enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. No-move, wake-up interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. NM_WU_CFG high and low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. Wake-up interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. No-move interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 13. FIFO_EN connection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 14. FIFO mode behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 15. Stream mode fast reading behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 16. Stream mode slow reading behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 17. Stream mode slow reading zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 18. Stream-to-FIFO mode: interrupt not latched. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 19. Stream-to-FIFO mode: interrupt latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 20. Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 21. Watermark behavior - FTH[4:0] = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 22. FIFO reading diagram - FTH[4:0] = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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1

Registers table

Table 1.

Registers table

Register name

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

WHO_AM_I

0Fh

1

1

0

1

0

0

1

1

CTRL_REG1

20h

DR1

DR0

BW1

BW0

PD

Zen

Yen

Xen

CTRL_REG2

21h

0

0

HPM1

HPM0

HPCF3

HPCF2

HPCF1

HPCF0

CTRL_REG3

22h

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

CTRL_REG4

23h

BDU

BLE

FS1

FS0

-

ST1

ST0

SIM

CTRL_REG5

24h

BOOT

FIFO_EN

--

HPen

INT1_Sel1

INT1_Sel0

Out_Sel1

Out_Sel0

Doc

REFERENCE

25h

REF7

REF6

REF5

REF4

REF3

REF2

REF1

REF0

OUT_TEMP

26h

Temp7

Temp6

Temp5

Temp4

Temp3

Temp2

Temp1

Temp0

ID

STATUS_REG

27h

ZYXOR

ZOR

YOR

XOR

ZYXDA

ZDA

YDA

XDA

018750

OUT_X_L

28h

XD7

XD6

XD5

XD4

XD3

XD2

XD1

XD0

Rev

OUT_X_H

29h

XD15

XD14

XD13

XD12

XD11

XD10

XD9

XD8

OUT_Y_L

2Ah

YD7

YD6

YD5

YD4

YD3

YD2

YD1

YD0

1

OUT_Y_H

2Bh

YD15

YD14

YD13

YD12

YD11

YD10

YD9

YD8

OUT_Z_L

2Ch

ZD7

ZD6

ZD5

ZD4

ZD3

ZD2

ZD1

ZD0

OUT_Z_H

2Dh

ZD15

ZD14

ZD13

ZD12

ZD11

ZD10

ZD9

ZD8

FIFO_CTRL_REG

2Eh

FM2

FM1

FM0

WTM4

WTM3

WTM2

WTM1

WTM0

FIFO_SRC_REG

2Fh

WTM

OVRN

EMPTY

FSS4

FSS3

FSS2

FSS1

FSS0

INT1_CFG

30h

AND/OR

LIR

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

INT1_SRC

31h

-

IA

ZH

ZL

YH

YL

XH

XL

INT1_TSH_XH

32h

-

THSX14

THSX13

THSX12

THSX11

THSX10

THSX9

THSX8

INT1_TSH_XL

33h

THSX7

THSX6

THSX5

THSX4

THSX3

THSX2

THSX1

THSX0

6/41

INT1_TSH_YH

34h

-

THSY14

THSY13

THSY12

THSY11

THSY10

THSY9

THSY8

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table Registers

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Table 1.	Registers table (continued)
Register name		Address	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
INT1_TSH_YL		35h	THSY7	THSY6	THSY5	THSY4	THSY3	THSY2	THSY1	THSY0
INT1_TSH_ZH		36h	-	THSZ14	THSZ13	THSZ12	THSZ11	THSZ10	THSZ9	THSZ8
INT1_TSH_Z		37h	THSZ7	THSZ6	THSZ5	THSZ4	THSZ3	THSZ2	THSZ1	THSZ0
INT1_DURATION		38h	WAIT	D6	D5	D4	D3	D2	D1	D0

table Registers

AN3393

Operating modes	AN3393

2 Operating modes

The L3G4200D provides three different operating modes, respectively reported as powerdown mode, sleep mode and normal mode.

After power supply is applied, the L3G4200D performs a 10 ms boot procedure to load the trimming parameter. After the boot is completed, the device is automatically configured in power-down mode.

Referring to the L3G4200D datasheet, output data rate (ODR), power down (PD) and Zen, Yen, Xen bits of CTRL_REG1 are used to select the operating modes (power-down mode, low power mode and normal mode) and output data rate (Table 2 and Table 3).

Table 2.	Operating mode selection
Operating mode		PD		Zen	Yen	Xen
Power down		0		-	-	-
Sleep		1		0	0	0
Normal mode		1		-	-	-

Table 3.	Data rate configuration
DR <1:0>		BW <1:0>		ODR [Hz]	Cut-off LPF1 [Hz]	Cut-off LPF2 [Hz]
00		00		100		12.5
00		01		100	32	25
00		10		100		25
00		11		100		25
01		00		200		12.5
01		01		200	54	25
01		10		200		50
01		11		200		70
10		00		400		20
10		01		400	78	25
10		10		400		50
10		11		400		110
11		00		800		30
11		01		800	93	35
11		10		800		50
1		11		800		110

Table 4 shows the typical values of the power consumption for the different operating modes. Power consumption in normal mode is independent on selected ODR.

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AN3393				Operating modes
	Table 4.	Power consumption
		Operating mode		Power consumption
		Power-down		5 µA
		Sleep		1.5 mA
		Normal		6.1 mA

2.1Power-down mode

When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. Digital interfaces (I2C and SPI) are still active to allow communication with the device. The configuration registers content is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode.

2.2Sleep mode

While the device is in sleep mode the driving circuitry making the moving mass of the gyroscope oscillating is kept active. Turn-on time from sleep mode to normal mode is drastically reduced.

2.3Normal mode

In normal mode, data are generated at the data rate (ODR) selected through the DR bits. Data interrupt generation is active and configured through the INT1_CFG register.

2.4Switch mode timing

Switch mode time is shown in Table 5.

	Table 5.	Turn-on time
		Starting mode	Target mode	Turn-on time - TYP
		Power-down	Normal	250 ms
		Power-down	Self test	250 ms
		Sleep	Normal	1/ODR: LPF2 disabled
				6/ODR: LPF2 enabled
		Normal	Sleep	immediate
		Normal	Power-down	immediate
	Other settings change		-	1/ODR: LPF2 disabled
				6/ODR: LPF2 enabled

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Startup sequence	AN3393

3 Startup sequence

Once the device is powered-up, it automatically downloads the calibration coefficients from the embedded flash to the internal registers. When the boot procedure is completed, i.e. after approximately 5 milliseconds, the device automatically enters power-down mode. To turn-on the device and gather angular rate data, it is necessary to select one of the operating modes through CTRL_REG1 and to enable at least one of the axes.

The following general purpose sequence can be used to configure the device:

1.Write CTRL_REG2

2.Write CTRL_REG3

3.Write CTRL_REG4

4.Write CTRL_REG6

5.Write Reference

6.Write INT1_THS

7.Write INT1_DUR

8.Write INT1_CFG

9.Write CTRL_REG5

10.Write CTRL_REG1

3.1Reading angular rate data

3.1.1Using the status register

The device is provided with a STATUS_REG which should be polled to check when a new set of data is available. The reading procedure should be the following:

1.Read STATUS_REG

2.If STATUS_REG(3) = 0 then go to 1

3.If STATUS_REG(7) = 1 then some data have been overwritten

4.Read OUT_X_L

5.Read OUT_X_H

6.Read OUT_Y_L

7.Read OUT_Y_H

8.Read OUT_Z_L

9.Read OUT_Z_H

10.Data processing

11.Go to 1

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AN3393	Startup sequence

The check performed at step 3 allows to understand whether the reading rate is adequate compared to the data production rate. In case one or more angular rate samples have been overwritten by new data, because of a too slow reading rate, the ZYXOR bit of STATUS_REG is set to 1.

The overrun bits are automatically cleared when all the data present inside the device have been read and new data have not been produced in the meantime.

3.1.2Using the data-ready (DRY) signal

The device may be configured to have one HW signal to determinate when a new set of measurement data is available for reading. This signal is represented by the XYZDA bit of STATUS_REG. The signal can be driven to DRY/INT2 pin by setting the I2_DRDY bit of CTRL_REG3 to 1 and its polarity set to active-low or active-high through the H_Lactive bit of CTRL_REG3 (see Section 5.1).

The data-ready signal rises to 1 when a new set of angular rate data has been generated and it is available for reading.The interrupt is reset when the higher part of one of the enabled channels has been read (29h, 2Bh, 2Dh).

Figure 1. Data ready signal

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3.1.3Using the block data update (BDU) feature

If the reading of the angular rate data is particularly slow and cannot be synchronized (or it is not required) with either the XYZDA bit present inside the STATUS_REG or with the RDY signal, it is strongly recommended to set the BDU (block data update) bit in CTRL_REG4 to 1.

This feature avoids the reading of values (most significant and least significant parts of the angular rate data) related to different samples. In particular, when the BDU is activated, the data registers related to each channel always contain the most recent angular rate data produced by the device, but, in case the reading of a given pair (i.e. OUT_X_H and OUT_X_L, OUT_Y_H and OUT_Y_L, OUT_Z_H and OUT_Z_L) is initiated, the refresh for that pair is blocked until both MSB and LSB parts of the data are read.

Note:	BDU only guarantees that OUT_X(Y, Z)_L and OUT_X(Y,Z)_H have been sampled at the
	same moment. For example, if the reading speed is too low, it may read X and Y sampled at
	T1 and Z sampled at T2.

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Startup sequence	AN3393

3.2Understanding angular rate data

The measured angular rate data are sent to OUT_X_H, OUT_X_L, OUT_Y_H, OUT_Y_L, OUT_Z_H, and OUT_Z_L registers. These registers contain, respectively, the most significant part and the least significant part of the angular rate signals acting on the X, Y, and Z axes.

The complete angular rate data for the X (Y, Z) channel is given by the concatenation OUT_X_H & OUT_X_L (OUT_Y_H & OUT_Y_L, OUT_Z_H & OUT_Z_L) and it is expressed as a 2’s complement number.

3.2.1Data alignment

Angular rate data are represented as 16-bit numbers and are left justified.

3.2.2Big-little endian selection

The L3G4200D allows to swap the content of the lower and the upper part of the angular rate registers (i.e. OUT_X_H with OUT_X_L), to be compliant with both little-endian and bigendian data representations.

“Little Endian” means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (The little end comes first). This mode corresponds to bit BLE in CTRL_REG4 reset to 0 (default configuration).

On the contrary, “Big Endian” means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address.

3.2.3Example of angular rate data

Table 6 provides a few basic examples of the data that is read in the data-registers when the device is subject to a given angular rate. The values listed in the table are given under the hypothesis of perfect device calibration (i.e. no offset, no gain error,....) and practically show the effect of the BLE bit.

Table 6.	Output data registers content vs. angular rate (FS = 250 dps)
		BLE = 0			BLE = 1
Angular rate values				Register address
		28h		29h	28h		29h
	0 dps	00h		00h	00h		00h
	100 dps	A4h		2Ch	2Ch		A4h
	200 dps	49h		59h	59h		49h
	-100 dps	5Ch		C4h	C3h		5Ch
	-200 dps	B7h		A6h	A6h		B7h

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AN3393	Digital filters

4 Digital filters

The L3G4200D provides embedded low-pass and as well as high-pass filtering capability to easily delete the DC component of the measured angular rate. As shown in Figure 2, through HPen, INTx_Sel and Out_Sel bits of CTRL_REG5 configuration, it is possible to independently apply the filter on the output/fifo data and/or on the interrupts data. This means that it is possible, i.e., to get filtered data while interrupt generation works on unfiltered data.

Table 7. CTRL_REG5 register

BOOT	FIFO_EN	-	HPen	INT1_Sel1	INT1_Sel0	Out_Sel1	Out_Sel0

Figure 2. Low-pass/High-pass filter connections block diagram

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4.1Filters configuration

Referring to Table 8, HPen and Out_sel bits are used to drive unfilterd or filterd data to the output registers and to the FIFO:

Table 8.	Out_Sel configuration setting
Hpen		OUT_SEL1	OUT_SEL0	Description
x		0	0	Data in DataReg and FIFO are non-high-
				pass-filtered
x		0	1	Data in DataReg and FIFO are high-pass-
				filtered
0		1	x	Data in DataReg and FIFO are low-pass-
				filtered by LPF2
1		1	x	Data in DataReg and FIFO are high-pass and
				low-pass-filtered by LPF2

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