ST AN3392 Application note
AN3392
Application note
Designing with the SPV1020, an interleaved boost converter with
MPPT algorithm
By Domenico Ragonese, Massimiliano Ragusa
Introduction
The SPV1020 is a monolithic DC-DC boost converter designed to maximize the power
generated by photovoltaic panels independent of temperature and the amount of solar
radiation. The optimization of the power conversion is obtained with embedded logic which
performs the MPPT (maximum power point tracking) algorithm on the PV cells connected to
the converter.
One or more converters can be housed in the junction box of PV panels, replacing the
bypass diodes. Because of the fact that the maximum power point is locally computed, the
efficiency at system level is higher compared to the use of conventional topologies, where
the MPPT is computed in the main centralized inverter.
For a cost effective application and miniaturized solution, the SPV1020 embeds the Power
MOSFETs for active switching and synchronous rectification, minimizing the number of
external devices. Furthermore, the 4-phase interleaved topology of the DC-DC converter
avoids the use of electrolytic capacitors, which can severely limit the system lifetime.
The SPV1020 operates at fixed frequency in PWM mode, where the duty cycle is controlled
by embedded logic running a Perturb&Observe MPPT algorithm. The switching frequency,
internally generated and set by default at 100 kHz, is externally adjustable, while the duty
cycle can range from 5% to 90% in steps of 0.2%.
Safety of the application is guaranteed by stopping the drivers in the case of output
overvoltage or overtemperature.
Figure 1. STEVAL-ISV009V1 demonstration board
May 2012 Doc ID 018749 Rev 1 1/57
www.st.com
Contents AN3392
Contents
1 Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPV1020 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Application efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 SPV1020 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 OFF-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.4 Normal/MPPT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 Current balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 External component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 Power and thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.3 Bootstrap capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4 Internal voltage rail capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.5 Input voltage capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.6 Input voltage partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/57 Doc ID 018749 Rev 1
AN3392 Contents
10.7 Input voltage sensing capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.8 Output voltage capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.9 Output voltage partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.10 Output voltage sensing capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.11 Internal oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.12 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.13 Protection devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.14 Pole-zero compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix A STEVAL-ISV009V1 application diagram. . . . . . . . . . . . . . . . . . . . . . 40
Appendix B SPV1020 parallel and series connection . . . . . . . . . . . . . . . . . . . . . 41
B.1 SPV1020 parallel connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
B.2 SPV1020 series connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Appendix C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
C.1 Power efficiency, MPPT efficiency and thermal analysis. . . . . . . . . . . . . . 46
13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Doc ID 018749 Rev 1 3/57
List of figures AN3392
List of figures
Figure 1. STEVAL-ISV009V1 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. SPV1020 output series connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Photovoltaic system with multi-string inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Photovoltaic panel for a distributed architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Step-up converter single-ended architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Step-up converter in continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Step-up converter in discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Boost converter interleaved 4-phase architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Synchronous rectification and zero crossing block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Boost IL-4 and SPV1020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Step-up current waveforms or interleaved 4-phase architecture . . . . . . . . . . . . . . . . . . . . 13
Figure 12. SPV1020 general FSM (finite state machine). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Burst mode FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. SPV1020 MPPT block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. SPV1020 equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. PV panels, power vs. voltage and current vs. voltage curves . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. MPPT data flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. MPPT concept flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Normal/MPPT mode, DCM vs. CM FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. Input voltage partitioning, sample circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. SPI interface: master/slaves connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 22. Frame structure: register read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23. Pin connection top view PowerSSO-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 24. STEVAL-ISV009V1 schematic (PowerSSO-36 package). . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 25. PCB layout example (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. PCB layout example (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 27. STEVAL-ISV009V1 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 28. SPV1020, output parallel connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. SPV1020, output series connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30. Measurement environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 31. Power efficiency vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 32. Power efficiency vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 33. Power efficiency vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 34. MPPT accuracy vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 35. MPPT accuracy vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 36. MPPT accuracy vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 37. Vin = 12 V, Iin = 8 A, VOUT = 36 V, Tamb = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 38. Vin = 12 V, Iin = 8 A, VOUT = 14 V, Tamb = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 39. Vin = 24 V, Iin = 8 A, VOUT = 36 V, Tamb = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 40. Vin = 24 V, Iin = 8 A, VOUT = 26 V, Tamb = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 41. Vin = 30 V, Iin = 8 A, VOUT = 36 V, Tamb = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 42. Vin = 30 V, Iin = 8 A, VOUT = 32 V, Tamb = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 43. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4/57 Doc ID 018749 Rev 1
AN3392 List of tables
List of tables
Table 1. Data format for words longer than 8 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2. Commands list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5. Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Doc ID 018749 Rev 1 5/57
Application overview AN3392
1 Application overview
The following diagram shows the typical architecture of a photovoltaic system for a grid
connected application and consists of a photovoltaic field and an electronic section.
Figure 2. SPV1020 output series connection
"LOCKING
DIODES
"Y PASS
DI
ODES
'RID
)NVERTER
.
The photovoltaic field is made up of PV panels. Some PV panels are connected in series to
make a PV string. Each string is connected in parallel with the others and then connected to
the electronic section of the system, the “inverter”, which has the role of adapting the
produced power to the characteristics of the public electrical grid.
.
.
!-V
Other electronic components are the bypass diodes and the blocking diodes.
Each bypass diode protects the panel to which it is connected by providing an alternative
path for the current flow generated by other panels. These diodes guarantee both panel
protection and system functionality in case of damaged or shaded panels.
Blocking diodes (or “cut-off” diodes) protect the entire string from current following from
other strings due to a lower voltage of the string, typically caused by shadows on a part of
the string.
6/57 Doc ID 018749 Rev 1
AN3392 Application overview
Inverters are complex systems normally providing three functions (DC-DC conversion, DCAC conversion and Anti-Islanding) managed by a main controller typically implemented by a
microcontroller or DSP and executing the following actions:
● Anti-Island control, a safety control forcing the system to disconnect from the grid when
it is OFF for maintenance.
● Inverter control, for converting the DC power generated by the PV field to AC power
compatible with the power on the public grid (voltage and current amplitude, frequency
and phase).
● The MPPT (maximum power point tracking) control, allowing the extraction of the
maximum amount of power possible from the PV field in order to maximize the power
sourced to the grid.
A limitation of the architecture in Figure 2 is that the MPPT control performs properly only
when the PV field is uniformly irradiated.
A first evolution of the above architecture is shown in Figure 3 (string-distributed), where the
inverter includes more DC-DC converter sub-blocks, each implementing its own MPPT
algorithm.
Figure 3. Photovoltaic system with multi-string inverter
"Y PASS
DI
ODES
'RID
)NVERTER
.
.
Even though this architecture provides for a different shadow on each string, it doesn’t solve
the problem of the partial shading on each panel.
.
!-V
Doc ID 018749 Rev 1 7/57
Application overview AN3392
A better solution for this issue is to place the DC-DC converter and related MPPT algorithm
on each panel. This approach provides for a simpler inverter architecture that doesn’t
require a DC-DC block and related controller.
Furthermore, in order to minimize the impact of partial shading on each panel, it’s possible
to show the concept having a DC-DC converter for each cell of the panel. As a compromise
between cost and performance the following approach splits a panel into 3 different
substrings.
Figure 4. Photovoltaic panel for a distributed architecture
6O
UT
"//34
06
-004
06
06
"//34
-004
"//34
-004
DISTRIBUTED
ARCHITECTURE
6O UT
!-V
8/57 Doc ID 018749 Rev 1
AN3392 Application information
2 Application information
A step-up (or boost) converter is a switching DC-DC converter able to generate an output
voltage higher than the input voltage.
Figure 5. Step-up converter single-ended architecture
!-V
The switching element (Sw) is typically driven by a fixed-frequency rectangular waveform
generated by a PWM controller.
When Sw is closed (T
), the inductor stores energy and its current increases with a slope
on
depending on the voltage across the inductor and its inductance value. During this time the
output voltage is sustained by C
and the diode doesn’t allow any charge transfer from
out
output to input stages.
When Sw is open (T
) the current in the inductor flows toward the output until the voltage
off
on node “A” is higher than the output voltage. During this phase the current in the inductor
decreases while the output voltage increases.
Figure 6 shows the behavior of the current on the inductor.
Figure 6. Step-up converter in continuous mode
Comparing the energy stored in the inductor during T
the relation between V
and Vin is:
OUT
Doc ID 018749 Rev 1 9/57
and the energy released during T
on
off
,
Application information AN3392
Equation 1
V
out
-----------
V
in
-------------=
1D–
1
where “D” is the duty cycle [T
/(Ton+T
on
)] of the rectangular waveform driving the switching
off
element.
Boost converters can work in two main modes:
● Continuous mode (CM);
● Discontinuous mode (DCM);
depending on whether the current on the inductor becomes zero (DCM), or not (CM), within
the switching period.
Figure 7. Step-up converter in discontinuous mode
Even though a boost converter may work both in CM and DCM modes, efficiency is normally
higher when it works in CM, if the switching frequency is constant.
Inductance and switching frequency (F
) determine the working mode. In order to have the
sw
system working in CM, the following rule should be used:
Equation 2
Vout
L
Pin
∗>
Worst case for L in the above formula is D = 50%.
10/57 Doc ID 018749 Rev 1
22
−
))D1(*D(
Fsw*2
AN3392 SPV1020 description
3 SPV1020 description
The SPV1020 is an IC designed to provide a boost with a 4-phase interleaved topology
when supplied by photovoltaic panels.
In a 4-phase topology, the inductor-switch-diode branch is cloned 3 times and the resulting
four branches are connected in parallel. The resulting architecture is shown in Figure 8
below:
Figure 8. Boost converter interleaved 4-phase architecture
!-V
The SPV1020 drives the four switching elements with the same waveform but shifted by
T
/4.
SW
In order to increase application efficiency each diode can be replaced by a switching
element driven complimentary with respect to the corresponding switch. Furthermore, these
four switching elements (synchronous rectifiers) must be driven in order to prevent current
flow from the output to the input.
The SPV1020 integrates four zero crossing blocks (ZCB), one for each branch. Their role is
to turn off the related synchronous rectifier to prevent reverse current flow from output to
input.
Doc ID 018749 Rev 1 11/57
SPV1020 description AN3392
Figure 9. Synchronous rectification and zero crossing block
".W
Finally, in order to minimize the entire bill of material, the SPV1020 integrates the eight
switching elements.
Figure 10. Boost IL-4 and SPV1020
VREF
PV+
PV-
MPPT
VOUT
PWM
GEN
VOUT
DC
PV-
PV+
SHIFTING
AM02597v1
Even though the interleaved topology increases the bill of material and the wiring of the final
PCB, it is preferable to the single-ended approach especially in high-power applications.
In fact, output voltage ripple and efficiency are critical parameters for boost applications.
The following is a brief description of a boost interleaved 4 (IL-4) architecture.
12/57 Doc ID 018749 Rev 1
AN3392 Output voltage ripple
4 Output voltage ripple
Assuming a resistive load, the output voltage ripple is directly related to the output current
ripple.
In a single-ended architecture, the output current is the current flowing on the inductor when
it recirculates through the rectifiers. Referring to Figure 6, the larger the inductance, the
smaller the current ripple (I
In IL-4 architecture, output current is the sum of the four currents flowing in each inductor.
Even if the current on each branch is the same as in the single-ended architecture, the
T
/4 shift between the driving signals implies that output current has a small amount of
SW
ripple. Figure 11 shows both the current in each branch and the final I
Figure 11. Step-up current waveforms or interleaved 4-phase architecture
b-Ia
).
.
OUT
With respect to single-ended architecture, input and output current ripple are significantly
reduced due to both the split of the incoming current in the four branches and the related
phase shift.
Doc ID 018749 Rev 1 13/57
Application efficiency AN3392
5 Application efficiency
In designing a boost application, a typical constraint is the maximum output current ripple.
Once frequency, input, and output voltage are defined, this ripple is directly related to the
inductance value in the application:
Equation 3
V
D
in
--------
I
rippleILmaxILmin
The inductance value can be designed for a single-ended architecture and then divided by 4
in the case of IL-4 architecture.
---------
⋅=–=
L
F
sw
Each inductor, due to its internal resistance (R
), can affect system efficiency. For high
L
current applications, an inductor with a compact geometry may compromise the efficiency
requirements.
Using the same ferromagnetic material, higher inductance can be achieved by increasing
the inductor geometry, or by increasing the number of turns but using a thinner wire.
In order to save space and cost, the latter solution is preferred but this increases the internal
resistance and the saturation current of the inductor.
14/57 Doc ID 018749 Rev 1
AN3392 SPV1020 functions
6 SPV1020 functions
6.1 Operating modes.
The SPV1020 works between three operating modes or states, depending on the voltage
provided by the supply source and by the previous mode or state:
● OFF-state
● Burst mode
● Normal (or MPPT) mode.
Figure 12. SPV1020 general FSM (finite state machine)
Normal/MPPT
Mode
6.2 OFF-state
The SPV1020 has a UVLO (undervoltage lockout) with hysteresis of 500 mV. The two
thresholds are 6.5 V (UVLO_H) for turn-on and 6.0 V for turn-off (UVLO_L).
At power-up, while the supply source provides a voltage lower than UVLO_H, the SPV1020
stays in the OFF-state. In this state, no switching is applied to the switching elements and all
the current provided by the PV panel (supply source) is directly transferred to the output
node through the intrinsic diode of the synchronous rectifiers.
All 4 Phases ON
[VCC > UVLO_H]
POWER UP
Burst
Mode
OFF State
[VCC < UVLO_L]
Not all phases ON
&
Default < N < Max
[VCC < UVLO_L]
&
N = default
AM02599v1
When the applied voltage reaches UVLO_H, the SPV1020 goes into burst mode. Burst
mode guarantees a soft startup and shutdown. When in burst mode, the SPV1020 updates
an internal counter according to the comparison between the sampled supply voltage and
UVLO thresholds. The SPV1020 goes back into the OFF-state when the internal counter
returns to its default value.
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SPV1020 functions AN3392
6.3 Burst mode
This mode guarantees a correct startup for the SPV1020, avoiding voltage oscillations. After
the input voltage is applied, the converter begins operation when the input voltage exceeds
6.5 V (ULVO_H).
Burst mode contains four internal states, which guarantee to gradually activate phase “1”
and sequentially the four phases. Figure 13 shows the FSM of burst mode (the grey circles
are the burst mode states).
Each phase is driven with a set of 10 “pulses”. Each pulse can be “ON”, driving the phase
with a signal at a minimum PWM duty cycle of 5%, or “OFF”, with the driving signal
completely low.
When activated, a phase is driven with 1 pulse “ON” and 9 pulses “OFF”. The number of
“ON” pulses can be increased up to 10 (in this case, another phase is activated), or
decreased down to 0 (the phase is always OFF).
An increase or decrease of “ON” pulses depends on the status of the ULVO signal that
checks if the input voltage is greater than the minimum threshold or not.
Figure 13. Burst mode FSM
[UVLO is ON ]
[UVLO is ON ]
Normal
Mode
[UVLO is OF F]
[UVLO is ON ]
Phases 1 & 3 active
@DC=5%
[UVLO is OF F]
[Check UVLO]
When all four phases are active, the system enters normal (or MPPT) mode.
6.4 Normal/MPPT mode
This mode guarantees the maximum power extraction from a photovoltaic input supply by
executing an MPPT algorithm.
The MPPT algorithm generates a voltage reference (Vref) for a PWM generator. The
resulting waveform, with a duty cycle (DC) proportional to Vref, drives the eight internal
switching elements.
[UVLO is OF F]
[UVLO is ON ]
& [n is 10]
Phases 1, 3 & 2 active
@DC=5%
Only Ph ase “1” is active
•n pulses @DC=5%
• (10-n) pulses @DC=0%
If UVL O is ON [n = n+1]
else [n = n -1]
[UVLO is OF F]
[UVLO is OF F]
&
[n is 1]
Phases 1, 3, 2 & 4 active
[UVLO is ON ]
@DC=5%
OFF State
[n = 1]
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16/57 Doc ID 018749 Rev 1
AN3392 SPV1020 functions
Figure 14. SPV1020 MPPT block
VOUT
PV+
PV-
MPPT
VREF
PWM
GEN
VOUT
DC
PV-
PV+
SHIFTING
AM02601v1
This application is equivalent to matching the impedance of the output load to the
impedance of the input source (PV panel). The value of the impedance (Z) that matches the
impedance of the input source depends on the duty cycle (DC) set by the SPV1020.
Figure 15. SPV1020 equivalent circuit
SPV1020
in
I
in
C
in
V
gm Vin
C
out
I
out
R
out
V
out
PV
DC
Panel
Z
AM02602v1
Each Z affects the power transfer between the input source and output load, and for each Z
an input voltage (V
algorithm is to regulate the proper DC in order to guarantee Z = Z
impedance of the source and Z is the impedance assuming Z
which the power extracted from the supply source (P
) and current (Iin) can be measured. The purpose of the MPPT
in
= Vin * Iin) is maximum
in
, where ZM is the
M
as the impedance value for
M
(MPP = VMP * IMP).
Figure 16 shows both the typical curves, power vs. voltage and current vs. voltage of a
photovoltaic panel.
Doc ID 018749 Rev 1 17/57
SPV1020 functions AN3392
Figure 16. PV panels, power vs. voltage and current vs. voltage curves
The voltage-current curve shows all the available working points of the PV panel at a given
solar irradiation. The power-voltage curve is derived by the voltage-current curve, plotting
the product V*I for each voltage applied.
Figure 17 shows the dataflow diagram of the MPPT algorithm implemented by the
SPV1020:
Figure 17. MPPT data flow diagram
MPPT algorithm
P(tn)
FV
P(tn) > P(t
)
n-1
Output voltage monitoring
V
o-max
V
o-th
V
ref
Sign = Inv(Sign)
V
=
ref
V
+ Sign * Step
ref
Vo (tn)
Update P(t
to DAC
The voltage reference generated by the MPPT algorithm is always limited by the overvoltage
(V
This algorithm is defined as Perturb&Observe because the system is excited (perturbed)
with a certain duty cycle (DC), the power is then monitored (observed), and then perturbed
with a new DC depending on the monitoring result.
) and voltage regulation (V
o-max
) control of the output.
o-th
)
n-1
AM02604v1
The SPV1020 executes the MPPT algorithm with a period equal to 256 times the switching
period. The switching period is 10 µs, therefore the MPPT algorithm period is 2.56 ms. This
time is required for the application to reach the new steady-state (voltage and current) after
18/57 Doc ID 018749 Rev 1
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