ST AN3390 APPLICATION NOTE

AN3390

Application note

EEPROM emulation in STM32F2xx microcontrollers

Introduction

EEPROMs (Electrically Erasable Programmable Read-Only Memory) are often used in industrial applications to store updateable data. An EEPROM is a type of permanent (nonvolatile) memory storage system used in complex systems (such as computers) and other electronic devices to store and retain small amounts of data in the event of power failure.

For low-cost purposes, external EEPROM can be replaced using one of the following features of STM32F2xx:

●On-chip 4 Kbytes backup SRAM

●On-chip Flash, with specific software algorithm

The STM32F2xx features 4 Kbytes backup SRAM that can be powered from the VBAT supply when the main VDD supply is powered off.

This backup SRAM can be used as internal EEPROM (without any additional software) as long as the VBAT is present (typically in battery powered application) with the advantage of high speed access at CPU frequency.

However, when the backup SRAM is used for other purposes and/or the application does not use the VBAT supply, the on-chip Flash memory (with a specific software algorithm) can be used to emulate EEPROM memory.

This application note describes the software solution for substituting standalone EEPROM by emulating the EEPROM mechanism using the on-chip Flash of STM32F2xx devices.

Emulation is achieved by employing at least two sectors in the Flash. The EEPROM emulation code swaps data between the sectors as they become filled, in a manner that is transparent to the user.

The EEPROM emulation driver supplied with this application note meets the following requirements:

●Lightweight implementations offering a simple API that consists of three functions for initialization, read data and write data, and reduced footprint.

●Simple and easily updateable code model

●Clean-up and internal data management transparent to the user

●Background sector erase

●At least two Flash memory sectors to be used, more if possible for wear leveling

The EEPROM size to be emulated is flexible, within the limits and constraints of the sector size, and allows for a maximum EEPROM size.

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Contents	AN3390

Contents

1	Main differences between external and emulated EEPROM . . . . . . . . .		5
	1.1	Difference in write access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	1.2	Difference in erase time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	1.3	Similarity in writing method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
2	Implementing EEPROM emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8

2.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Case of use: application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 EEPROM emulation software description . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 EEPROM emulation memory footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 EEPROM emulation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3	Embedded application aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.1	Data granularity management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	3.2	Wear leveling: Flash memory endurance improvement . . . . . . . . . . . . . .	16

3.2.1 Wear-leveling implementation example . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Page header recovery in case of power loss . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Cycling capability and page allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.1 Cycling capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.2 Flash page allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Real-time consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

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AN3390	List of tables

List of tables

Table 1. Differences between external and emulated EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Emulated pages possible status and corresponding actions . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. STM32F2xx Flash memory sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. API definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Memory footprint for EEPROM emulation mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. EEPROM emulation timings with a 120 MHz system clock . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Flash program functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Application design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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List of figures	AN3390

List of figures

Figure 1. Header status switching between page0 and page1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. EEPROM variable format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. Data update flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. WriteVariable flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Flash memory footprint for EEPROM emulation (mechanism and storage) . . . . . . . . . . . . 14 Figure 6. Page swap scheme with four pages (wear leveling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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AN3390	Main differences between external and emulated EEPROM

1Main differences between external and emulated EEPROM

EEPROM is a key component of many embedded applications that require non-volatile storage of data updated with byte or word granularity during run time.

Microcontrollers used in these systems are more often based on embedded Flash memory. To eliminate components, save PCB space and reduce system cost, the STM32F2xx Flash memory may be used instead of external EEPROM for simultaneous code and data storage.

Unlike Flash memory, however, external EEPROM does not require an erase operation to free up space before data can be rewritten. Special software management is required to store data in embedded Flash memory.

The emulation software scheme depends on many factors, including the EEPROM reliability, the architecture of the Flash memory used, and the product requirements.

The main differences between embedded Flash memory and external serial EEPROM are the same for any microcontroller that uses the same Flash memory technology (it is not specific to the STM32F2xx family products). The major differences are summarized in

Table 1.

	Table 1.	Differences between external and emulated EEPROM
		External EEPROM	Emulated EEPROM using on-	Emulated EEPROM using on-
	Feature	(for example, M24C64:
			chip Flash memory	chip backup SRAM memory (1)
		I²C serial access EEPROM)
		– Random byte Write within 5
		ms. Word program time = 20
	Write time	ms	Half-word program time: from	CPU speed with 0 wait state
		– Page (32 bytes) Write within	28 µs to 251 ms (2)
		5 ms. Word program time =
		625 µs
			Sector (large page) Erase time:
	Erase time	N/A	from 1s to 3 s (depending on the	NA
			sector size)
			Once started, is CPU-
			dependent.
			If a Write operation is interrupted	Can be accessed as bytes (8
		– Once started, is not CPU-	by CPU reset, the EEPROM
	Write		Emulation algorithm is stopped,	bits), half words (16 bits) or full
		dependent	but current Flash write operation	words (32 bits).
	method
		– Only needs proper supply	is not interrupted by a software	Write operation is interrupted by
			reset.	a software reset.
			Can be accessed as bytes (8
			bits), half words (16 bits) or full
			words (32 bits).

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Main differences between external and emulated EEPROM	AN3390

Table 1. Differences between external and emulated EEPROM (continued)

		External EEPROM	Emulated EEPROM using on-	Emulated EEPROM using on-
	Feature	(for example, M24C64:
			chip Flash memory	chip backup SRAM memory (1)
		I²C serial access EEPROM)
	Read	– Serial: a hundred µs	Parallel: (at 120 MHz) the
		– Random word: 92 µs	access time by half-word is from	CPU speed with 1 wait state
	access
		– Page: 22.5 µs per byte	0.44 µs to 332 µs (2)
			10 kilocycles by sector (large
			page). Using multiple on-chip
	Write/Erase		Flash memory pages is	No limit as long as VBAT is
		1 million Write cycles	equivalent to increasing the
	cycles		number of write cycles. See	present
			Section 3.4: Cycling capability
			and page allocation.

1.For more information about the backup SRAM usage, refer to “Battery backup domain” in STM32F2xx reference manual (RM0033).

2.For further detail, refer to Chapter 2.5: EEPROM emulation timing.

1.1Difference in write access time

Because Flash memories have a shorter write access time, critical parameters can be stored faster in the emulated EEPROM than in an external serial EEPROM, thereby improving data storage.

1.2Difference in erase time

	The difference in erase time is the other major difference between a standalone EEPROM
	and emulated EEPROM using embedded Flash memory. Unlike Flash memories,
	EEPROMs do not require an erase operation to free up space before writing to them. This
	means that some form of software management is required to store data in Flash memory.
	Moreover, as the erase process of a block in the Flash memory does not take long, power
	shutdown and other spurious events that might interrupt the erase process (a reset, for
	example) should be considered when designing the Flash memory management software.
	To design robust Flash memory management software a thorough understanding of the
	Flash memory erase process is necessary.
Note:	In the case of a CPU reset, ongoing sector erase or mass erase operations on the
	STM32F2xx embedded Flash are not interrupted.

1.3 Similarity in writing method

One of the similarities between external EEPROM and emulated EEPROM with the STM32F2xx embedded Flash is the writing method.

● Standalone external EEPROM: once started by the CPU, the writing of a word cannot be interrupted by a CPU reset. Only a supply failure will interrupt the write process, so

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AN3390	Main differences between external and emulated EEPROM

properly sizing the decoupling capacitors can secure the complete writing process inside a standalone EEPROM.

●Emulated EEPROM using embedded Flash memory: once started by the CPU, the write process can be interrupted by a power failure. In the case of a CPU reset, ongoing word write operation on the STM32F2xx embedded Flash are not interrupted. The EEPROM algorithm is stopped, but the current Flash word write operation is not interrupted by a CPU reset.

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