ST AN3352 Application note

AN3352

Application note

Dual LNB power supply based on the LNBH24L supply and control IC with step-up and I²C interface

Introduction

This application note is intended to provide additional information and suggestions for the correct use of the LNBH24L device. All waveforms shown are based on the demonstration board order code STEVAL-CBL008V1 described in Section 3.

The LNBH24L is an integrated solution for supplying/interfacing two independent LNB down-converters in antenna dishes and/or multi-switch box. It gives good performance in a simple and cheap way, with minimum external components necessary. It includes all functions needed for LNB supplying and interfacing, in accordance with international standards. Moreover, it includes an I²C bus interface and, thanks to a fully integrated step-up DC-DC converter, it functions with a single input voltage supply ranging from 8 V to 15 V.

Figure 1. LNBH24L internal block diagram

TTX-A

ISEL-A

ADDR -A

SDA

SCL

ADDR -B

Vcc

Byp

Vcc-L

ISEL-B

TTX-B

LX -A

Preregulator

LX -B

+U.V.lockout

Controller

PWM

+P.ON reset

Controller

Rsense

EN-A

TEN-A

TEN-B

EN-B

PWM

Rsense

P-GND-A

VSEL-A

VSEL-B

P-GND-B

EN-A

ce

EN-B

VSEL-A

interfa

VSEL-B

TTX-A

TTX-B

Vup -B

Vup -A

C

ISEL-A

VOUT-A Control

I²

VOUT-B Control

ISEL-B

VoRX -A

Linear Post -reg

Linear Post -reg

VoRX -B

+Protections

+Protections

TTX-A

+Diagnostics

I²C Diagnostics

+Diagnostics

TTX-B

VoTX-A

FB

FB

22 kHz

22 kHz

VoTX -B

Oscillator

Oscillator

EXTM-A

EXTM-B

DSQIN-A

DSQIN-B

TEN-A

LNBH24L

TEN-B

PDC-A

PDC-B

Pull Down

Pull Down

Controller

Controller

AM09362v1

A-GND

November 2011

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www.st.com

Contents	AN3352

Contents

1	Block diagram and pin function description . . . . . . . . . . . . . . . . . . . . .		5
	1.1	Step-up controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Pre-regulator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.3	I²C interface and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.4	DiSEqC™ 1.X implementation through EXTM pin . . . . . . . . . . . . . . . . . . .	6
	1.5	DiSEqC 1.X implementation through VoTX and EXTM . . . . . . . . . . . . . . .	7

1.6PDC optional circuit for DiSEqC 1.X applications using VoTX signal

on to EXTM pin and 22 kHz tone controlled by DSQIN pin . . . . . . . . . . . . 7 1.7 22 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.8 DiSEqC communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.9 Linear post-regulator, modulator and protection . . . . . . . . . . . . . . . . . . . . 8 1.10 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2	Component selection guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.1	DC-DC converter inductor (L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.2	Output current limit selection (R2-RSEL) . . . . . . . . . . . . . . . . . . . . . . . . .	13
	2.3	DC-DC converter Schottky diode (D1) . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.4	TVS diode (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.5	DC-DC output capacitors (C3, C4, C6) and ferrite bead . . . . . . . . . . . . .	16
	2.6	Input capacitors (C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	2.7	PDC optional external circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	2.8	EXTM-VOTX resistor (R9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	2.9	Undervoltage protection diode (D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

3	Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	3.1	PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	3.2	PCB Thermal managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
4	Startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
5	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25

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AN3352	List of tables

List of tables

Table 1. LNBH24L I²C addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. LNBH24L pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. LNBH24L demo-board BOM list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Recommended Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Recommended Schottky diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Recommended LNBTVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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List of figures	AN3352

List of figures

Figure 1. LNBH24L internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. EXTM example of use with 22 kHz IC controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. DiSEqC 1.X tone burst with 22 kHz IC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. DiSEqC timing control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. LNBH24L pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. LNBH24L typical application circuit with internal tone generator . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Typical output current limiting vs. RSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Example of LNBTVS diode connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. DC-DC converter output stage with ferrite bead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Application circuit with PDC optional solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. PDC optional circuit load calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. PDC circuit waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. Tone amplitude vs. R9 value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14. PBC top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15. PBC bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16. PCB components layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 17. PCB connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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AN3352	Block diagram and pin function description

1 Block diagram and pin function description

Here below a description of the LNBH24L internal blocks that includes two completely independent sections. Except for the VCC and I²C inputs, each circuit can be separately controlled and contain independent external components. All the specifications below must be considered equal for both sections (A/B).

1.1Step-up controller

The LNBH24L features a built-in step-up DC-DC converter that, from a single supply source ranging from 8 V to 15 V, generates the voltages that allow the linear post-regulator to work with minimum power dissipation. The external components of the DC-DC converter are connected to the LX and VUP pins (see Figure 6). No external power MOSFET is needed.

1.2Pre-regulator block

This block includes a voltage reference connected to the BYP pin, an undervoltage lockout circuit, intended to disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7 V typ), and a power-on reset that sets all the I²C registers to zero when the VCC is turned on and rises from zero above the “ON” threshold (7.3 V typ).

1.3I²C interface and diagnostic

The main functions of the device are controlled via the I²C bus by writing 5 bits on the system register (SR bits in write mode). In the same register there are 5 bits that can be read back (SR bits in read mode) and provide 2 diagnostic functions, whereas the other 3 bits are for internal use (TEST1, TEST2, and TEST3).

Two bits report the diagnostic status of the two internal monitoring functions:

–OTF: overtemperature flag. If an overheating occurs (junction temperature exceeds 150 °C), the OTF I²C bit is set to “1”.

–OLF: overload flag. If the output current required exceeds the current limit threshold or a short-circuit occurs, the OLF I²C bit is set to “1”.

Moreover, three bits report the last output voltage register status (EN, VSEL, LLC) received by the I²C. The LNBH24L I²C interface address can be selected from two different addresses for each section A/B by setting the voltage level of the relevant ADDR pin according to Table 1:

Table 1.	LNBH24L I²C addresses
Section		Pin Set-up	Write (HEX)	Read (HEX)
	A	ADDR-A=low or floating	10	11
		ADDR-A=high	12	13
	B	ADDR-B=low or floating	14	15
		ADDR-B=high	16	16

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Block diagram and pin function description	AN3352

1.4DiSEqC™ 1.X implementation through EXTM pin

The EXTM pin is an analog input to generate the 22 kHz tone superimposed to the VoRX DC output voltage. If the EXTM pin is used, the internal 22 kHz generator must be kept OFF (TTX pin or TTX bit set LOW). A cheaper circuit must be used to couple the modulating signal source to the EXTM pin (see Figure 2).

The EXTM pin modulates the VoRX voltage through the series decoupling capacitor, so that:

VoRX (AC) = VEXTM (AC) x GEXTM

where:

–VoRX (AC) and VEXTM (AC) are, respectively, the peak-to-peak voltage on the VoRX and EXTM pin

–GEXTM is the voltage gain from EXTM to VoRX.

In order to avoid the 22 kHz tone distortion, a dummy output load may be necessary, strictly dependent on the output bus capacitance.

Table 2.	Output load
	Output bus capacitance	Output load
	< 50 nF	10 mA
	250 nF (EUTELSAT spec.)	30 mA
	750 nF (DIRECT TV spec.)	80 mA

For the correct DiSEqC implementation, during tone transmission, it is most important that the DiSEqC_out pin of the 22 kHz IC controller, is set in low impedance and vice versa, during no-tone transmission, it must be set in high impedance.

Figure 2 shows an example circuit as an appropriate solution with a 22 kHz IC controller to drive the EXTM pin for the DiSEqC implementation.

Figure 2. EXTM example of use with 22 kHz IC controller

	VDD 3V3
22 KHz IC		LNBH24L
controller	R2
	Vtone signal
DISEQC_OUT	C1	EXTM pin
	15 K
	1µF	VoRX	VoRx OUTPUT
PD	R1	EXTM
	R3
R		Z
			AM09363v1

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AN3352	Block diagram and pin function description

Figure 3. DiSEqC 1.X tone burst with 22 kHz IC controller

High-Z			High-Z		High-Z
STATE			STATE		STATE

VoRx OUTPUT

Vtone signal

Push -pull		Push -pull
Action		Action

1.5DiSEqC 1.X implementation through VoTX and EXTM

If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz tone generator signal available through the VoTX pin to drive the EXTM pin. In this way the

VoTX 22 kHz signal is superimposed to the VoRX DC voltage to generate the LNB output 22 kHz tone (see Figure 6). The internal 22 kHz tone generator, available through the VoTX pin,

must be activated during the 22 kHz transmission by the DSQIN pin or by the TEN bit. The DSQIN internal circuit activates the 22 kHz tone on the VoTX output with 0.5 cycles ± 25 µs delay from the TTL signal present on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal has expired. The VoTX pin internal circuit must be preventively set ON by the TTX function. This can be controlled both through the TTX pin and the I²C bit. As soon as the tone transmission has expired, the VoTX must be disabled by setting the TTX to LOW. The 13/18 V power supply is always provided to the LNB from the VoRX pin.

1.6PDC optional circuit for DiSEqC 1.X applications using VoTX signal on to EXTM pin and 22 kHz tone controlled by DSQIN pin

In some applications, at light output current (< 50 mA), having a heavy LNB output capacitive load, the 22 kHz tone can be distorted. In this case it is possible to add the “Optional” external components described on Section 2.7.

1.722 kHz oscillator

The internal 22 kHz tone generator is factory-trimmed in accordance with current standards and can be selected by the I²C interface TTX bit (or TTX pin) and controlled by the DSQIN pin (TTL compatible), which allows immediate DiSEqC data encoding. If the 22 kHz tone presence is requested in continuous mode, the internal oscillator can be activated by the I²C

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Block diagram and pin function description	AN3352

interface TEN bit. The rise and fall edges are controlled to be in the 5 µs to 15 µs range, 8 µs typ for 22 kHz. The duty cycle is 50% typ., it modulates the DC output with a 0.650 VPP (typ.) amplitude as well as the DSQIN pin.

1.8DiSEqC communication

The following steps must be taken to ensure the correct implementation of the DiSEqC communication:

Figure 4. DiSEqC timing control

LNBout
DSQIN	> 500µs
			> 200 µs
TTX
T0	T1	T2	T3
	DiSEqC Transmit Mode		DiSEqC Receive Mode

●T0: before starting the DiSEqC transmission. The TTX function must be activated (through the TTX pin or TTX I²C bit)

●T1: after 500 µs minimum, the IC is ready to receive the DiSEqC code through the DSQIN pin (or, alternatively, the TEN I²C bit can be set to HIGH to activate the 22 kHz burst)

●T2: when the transmission has elapsed, the TTX function is set to LOW (through the TTX pin or TTX I²C bit) not earlier than 200 µsec after the last falling edge of the DiSEqC code.

1.9Linear post-regulator, modulator and protection

The output voltage selection and the current selection commands join this block, which manages the LNB output function. This block gives feedback to the I²C interface from the diagnostic block, regarding the status of the thermal protection, overcurrent protection, and output settings.

1.10Pin description

The LNBH24L is available in an exposed pad QFN-32 package for surface mount assembly. Figure 5 shows the device pinout and Table 3 briefly summarizes the pin function.

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