This application note complements the information in the STM8TL53xx datasheets by
describing the minimum hardware and software environment required to build an application
around an STM8TL53xx 8-bit microcontroller device.
A brief description of the principal hardware components is given. The power supply, reset
control and ProxSense lines are described in some detail. In addition, some hardware
recommendations are given. This application note also contains detailed reference design
schematics with descriptions of the main components. The STM8 development tools and
software toolchain are common to STM8TL53xx, STM8L, STM8S and STM8A and are
presented in Section 9, and10. Section 11 describes how to set up the STM8 development
environment. Finally, Section 12 provides a list of relevant documentation and online
support resources.
To build an application around an STM8TL53xx device, the application board should provide
the following features:
●Power supply (mandatory)
●Reset management (optional)
●ProxSense line management (optional)
●Debugging tool support: Single wire interface module (SWIM) connector (optional)
2 Power supply
2.1 Power supply overview
The STM8TL53xx needs to be powered by a 1.65 V to 3.6 V external source.
An on-chip power management system provides the constant digital supply to the core logic,
both in normal and low power modes. This ensures that the logic consumes a constant
current level over the voltage range. It is also capable of detecting voltage drops and
generate a reset to avoid erratic behaviour.
The STM8TL53xx device provides:
●One pair of power supply pins (V
DD/VSS
) for the main operating voltage (1.65 V to
3.6 V).
●Another pair of power supply pins (depending of package) (V
DDIO/VSSIO
) for the IOs
(1.65 V to 3.6 V)
The STM8TL53xx device manages the supply voltage needed by the ProxSense interface
by connecting a 1 µF capacitor to the PXS_V
pin (see Figure 1).
REG
6/35Doc ID 18461 Rev 2
AN3342Power supply
MS18954V1
NRST
PXS_VREG
1 μF
V
SS
V
DD
V
DD
V
DDIO
V
SS
V
SSIO
100 nF100 nF
V
SS
1 μF
3.6 V – 1.65 V
(see note 1)
+
+
Figure 1.Power supply
1. The device keeps operating as long as the battery voltage is above 1.65 V and no reset is generated.
Note:The capacitors must be connected as close as possible to the device power supply pins
(V
pins).
DDx
The decoupling capacitor must be connected as close as possible to the ground pins (V
pins).
2.2 Main operating voltages
The STM8TL53xx devices embed an internal voltage regulator for generating the 1.8 V
power supply for the core and peripherals and a second internal voltage regulator providing
a stable power supply (around 1.45 V) for the ProxSense peripheral.
SSx
Doc ID 18461 Rev 27/35
Power supplyAN3342
Via to V
SS
Via to V
DD
Cap.
VDDV
SS
STM8
2.3 Power-on/power-down reset (POR/PDR)
The input supply to the main and low power regulators is monitored by a power-on/powerdown reset circuit. The monitoring voltage begins at 0.7 V.
During power-on, the POR/PDR keeps the device under reset until the supply voltage (V
DD
reach its specified working area. This internal reset is maintained for a period of ~1ms in
order to wait for supply stabilization.
At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a
reset release is defined in the electrical characteristics section of the product datasheets.
A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.
The POR/PDR also generates a reset when the supply voltage drops below the V
POR/PDR
threshold (isolated and repetitive events).
Recommendations
All VDD and VSS pins including V
supplies. These connections, including pads, tracks and vias should have the lowest
possible impedance. This is typically achieved with thick track widths and preferably
dedicated power supply planes in multi-layer printed circuit boards (PCBs).
In addition, the power supply pair should be decoupled with filtering ceramic capacitors (C)
at 100 nF with one chemical C (1..2 µF) in parallel on the STM8TL53xx device. The ceramic
capacitors should be placed as close as possible to the appropriate pins, or below the
appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but
exact values depend on the application needs. Figure 2 shows the typical layout of such a
V
DD/VSS
pair.
Figure 2.Typical layout of V
and V
DDIO
DD/VSS
SSIO
pair
need to be properly connected to the power
)
8/35Doc ID 18461 Rev 2
AN3342Clock management
3 Clock management
The STM8TL53xx has no external clock so no precautionary measures are needed.
3.1 Internal clocks
STM8TL53xx devices have three kinds of internal clock: A high speed internal clock (HSI)
running at 16 MHz, a low speed internal clock (LSI) running at 38 kHz and a high speed
internal clock dedicated to the ProxSense (HSI_PXS) running at 16 MHz. The HSI_PXS
clock runs once the ProxSense is enabled if the LowPower bit is reset. If LowPower bit is set
HSI_PXS clock runs only when an acquisition is being performed.
After reset, the CPU starts at speed of 2 MHz driven by the internal RC (HSI clock signal)
divided by 8.
Doc ID 18461 Rev 29/35
Reset controlAN3342
R
PU
V
DD_IO
Pulse
generator
(min 20 μs)
System reset
Filter
100 nF
External
reset circuit
NRST
MS18949V2
Illegal op code reset
SWIM reset
POR reset
IWDG/WWDG/software reset
Delay
STM8TL53xx
(typ 40 kOhm)
4 Reset control
4.1 Reset management overview
The reset pin is a 3.3 V bidirectional I/O (supplied by V
). After startup it can be
DDIO
programmed by software to be used as a general purpose output.
Its output buffer driving capability is fixed to Iol
= 2 mA @ 0.45 V in the 1.65 V to 3.6 V
MIN
range which includes a ~40 k pull-up. Output buffer is reduced to the n-channel MOSFET
(NMOS). The receiver includes a glitch filter, whereas the output buffer includes a 20 µs
delay.
There are many reset sources, including:
●External reset through the NRST pin
●Power-on reset (POR): During power-on, the POR keeps the device under reset until
the supply voltage (V
●Independent watchdog reset (IWDG)
●Window watchdog reset (WWDG), featuring also software reset.
●SWIM reset: An external device connected to the SWIM interface can request the
) reach the right voltage level.
DD
SWIM block to generate a microcontroller reset.
●Illegal opcode reset: If a code to be executed does not correspond to any opcode or
prebyte value, a reset is generated.
Figure 3 shows a simplified functional I/O reset schematic.
Figure 3.Reset management
4.1.1 Output characteristics
●A valid pulse on the pin is guaranteed with a ≥ 20 ns pulse duration on the internal
●After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed
output buffer.
starting from the falling edge of A (output of the OR between the different reset
sources).
10/35Doc ID 18461 Rev 2
AN3342Reset control
MS18950V1
≥ 20 ns
20 μs pulse stretch min.
Reset requested
A
Pin
MS18951V1
>5 ns>5 ns
>50 ns>50 ns>50 ns
Pad
System
reset
Valid reset
requested
Negative train of glitch filtered
>300 ns
Figure 4.Output characteristics
4.1.2 Input characteristics
●All pulses with a duration less than 50 ns are filtered
●All train/burst spikes with a ratio of 1/10 must be filtered. This means that a negative
spike of up to 50 ns is always filtered, when a 5 ns interval between spikes occurs (ratio
1/10).
●All pulses with duration more than 300 ns are recognized as valid pulses
Figure 5.Input characteristics
Doc ID 18461 Rev 211/35
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