ST AN3342 APPLICATION NOTE

AN3342

Application note

Getting started with STM8TL53xx

Introduction

This application note complements the information in the STM8TL53xx datasheets by describing the minimum hardware and software environment required to build an application around an STM8TL53xx 8-bit microcontroller device.

A brief description of the principal hardware components is given. The power supply, reset control and ProxSense lines are described in some detail. In addition, some hardware recommendations are given. This application note also contains detailed reference design schematics with descriptions of the main components. The STM8 development tools and software toolchain are common to STM8TL53xx, STM8L, STM8S and STM8A and are presented in Section 9, and 10. Section 11 describes how to set up the STM8 development environment. Finally, Section 12 provides a list of relevant documentation and online support resources.

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Contents	AN3342

Contents

1	Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
	2.1	Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.2	Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.3	Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . .	8
3	Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
	3.1	Internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
4	Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	4.1	Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

4.1.1 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1.2 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Hardware reset implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5	ProxSense line management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	5.1	ProxSense line management overview . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	5.2	Hardware ProxSense implementation . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
6	Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	6.1	Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	6.2	Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	6.3	Ground and power supply (VSS, VDD, VSSIO, VDDIO) . . . . . . . . . . . . . . . .	15
	6.4	Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	6.5	Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.6	Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
7	Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	7.1	Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	7.2	Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
8	STM8TL5x firmware libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19

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8.1 STM8TL5x standard peripheral library . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2 STM8TL5x touch sensing library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.3 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9	STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	9.1	Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

9.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.2 RLink and STLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10	STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	10.1	Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	10.2	Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
11	Setting up the STM8 development environment . . . . . . . . . . . . . . . . .		25
	11.1	Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	11.2	Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26

11.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

12	Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
13	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34

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List of tables	AN3342

List of tables

Table 1. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2. SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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AN3342	List of figures

List of figures

Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Typical layout of VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. ProxSense management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Touch key layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. STM8TL5x standard peripheral firmware library online help manual . . . . . . . . . . . . . . . . . 20 Figure 10. STM8TL5x touch sensing firmware library online help manual . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 17. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 18. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Hardware requirements summary	AN3342

1 Hardware requirements summary

To build an application around an STM8TL53xx device, the application board should provide the following features:

●Power supply (mandatory)

●Reset management (optional)

●ProxSense line management (optional)

●Debugging tool support: Single wire interface module (SWIM) connector (optional)

2 Power supply

2.1Power supply overview

The STM8TL53xx needs to be powered by a 1.65 V to 3.6 V external source.

An on-chip power management system provides the constant digital supply to the core logic, both in normal and low power modes. This ensures that the logic consumes a constant current level over the voltage range. It is also capable of detecting voltage drops and generate a reset to avoid erratic behaviour.

The STM8TL53xx device provides:

●One pair of power supply pins (VDD/VSS) for the main operating voltage (1.65 V to 3.6 V).

●Another pair of power supply pins (depending of package) (VDDIO/VSSIO) for the IOs (1.65 V to 3.6 V)

The STM8TL53xx device manages the supply voltage needed by the ProxSense interface by connecting a 1 µF capacitor to the PXS_VREG pin (see Figure 1).

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Figure 1. Power supply

	1 μF	+
VDD		VSS
3.6 V – 1.65 V	+
(see note 1)
	1 μF	100 nF	100 nF
	VSS

NRST

PXS_VREG

VDD

VDDIO

VSSIO

VSS

	MS18954V1
	1. The device keeps operating as long as the battery voltage is above 1.65 V and no reset is generated.
Note:	The capacitors must be connected as close as possible to the device power supply pins
	(VDDx pins).
	The decoupling capacitor must be connected as close as possible to the ground pins (VSSx
	pins).

2.2 Main operating voltages

The STM8TL53xx devices embed an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals and a second internal voltage regulator providing a stable power supply (around 1.45 V) for the ProxSense peripheral.

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Power supply	AN3342

2.3Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power- down reset circuit. The monitoring voltage begins at 0.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltage (VDD) reach its specified working area. This internal reset is maintained for a period of ~1ms in order to wait for supply stabilization.

At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a reset release is defined in the electrical characteristics section of the product datasheets.

A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the VPOR/PDR threshold (isolated and repetitive events).

Recommendations

All VDD and VSS pins including VDDIO and VSSIO need to be properly connected to the power supplies. These connections, including pads, tracks and vias should have the lowest

possible impedance. This is typically achieved with thick track widths and preferably dedicated power supply planes in multi-layer printed circuit boards (PCBs).

In addition, the power supply pair should be decoupled with filtering ceramic capacitors (C) at 100 nF with one chemical C (1..2 µF) in parallel on the STM8TL53xx device. The ceramic capacitors should be placed as close as possible to the appropriate pins, or below the appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 2 shows the typical layout of such a VDD/VSS pair.

Figure 2. Typical layout of VDD/VSS pair

Via to VDD

Via to VSS

Cap.

VDD VSS

STM8

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3 Clock management

The STM8TL53xx has no external clock so no precautionary measures are needed.

3.1Internal clocks

STM8TL53xx devices have three kinds of internal clock: A high speed internal clock (HSI) running at 16 MHz, a low speed internal clock (LSI) running at 38 kHz and a high speed internal clock dedicated to the ProxSense (HSI_PXS) running at 16 MHz. The HSI_PXS clock runs once the ProxSense is enabled if the LowPower bit is reset. If LowPower bit is set HSI_PXS clock runs only when an acquisition is being performed.

After reset, the CPU starts at speed of 2 MHz driven by the internal RC (HSI clock signal) divided by 8.

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Reset control	AN3342

4 Reset control

4.1Reset management overview

The reset pin is a 3.3 V bidirectional I/O (supplied by VDDIO). After startup it can be programmed by software to be used as a general purpose output.

Its output buffer driving capability is fixed to IolMIN = 2 mA @ 0.45 V in the 1.65 V to 3.6 V range which includes a ~40 k pull-up. Output buffer is reduced to the n-channel MOSFET

(NMOS). The receiver includes a glitch filter, whereas the output buffer includes a 20 µs delay.

There are many reset sources, including:

●External reset through the NRST pin

●Power-on reset (POR): During power-on, the POR keeps the device under reset until the supply voltage (VDD) reach the right voltage level.

●Independent watchdog reset (IWDG)

●Window watchdog reset (WWDG), featuring also software reset.

●SWIM reset: An external device connected to the SWIM interface can request the SWIM block to generate a microcontroller reset.

●Illegal opcode reset: If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated.

Figure 3 shows a simplified functional I/O reset schematic.

Figure 3. Reset management

STM8TL53xx

VDD_IO

RPU

External (typ 40 kOhm) reset circuit

NRST

Filter

100 nF

Pulse generator (min 20 μs)

Delay

System reset

Illegal op code reset

IWDG/WWDG/software reset SWIM reset

POR reset

MS18949V2

4.1.1Output characteristics

●A valid pulse on the pin is guaranteed with a ≥ 20 ns pulse duration on the internal output buffer.

●After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed starting from the falling edge of A (output of the OR between the different reset sources).

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Figure 4. Output characteristics

≥ 20 ns

A

20 μs pulse stretch min.

Pin

Reset requested

MS18950V1

4.1.2Input characteristics

●All pulses with a duration less than 50 ns are filtered

●All train/burst spikes with a ratio of 1/10 must be filtered. This means that a negative spike of up to 50 ns is always filtered, when a 5 ns interval between spikes occurs (ratio 1/10).

●All pulses with duration more than 300 ns are recognized as valid pulses

Figure 5. Input characteristics

>5 ns		>5 ns
			>300 ns
>50 ns	>50 ns		>50 ns	Pad
				System
Negative train of glitch filtered			Valid reset	reset
			requested
				MS18951V1

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