ST AN3334 Application note
AN3334
Application note
SPC560P50/SPC56AP60
HW/SW comparison
Introduction
This document addresses HW/SW differences between two 32-bit system-on-chip (SoC)
automotive microcontrollers of the SPC56xP family: SPC560P50 and SPC56AP60 devices.
When designing a system using an SPC560P50 device, HW/SW differences must be
considered for a subsequent and eventual migration to an SPC56AP60 device.
All topics covered in this document refer to RM0022, Rev. 3 (see A.1: Reference document
in Appendix A).
This application note applies to the SPC560P50/SPC56AP60 devices listed in Ta bl e 1 .
\
Table 1. Device summary
Part number Package
SPC560P50L3 LQFP100
SPC560P50L5 LQFP144
SPC56AP60L3 LQFP100
SPC56AP60L5 LQFP144
September 2011 Doc ID 18401 Rev 2 1/31
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Contents AN3334
Contents
1 SPC560P50/SPC56AP60 device comparison . . . . . . . . . . . . . . . . . . . . . 6
2 Device pinout and pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Clock distribution and management . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Code Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Data Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.1 ECC and EEPROM emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.3 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.4 Array integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.5 Margin read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.6 ECC logic check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Peripheral interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 eDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 AIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 LINFlex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6 FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 Junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.8 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.9 CTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/31 Doc ID 18401 Rev 2
AN3334 Contents
7.10 SWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.11 SSCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.12 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.13 FCCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Appendix A Additional information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
A.1 Reference document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
A.2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 18401 Rev 2 3/31
List of tables AN3334
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC560P50/SPC56AP60 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. SPC56AP60 pin multiplexing: added functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. SPC56AP60 pin multiplexing: ADC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Maximum system clock speed for motor control peripherals . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. SPC560P50/SPC56AP60 code Flash memory sectorization comparison . . . . . . . . . . . . . 13
Table 7. SPC560P50/SPC56AP60 data Flash memory feature comparison . . . . . . . . . . . . . . . . . . 14
Table 8. Application view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. External interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. SPC560P50/SPC56AP60 DMA_MUX mapping comparison . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. SPC560P50/SPC56AP60 ADC channels comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. CTU/ADC commands remapping IP on SPC56AP60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. FCCU SPC56AP60/FCU SPC560P50 connections comparison . . . . . . . . . . . . . . . . . . . . 23
Table 14. SPC560P50/SPC56AP60 destructive reset source mapping comparison . . . . . . . . . . . . . 25
Table 15. SPC560P50/SPC56AP60 functional reset source mapping comparison . . . . . . . . . . . . . . 25
Table 16. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/31 Doc ID 18401 Rev 2
AN3334 List of figures
List of figures
Figure 1. SPC560P50/SPC56AP60 clocking architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. CTU/ADC commands remapping IP on SPC56AP60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 18401 Rev 2 5/31
SPC560P50/SPC56AP60 device comparison AN3334
1 SPC560P50/SPC56AP60 device comparison
Table 2. SPC560P50/SPC56AP60 device comparison
(1) (2)
Feature SPC560P50 SPC56AP60
Core Single-core e200z0h Dual-core e200z0h
System clock Up to 64 MHz
Code Flash memory (with ECC) 512 Kbyte 1024 Kbyte
(3)
Data Flash memory / EE (with ECC) 4 × (16 Kbyte) 4 × (16 Kbyte)
SRAM (with ECC) 40 Kbyte 80 Kbyte
FlexCAN (controller area network) 2 × (32 MB) 3 × (32 MB)
Safety port Yes (via second FlexCAN module)
LINFlex 2 × (2 × M/S)
DSPI (deserial serial peripheral interface) 4 × (up to 8/4/4/4 CS) 5 × (up to 8/8/4/4/4 CS)
eTimer 2 × (2 × 6 channels)
ADC (analog-to-digital converters) 2 × 10-bit 1 × 10-bit
(5)
FlexPWM (pulse-width modulation) 1 × (4 × 2 channels) No
CTU (cross triggering unit) 1 × (8 events) 1 × (8 events)
(6)
FlexRay 1 × (32 MB) 1 × (64 MB)
FMPLL (frequency-modulated phase
locked loop)
21
IRC OSC (16 MHz) 1
External interrupts 32
(4)
eDMA (enhanced direct memory access) 1 × (16 channels)
FCU (fault collection unit) Yes Yes
CRC (cyclic redundancy check) unit 1 2
(7)
(8)
Junction temperature sensor Yes No
Debug port JTAG; Nexus class 2+ JTAG; Nexus class 2+
Supply voltage 3.3 V or 5 V single supply with external ballast transistor
Packages LQFP100, LQFP144
LQFP100, LQFP144,
LQFP176
(10)
Temperature range –40 to 125 °C
1. The comparison is made between two different devices both in “Full Featured” configuration.
2. Acronyms used: MB = message buffer, M/S = master/slave, CS = chip select
3. Dual port Flash Controller with 4 buffers per port and support for pre-fetching
4. Increased number of CSs for DSPI_1
5. With pre-sampling capability
6. With ADC commands remapping
7. Enhanced FCCU version
8. Upgraded specification with addition of 8-bits polynom (CRC-8) support and 3rd context
6/31 Doc ID 18401 Rev 2
(9)
AN3334 SPC560P50/SPC56AP60 device comparison
9. Improved debugging capability with data trace capability and increased Nexus throughput available on emulation package
10. Emulation package only. Not available for production
Doc ID 18401 Rev 2 7/31
Device pinout and pin multiplexing AN3334
2 Device pinout and pin multiplexing
Pinout compatibility is very important when designing hardware destined to support multiple
devices within one product family. For this reason, the SPC56AP60 pin multiplexing is based
on that of the SPC560P50 to ensure the pinouts of both devices are fully compatible.
Ta bl e 3 shows the SPC560P50 functions which have been added to the pin multiplexing of
the SPC56AP60 device. Tab le 4 shows ADC_0 channel functions on SPC56AP60 that are
functions of ADC_1 on the SPC560P50 device.
Moreover the pin multiplexing FlexPWM_0 functions are removed on the SPC56AP60 and
the FCCU I/Os replace the SPC560P50 FCU I/Os.
Furthermore the following device enhancements found on the SPC56AP60 need to be taken
into account as they require an adaptation of the external pull-up/down resistor circuit on two
specific pins:
● BCTRL pin:
– SPC560P50: An external pull-down resistor must be implemented
– SPC56AP60: A pull-down resistor is integrated, thus BCTRL pin is not connected
(the same for SPC560P40xx devices).
● RESET pin:
– SPC560P50: is pulled-up
– SPC56AP60: is internally pulled-down increasing the device safety
Table 3. SPC56AP60 pin multiplexing: added functions
Port pin Alternate function Function Peripheral
A[2] ALT2 CS3 DSPI_4
A[6] ALT2 CS2 DSPI_4
A[7] ALT2 CS1 DSPI_4
A[8] ALT2 CS0 DSPI_4
A[9] ALT2 SIN DSPI_4
B[2] ALT2 SOUT DSPI_4
B[3] ALT2 SCK DSPI_4
C[5] ALT2 SCK DSPI_4
C[7] ALT2 SIN DSPI_4
C[8] ALT2 CS1 DSPI_4
C[9] ALT2 CS0 DSPI_4
C[10] ALT2 CS2 DSPI_4
D[6] ALT3 SOUT DSPI_4
G[2] ALT2 SIN DSPI_4
G[3] ALT2 SOUT DSPI_4
G[4] ALT2 SCK DSPI_4
G[5] ALT2 CS0 DSPI_4
8/31 Doc ID 18401 Rev 2
AN3334 Device pinout and pin multiplexing
Table 3. SPC56AP60 pin multiplexing: added functions (continued)
Port pin Alternate function Function Peripheral
G[6] ALT2 CS1 DSPI_4
G[7] ALT2 CS2 DSPI_4
G[8] ALT2 CS3 DSPI_4
A[13] ALT1 CS4 DSPI_1
A[14] ALT3 CS5 DSPI_1
A[15] ALT1 CS6 DSPI_1
B[1] ALT1 CS7 DSPI_1
D[1] ALT1 CS4 DSPI_1
D[2] ALT1 CS5 DSPI_1
D[9] ALT3 CS6 DSPI_1
D[12] ALT3 CS7 DSPI_1
G[5] ALT2 CS4 DSPI_1
G[6] ALT2 CS5 DSPI_1
G[7] ALT2 CS6 DSPI_1
G[8] ALT2 CS7 DSPI_1
D[8] ALT2 RDY Nexus
G[12]
(1)
ALT1 RDY Nexus
C[13] ALT3 RX FlexCAN_1
C[14] ALT3 TX FlexCAN_1
G[9] ALT2 RX FlexCAN_1
G[10] ALT2 TX FlexCAN_1
1. This port pin is not present on SPC560P50
Table 4. SPC56AP60 pin multiplexing: ADC channels
Port pin Function Peripheral
B[13] AN[16] ADC_0
B[14] AN[17] ADC_0
B[15] AN[18] ADC_0
C[0] AN[19] ADC_0
D[15] AN[20] ADC_0
E[0] AN[21] ADC_0
E[8] AN[22] ADC_0
E[9] AN[23] ADC_0
E[10] AN[24] ADC_0
Doc ID 18401 Rev 2 9/31
Device pinout and pin multiplexing AN3334
Table 4. SPC56AP60 pin multiplexing: ADC channels (continued)
Port pin Function Peripheral
E[11] AN[25] ADC_0
E[12] AN[26] ADC_0
10/31 Doc ID 18401 Rev 2
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