ST AN3317 APPLICATION NOTE

AN3317

Application note

PCB guidelines for SPEAr1340

This document applies to the SPEAr1340 embedded microprocessor, and is intended to assist experienced printed circuit board designers.

April 2012

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Contents	AN3317

Contents

1	Power integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	PCB layer stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
3	Via padstack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	3.1	Part orientation and placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
4	Ground and power supply connections . . . . . . . . . . . . . . . . . . . . . . . . .		8
5	DDR memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
	5.1	DRAM power decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	5.2	Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	5.3	Trace length matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	5.4	Return path integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	5.5	Vref routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	5.6	Observability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
6	USB routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	6.1	USB decoupling and reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . .	17
7	TDR test traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
8	Layer order check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
Appendix A		Low-inductance capacitor layout in high-frequency applications 19
	A.1	0402 package compact land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	A.2	0402 package low inductance layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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AN3317	List of tables

List of tables

Table 1. Trace length matching guidelines, balanced-T configuration . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2. USB signal routing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. USB power, ground, and reference guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. 0402 package compact land pattern dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. 0402 packages low inductance layout dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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List of figures	AN3317

List of figures

Figure 1. PCB bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. Routing topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3. Data signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. PCB cross section showing minimum spacing dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. Decoupling capacitor layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. 0402 package compact land pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. 0402 package low inductance layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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AN3317	Power integrity

1 Power integrity

One of the most important requirements of a reliable high-speed memory interface, and most commonly underestimated, is a low impedance, wide bandwidth power supply at the power and ground balls of the devices.

Achieving the necessary performance requires minimizing all parasitic inductances found in power delivery and grounding connections, exploiting various techniques to provide low impedance paths, and attention to controlling plane resonances.

A solid, unbroken ground plane located close to the high-speed devices in the PCB layer stack is critical. The ground plane must not have large gaps anywhere in the area of the interface. Be especially aware of overlapping antipads that can create an extended gap in the internal plane layers.

A power plane closely spaced to the ground plane greatly aids in high-frequency decoupling by providing a low inductance path between a capacitor and the device's power balls.

Use a low-inductance layout for all high-frequency decoupling capacitors.

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PCB layer stacking	AN3317

2 PCB layer stacking

Include a closely spaced power and ground plane pair; a minimum of 6 layers is recommended, as follows:

●Layer 1: signal

●Layer 2: ground plane, unbroken

●Layer 3: power plane and islands, signals

●Layer 4: signal and power routing

●Layer 5: ground plane, unbroken

●Layer 6: signal

Select dielectric thickness to support required signal trace characteristic impedances and power plane capacitance and inductance.

Perform resonance analysis on all plane cavities.

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AN3317	Via padstack

3 Via padstack

Ensure that via padstack dimensions support density requirements.

While meeting PCB fabrication tolerances, make antipad diameters small enough to allow an adequate copper web between the clearance holes of adjacent vias.

3.1Part orientation and placement

To optimize routing and signal integrity, give the DRAM placement and orientation priority over other unassociated components.

Orient DRAM components such that the DQ balls face the controller.

Define a dedicated area for the memory system that encloses all components associated with the memory system and excludes all other components and signal routing.

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