AN3317
Application note
PCB guidelines for SPEAr1340
This document applies to the SPEAr1340 embedded microprocessor, and is intended to
assist experienced printed circuit board designers.
April 2012 Doc ID 18249 Rev 2 1/22
Contents AN3317
Contents
1 Power integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PCB layer stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Via padstack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Part orientation and placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Ground and power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 DDR memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 DRAM power decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Trace length matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Return path integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 Vref routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Observability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 USB routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 USB decoupling and reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 TDR test traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Layer order check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix A Low-inductance capacitor layout in high-frequency applications 19
A.1 0402 package compact land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
A.2 0402 package low inductance layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22 Doc ID 18249 Rev 2
AN3317 List of tables
List of tables
Table 1. Trace length matching guidelines, balanced-T configuration . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2. USB signal routing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. USB power, ground, and reference guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. 0402 package compact land pattern dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. 0402 packages low inductance layout dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 18249 Rev 2 3/22
List of figures AN3317
List of figures
Figure 1. PCB bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. Routing topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Data signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. PCB cross section showing minimum spacing dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Decoupling capacitor layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. 0402 package compact land pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. 0402 package low inductance layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4/22 Doc ID 18249 Rev 2
AN3317 Power integrity
1 Power integrity
One of the most important requirements of a reliable high-speed memory interface, and
most commonly underestimated, is a low impedance, wide bandwidth power supply at the
power and ground balls of the devices.
Achieving the necessary performance requires minimizing all parasitic inductances found in
power delivery and grounding connections, exploiting various techniques to provide low
impedance paths, and attention to controlling plane resonances.
A solid, unbroken ground plane located close to the high-speed devices in the PCB layer
stack is critical. The ground plane must not have large gaps anywhere in the area of the
interface. Be especially aware of overlapping antipads that can create an extended gap in
the internal plane layers.
A power plane closely spaced to the ground plane greatly aids in high-frequency decoupling
by providing a low inductance path between a capacitor and the device's power balls.
Use a low-inductance layout for all high-frequency decoupling capacitors.
Doc ID 18249 Rev 2 5/22
PCB layer stacking AN3317
2 PCB layer stacking
Include a closely spaced power and ground plane pair; a minimum of 6 layers is
recommended, as follows:
● Layer 1: signal
● Layer 2: ground plane, unbroken
● Layer 3: power plane and islands, signals
● Layer 4: signal and power routing
● Layer 5: ground plane, unbroken
● Layer 6: signal
Select dielectric thickness to support required signal trace characteristic impedances and
power plane capacitance and inductance.
Perform resonance analysis on all plane cavities.
6/22 Doc ID 18249 Rev 2
AN3317 Via padstack
3 Via padstack
Ensure that via padstack dimensions support density requirements.
While meeting PCB fabrication tolerances, make antipad diameters small enough to allow
an adequate copper web between the clearance holes of adjacent vias.
3.1 Part orientation and placement
To optimize routing and signal integrity, give the DRAM placement and orientation priority
over other unassociated components.
Orient DRAM components such that the DQ balls face the controller.
Define a dedicated area for the memory system that encloses all components associated
with the memory system and excludes all other components and signal routing.
Doc ID 18249 Rev 2 7/22
Ground and power supply connections AN3317
4 Ground and power supply connections
For proper device operation, it is critical to provide a very low impedance, wide bandwidth
connection to ground and to the voltage supplies. To achieve this, minimize inductance
between the device power and ground balls, and the PCB ground plane and decoupling
network. This guideline also applies to other critical components:
● termination resistors
● decoupling capacitors
● ICs
● multiple ground or power pins from the same IC
Directly connect each ground ball to the PCB ground plane with its own via. Do not share
vias among multiple ground balls.
Exception: the center 10 x 10 ground ball grid should have a fully populated ground via
grid between the balls, and the surface layers may be filled.
Directly connect each power ball to the PCB decoupling network with its own via. Do not
share vias among multiple power balls.
Exception: when multiple power balls are adjacent to each other and are connected to
the same voltage plane, but use the maximum number of vias that space allows.
To avoid cross-contamination of ground or power supplies between different devices (for
example, an IC and a termination resistor), do not share ground connections among multiple
ground or power balls. Give each ball and pin its own via to the ground or power plane. Do
not simply connect power and ground connections to surface layer copper fill areas, which
are not good low impedance paths at high frequencies.
Ball-to-via trace: Connect each ground and power ball to its via with a short, wide trace. Do
not simply connect ground or power balls to surface fill areas; a close, direct via to the
ground or power plane is necessary.
Caution: It is critical to minimize trace length and maximize trace width.
● In the ball field, make trace length less than 1 mm.
● Outside the ball field, make trace length less than 0.25 mm.
● Make trace width wide.
Note: When it is not possible to achieve a close direct trace, a relatively high impedance will result.
Make every effort to minimize trace length, and consider high impedance power connections
only for power connections that require lower bandwidth.
8/22 Doc ID 18249 Rev 2
AN3317 DDR memory interface
5 DDR memory interface
5.1 DRAM power decoupling
A low impedance, wide bandwidth power delivery network (PDN) is critical for the proper
operation of high-speed ICs such as SPEAr and DDR memory. If the PDN impedance is too
high or does not have sufficient bandwidth, logic performance is affected. This results in
ground and rail bounce, and slower rise and fall times of both IO and internal logic, which in
turn results in delayed timing of events. These timing delays from inadequate ground and
power subtract directly from the specified timing budget, which can result in interface failure.
To achieve a low impedance wide bandwidth power delivery network, use the appropriate
decoupling capacitors and capacitor layout. A large portion of the power delivery network’s
frequency spectrum is above the decoupling capacitor’s series resonant frequency, where
they are inductive. The PCB layout for decoupling capacitors is also inductive, and is a
larger inductance than that of the capacitors themselves.
For IC core voltage and high-speed IO supplies (such as DDR) select:
● capacitors with low inherent inductance (small package size)
● a lossy dielectric
● a PCB layout that provides the lowest possible inductance
Use as many capacitors as can fit in the space available. This creates many parallel paths,
reducing the overall inductance seen by the IC. A small capacitor package size and a small
layout enable this.
5.1.1 Capacitors
See also, Appendix A: Low-inductance capacitor layout in high-frequency applications
Package: Use 0402 package size to minimize mounting inductance. The small 0402
package also frees board space, which is essential in high density areas for more
decoupling capacitors and signal routing.
Capacitance: 100 nF or larger
A few capacitors of smaller value will probably be necessary for plane resonance
suppression. The correct values for these depend on the board layout and stack up, and
must be determined individually for each unique PC board.
Dielectric: X7R or X5R dielectric. Do not use Y5V dielectric for decoupling mid-frequency
applications.
Decoupling capacitor layout
Decoupling capacitors layout is extremely important to minimize the induction loop formed
between the capacitor and the IC power and ground balls. Using the layout guidelines that
follow can reduce the capacitor mounting induction loop by 50% or more over a layout with
vias at the end of the capacitor lands. If space allows, a second pair of vias on the opposite
side of the capacitor will reduce the inductance further. Closely follow the decoupling layout
example on
● Place vias on the side of the capacitor lands, not on the ends.
● Locate vias at minimum keepout distance, and connect them to the capacitor lands with
a wide trace – at least as wide as the via pad.
page 10.
Doc ID 18249 Rev 2 9/22
DDR memory interface AN3317
GND
I/O VDD3V3
VDD1V2
DDR PHY VDD1V2
DDR I/O VDD1V5
PLL AVDD2V5
USB VDD3V3
MIPHY VDDPLL2V5
MIPHY VDDPLL1V2
MIPHY VDDR1V2
USB VDD1V2
USB VDD2V5
VDD I/O GMAC
VREG2 3V3 IN
VREG1 3V3 IN
PLL VDD1V2
NAND VDD I/O1
NAND VDD I/O2
● Place vias of opposite polarity as close together as possible (minimum keepout
distance), and separate vias of the same polarity as much as possible.
Decoupling layout example
Figure 1 is an
example of an
effective
low-inductance
decoupling
capacitor
placement and
mounting layout.
Figure 1. PCB bottom layer
5.2 Signal routing
5.2.1 Data signal routing
5.2.2 CLK/CLK# and DQS/DQS# signals
10/22 Doc ID 18249 Rev 2
The guidelines in this section are sufficient for initial routing. Simulate all layouts with IBIS
models to verify adequate timing margins. Modify layouts as necessary to improve the
interface and to comply with all timing parameters. Modifications can include trace length,
width, and spacing, and stack up.
Where routing density allows, increase trace spacing to reduce crosstalk (see also
Section 5.4: Return path integrity).
Do not route any other signals inside or on top of the area reserved for the DDR.
Maintain adequate separation between DDR signals and any other signals.
For traces routed near the edge of a reference plane, keep the trace at least 30 mil from the
edge of the reference plane.
To minimize reflection, ensure that all traces have an impedance of 45 to 55Ω.
Route CLK/CLK# and DQS/DQS# signals as length-matched differential pairs.
AN3317 DDR memory interface
5.3 Trace length matching
Always use trace length equalization to maximize the valid timing window of all signals, and
include the trace lengths inside the SPEAr device package.
A spreadsheet that compensates for the trace lengths inside the substrate is available to
compute the necessary PCB trace length offsets (contact ST).
Fly-by and balanced-T topologies each have advantages and disadvantages. Which
topology is best suited for a particular application must be evaluated on a case-by-case
basis, and take into consideration any other system constraints.
5.3.1 Address, control, and command (A/C/C) signal group,
fly-by configuration
Match trace lengths on the address, control, and command trace segments between the
SPEAr device and the first memory device in the chain.
The spreadsheet mentioned above is the easiest way to compute lengths for the A/C/C
signal group between the SPEAr device and the first memory device.
Match trace lengths for each segment group between memory devices.
Locate terminations beyond the final memory device in the chain.
Length matching is not critical between the final memory device and the termination, but
keep the termination components reasonably near the final memory device.
Ensure that the termination resistors have excellent decoupling.
5.3.2 A/C/C signal group, dual DRAM balanced-T configuration
Balanced-T topology does not require termination resistors (except for clk and nclk).
Balanced-T topology does require equal length branches on all signals within the A/C/C
signal group. Signal integrity degrades rapidly with unequal branch lengths, with serious
negative effects on signal timing.
The spreadsheet mentioned above is the easiest way to compute lengths for the A/C/C
signal group.
Place the differential clock termination resistors near the T junction.
For a single rank dual DRAM configuration, either fly-by or balanced-T topology can be
used.
5.3.3 Data signal groups
Provide matched trace lengths for each 8-bit data slice, DM signals, and DQS/DQSn
signals. It is not necessary to match the trace lengths of one data slice with the trace lengths
of any other data slice, because they are independent from a timing perspective. The
spreadsheet mentioned above is the easiest way to compute lengths for each data slice
signal group.
Figure 2 and Ta bl e 1 describe the length matching guidelines for a dual DRAM topology.
Note: This is a guideline only; perform simulations using IBIS models on the actual PCB layout to
assess signal integrity and timing margin.
Doc ID 18249 Rev 2 11/22
DDR memory interface AN3317
DRAM1
DRAM2
DRAM3
DRAM1
DRAM2
ADDR/CON/COM
DQ[15:0] DQ[31:16] DQ[ECC]
DQ[15:0] DQ[31:16]
Termination
Fly-by topology
ADDR/CON/COM
Equal length
L1
Balanced T topology
L2 L3
SPEAr1340
SPEAr1340
Fly-by topology routes A/C/C signal groups in a daisy chain fashion, with terminations on
all signals after the last DRAM device. Data lane slices are routed to individual DRAM
devices.
Balanced T topology can be used for A/C/C signal groups if only two memory devices are
used.
Figure 2. Routing topologies
Table 1. Trace length matching guidelines, balanced-T configuration
Parameter Description Maximum Unit
t
mm
T
mm2,3
L1+L2, L1+L3 length matching for all signals 15 ps
|L2-L3| length matching tolerance of branches 30 ps
5.3.4 Data signal routing
To simplify the routing of the data signals, it is possible to swap data between data slices.
But it is mandatory to route and connect the SPEAr DDR_DQ0 (ball AF2), DDR_DQ8 (ball
AH3) DDR_DQ16 (ball AE8) and DATA24 (ball AH9) on each LSB DDR data pin.
12/22 Doc ID 18249 Rev 2
AN3317 DDR memory interface
DATA0
ADDR9
nCS0
DATA8
nDQS0
ADDR2
DQS0 BA2
DATA3
ADDR7
DATA2
ADDR3
DATA15
DQS1
DATA7
DATA[15..0]
DATA1
ADDR4
ADDR0
ADDR5
BA0
DATA14
DATA10
DATA9
DQM0
ADDR12
ODT0
ADDR1
DATA5
nDQS1
DATA12
ADDR11
BA1
DATA13
ADDR10
DATA6
DATA4
DATA11
ADDR6
ADDR8
DQM1
ADDR13
ADDR14
nCS1
ODT1
BA2 3,4
ODT0 3,4
nCS0 3 ,4
DATA[15..0]3
DQS03
DQM03
BA0 3,4
DQS13
nDQS03
nDQS13
BA1 3,4
DQM13
nCS1 3 ,4
ODT1 3,4
SPEAr 1340
U1A
DDR_DQ0
AF2
DDR_DQ1
AF4
DDR_DQ2
AF1
DDR_DQ3
AF5
DDR_DQ4
AE1
DDR_DQ5
AE6
DDR_DQ6
AE2
DDR_DQ7
AE4
DDR_DQ8
AH3
DDR_DQ9
AH2
DDR_DQ10
AH6
DDR_DQ11
AG1
DDR_DQ12
AG5
DDR_DQ13
AG2
DDR_DQ14
AH5
DDR_DQ15
AH1
DDR_DQS0p
AE3
DDR_DQS0n
AF3
DDR_DQS1n
AG4
DDR_DQS1p
AH4
DDR_DM0
AE5
DDR_DM1
AG3
DDR_ADDR0
U3
DDR_ADDR1
W2
DDR_ADDR2
V2
DDR_ADDR3
V3
DDR_ADDR4
Y2
DDR_ADDR5
W1
DDR_ADDR6
Y4
DDR_ADDR7
V1
DDR_ADDR8
T1
DDR_ADDR9
U4
DDR_ADDR10
AA3
DDR_ADDR11
V4
DDR_ADDR12
AA2
DDR_ADDR13
Y1
DDR_BA0
Y3
DDR_BA1
W3
DDR_BA2
AA1
DDR_ODT0
AC3
DDR_ODT1
U2
DDR_ADDR14
W4
DDR_CS0n
AB3
DDR_CS1n
U1
ADDR5
ADDR12
ADDR2
ADDR10
ADDR11
ADDR6
ADDR7
ADDR9
ADDR3
ADDR8
ADDR0
ADDR1
ADDR4
DATA0
DATA7
DATA6
DATA5
DATA3
DATA1
DATA2
DATA4
DDR3_VREF
ADDR13
ADDR14
BA2 2,4
BA0 2,4
DQM02
nCAS2,4
nRAS2,4
nWE2,4
nDQS02
nCS02,4
ADDR[14..0]2,4
DQS02
DATA[7..0] 2
BA1 2,4
nCS12,4
DDR3
SDRAM
U2
DATA0
B3
DATA1
C7
DATA2
C2
DATA3
C8
NF/DATA4
E3
NF/DATA5
E8
NF/DATA6
D2
NF/DATA7
E7
ADDR0
K3
ADDR1
L7
ADDR2
L3
ADDR3
K2
ADDR4
L8
ADDR5
L2
ADDR6
M8
ADDR7
M2
ADDR8
N8
ADDR9
M3
ADDR10/AP
H7
ADDR11
M7
ADDR12/#BC
K7
nWE
H3
BA0
J2
BA1
K8
BA2
J3
DM, DM/TDQS
B7
NF, NF/nTDQS
A7
nDQS
D3
DQS
C3
nRAS
F3
nCAS
G3
nCS0
H2
A13
N3
VREF_DQ
E1
VREF_CA
J8
nCS1
H1
A14
N7
ADDR10
BA2
ADDR5
ADDR2
BA1
ADDR4
nWE
ADDR11
ADDR0
ADDR9
ADDR7
BA0
ADDR8
ADDR3
nCS0
ADDR6
ADDR1
ADDR12
DATA9
DATA8
DATA10
DATA12
DATA15
DATA11
DATA14
DATA13
ADDR13
ADDR14
nCS1
DQM12
DATA[15..8] 2
DQS12
nDQS12
DDR3
SDRAM
U3
DATA0
B3
DATA1
C7
DATA2
C2
DATA3
C8
NF/DATA4
E3
NF/DATA5
E8
NF/DATA6
D2
NF/DATA7
E7
ADDR0
K3
ADDR1
L7
ADDR2
L3
ADDR3
K2
ADDR4
L8
ADDR5
L2
ADDR6
M8
ADDR7
M2
ADDR8
N8
ADDR9
M3
ADDR10/AP
H7
ADDR11
M7
ADDR12/#BC
K7
nWE
H3
BA0
J2
BA1
K8
BA2
J3
DM, DM/TDQS
B7
NF, NF/nTDQS
A7
nDQS
D3
DQS
C3
nCS0
H2
A13
N3
nCS1
H1
A14
N7
2
Figure 3. Data signal routing
Doc ID 18249 Rev 2 13/22
DDR memory interface AN3317
5.4 Return path integrity
To minimize signal delays, significant crosstalk, and timing violations, a continuous path for
return current must exist for all DRAM signals.
To simplify return paths, route all signals referenced to a ground plane.
Do not route any DDR3 signals on top of split planes or copper voids.
For traces routed near the edge of a reference plane, keep a minimum of 30 mil between the
trace and the edge of the reference plane.
Signal layer changes
The preferred location for layer change vias is near the signal ball under a device, either
DRAM or SPEAr, enabling a signal return path through the device ground vias and
decoupling capacitors.
If layer changes through a via to a different reference plane are necessary away from the
devices:
● Provide the layer transitions a nearby path for return current.
● If both layers are ground, place a return path ground via less than 1 mm from the signal
via.
● Avoid sharing return current vias; each signal via should have its own nearby return via
(ground via). If multiple signals change layers in close proximity:
– Provide each signal via its own return current via.
– Use a stagger pattern to separate signal vias (and their return current vias) from
other signal vias.
– If routing density prevents a stagger pattern, add as many ground vias as possible
among the signal vias.
5.5 Vref routing
Provide an accurate and quiet Vref to both the dram and the controller. Because of the slope
of the signal, a noisy Vref effectively introduces jitter, which can be a significant source of
jitter-caused timing errors.
Vref is generated by a precision voltage divider.
Recommended: Use 0.1% tolerance resistors.
Place a decoupling capacitor very close (within 1 mm) to the Vref balls.
Use good capacitor layout techniques. Place the voltage divider resistors close to the DRAM
device to minimize trace length, but not so close that they interfere with other critical signal
or power routing.
Do not route the Vref trace near noisy traces or planes.
Do not place a decoupling capacitor at the junction of the resistors – only at the Vref balls.
If the Vref trace length must be long, make the divider resistor value close to 2x the
characteristic impedance of the Vref trace; 150
much power. If a long trace, noise coupling, or both is unavoidable between the DRAM and
the controller, it is preferable to generate a separate Vref for the DRAM and the controller.
14/22 Doc ID 18249 Rev 2
Ω should work well without consuming too
AN3317 DDR memory interface
5.6 Observability
For system validation, timing, signal quality, and debugging, it is important to be able to
observe certain signals. Place test points on any signals or set of signals required for these
purposes.
Always provide a ground via near test points for the probe ground, preferably within 1 mm.
Very small test point pads can be used, preferably just a signal via. If there is insufficient
space, a simple window in the solder mask over a trace provides exposed metal for probing.
Do not create test point structures that significantly degrade signal quality, such as large test
points or stubs.
Locate test points at both ends of a trace (two test points per signal), as close to the device
balls as practical (a via next to the ball is preferable, untented on the bottom layer).
In high-speed interfaces, it is especially important to be able to observe signals at both the
driving and the receiving end of a trace to validate timing parameters and to quantify driver
behavior and reflection. Observing a signal at only one end can hide important features that
are evident at the other end, even with very short traces as is the case in a point-to-point
DDR interface.
In a DDR memory interface, the routing and component density is too high to add test points
on all signals. A subset of DDR signals with test points is a good compromise. Include test
points for the following DDR signals in all designs:
● CLK/nCLK
● DQS/nDQS: All data lanes
● DQ: Select a small number of signals that represent the best and worst signal paths, at
least two DQ signals.
● Address and Control: Select signals of interest that represent the best and worst
signal paths.
Doc ID 18249 Rev 2 15/22
USB routing AN3317
6 USB routing
Ensure that USB signal trace routing follows good high speed PCB rules, and meets the
specifications for differential impedance and maximum trace delay between the connector
and the SPEAr device.
Route USB data traces with the shortest, most direct path possible to their connectors.
USB data traces should have no resistors.
Route USB data traces only over ground planes.
Never route USB data traces across gaps or breaks in the return plane.
Never route USB data traces under other devices or between the pins of other devices.
Widely separate USB data vias from other signal vias.
If USB data traces must transition layers to a different return plane, place ground vias for the
return current very close to the signal vias.
Table 2. USB signal routing constraints
Parameter Description Minimum Typical Maximum Units
Zo
diff
Differential Impedance
Td Dev Trace delay of device port
Td Host Trace delay of host port
Td-match Trace length mismatch
— Number or length of stubs 0
— Number of via transitions 1
— Space to adjacent signal traces
— Space to adjacent area fill
— Space to edge of return plane 20 h
(1)
(1)
(1)
(4)
(2)
81 90 99 Ω
1.0 ns
3.0 ns
0.15
3.8
3h
3h
inch
mm
(3)
(3)
(3)
1. Trace delay between SPEAr device and USB connector (Universal Serial Bus Specification, Revision 2.0)
2. Includes other USB data trace pairs.
3. The same as the units used for h, the thickness of the dielectric separating the trace from the nearest
plane (see Figure 4), which can vary from board-to-board.
4. Do not use guard traces or ground flood or fill adjacent to high speed signal traces.
Figure 4. PCB cross section showing minimum spacing dimensions
16/22 Doc ID 18249 Rev 2
AN3317 USB routing
6.1 USB decoupling and reference resistor
Place decoupling capacitors as close as possible to the power balls (preferably directly
under the power balls) using short, wide connecting traces.
Placing decoupling capacitors at a distance degrades performance, which can result in
interoperability problems and specification compliance violations.
Table 3. USB power, ground, and reference guidelines
Pin Guideline
*vss* Connect all vss pins directly to internal PCB ground plane
*vdd* Connect all vdd pins to 100 nF capacitor under ball using short wide trace
USB_TXRTUNE 43.2 Ω resistor to ground
Doc ID 18249 Rev 2 17/22
TDR test traces AN3317
7 TDR test traces
Add test traces to all PCB designs on all signal layers.
It is simple to add a single trace of nominal impedance between 8 to 15 cm long on each
signal layer (it does not have to be straight) to all designs, and can it always be placed where
it will not impact the functional design, for example, usually along the board perimeter.
Include a test point pattern that matches your TDR probe. Test traces are invaluable in
validating PCB impedance parameters.
8 Layer order check
Include a visual feature (stair step numbered windows) to verify layer ordered in all PCB
layouts. This is most commonly located along one edge of the board.
18/22 Doc ID 18249 Rev 2
AN3317 Low-inductance capacitor layout in high-frequency applications
Appendix A Low-inductance capacitor layout in
high-frequency applications
Figure 5 shows several decoupling capacitor layouts.
Do not use layouts a or b. These layouts have inherently high inductance, and thus a high
impedance at high frequencies.
Use layout d or e for high frequency decoupling applications. These layouts have low
inductance.
● Where space allows, use the 4-via layout (e), which has the lowest inductance but
requires more board area.
● Where space does not permit the 4-via layout, the 2-via layout (d) is a good
compromise.
Use layout c as a last resort when there is no space for either layout d or e.
Figure 5. Decoupling capacitor layouts
A.1 0402 package compact land pattern
An area-efficient compact land pattern facilitates PCB layout of decoupling capacitors.
Figure 6 shows a commonly used land pattern.
Figure 6. 0402 package compact land pattern
Table 4. 0402 package compact land pattern dimensions
Dimension Distance (mil)
A20
B20
C15
Doc ID 18249 Rev 2 19/22
Low-inductance capacitor layout in high-frequency applications AN3317
A.2 0402 package low inductance layout
Figure 2 shows a low inductance layout for a 0402 decoupling capacitor using 2 vias with a
10 mil drill size. Note that:
● Vias are placed close to the lands.
● Vias of opposite polarity are place close together.
● The trace connecting land to via is wide.
Figure 7. 0402 package low inductance layout
Table 5. 0402 packages low inductance layout dimensions
Dimension Distance (mil)
D (land to hole) Typically 8 to 10
E (hole to hole) Typically 30
(1)
(2)
F (trace width) 20
1. The land to hole separation is determined by the PCB fabrication tolerances.
2. Minimize this distance, consistent with PCB fabrication tolerances. If the capacitor is placed within a BGA
ball field, make dimension E the same as the ball pitch.
20/22 Doc ID 18249 Rev 2
AN3317 Revision history
Revision history
Table 6. Document revision history
Date Revision Changes
14-Mar-2012 1.0 Initial release
06-Apr-2012 2.0 Update ST Corporate template
Doc ID 18249 Rev 2 21/22
AN3317
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