AN3316
Application note
SPC560B power and mode management
Introduction
This application note is intended for system designers who require a hardware implementation overview of the low-power modes of the SPC560B product family. It shows how to use the SPC560B product family in these modes and describes how to take power consumption measurements. Example firmware is provided with this application note for implementing and measuring the consumption and wake-up time of the different SPC560B family’s functioning modes.
November 2010 |
Doc ID 18232 Rev 1 |
1/42 |
www.st.com
Contents |
AN3316 |
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Contents
1 |
Power consumption factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
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1.1 |
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
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1.2 |
Dynamic power reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.3 |
Static power reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
7 |
2 |
Device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 9 |
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2.1 |
Modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.2 |
Modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
2.2.1 System modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 Running modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Low Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Key advantages of Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
2.3.1 Transition control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.2 Modules/peripherals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.3 HW failure and error modes management . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Application cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.1 Power-on reset phase (RESET → DRUN) . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.2 Application scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 |
Consumption tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
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3.1 |
Running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
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3.2 |
Low Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
35 |
3.2.1 HALT consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.2 STOP consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.3 STANDBY consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Consumption example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
2/42 |
Doc ID 18232 Rev 1 |
AN3316 |
List of tables |
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List of tables
Table 1. Module configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. Clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Loop divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4. Input divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5. Output divide ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. SPC560B54/6x peripheral clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. Peripherals clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. RUN0 mode consumption table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 9. RUN0 mode consumption example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 10. HALT mode consumption table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11. HALT mode consumption example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 12. STOP mode consumption table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 13. STOP mode consumption example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14. STANDBY mode consumption table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 15. Peripherals consumption table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 16. Peripherals consumption example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 18232 Rev 1 |
3/42 |
List of figures |
AN3316 |
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List of figures
Figure 1. Peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Global clock tree architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. SPC560B54/6x power domain structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. MC_ME mode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Power Domain 0 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Mode transition example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Peripheral configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. HW failure example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Transition (HW start-up) RESET → DRUN (execution from CFlash) . . . . . . . . . . . . . . . . . 18 Figure 10. Node configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. Transition step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. Scenario 2 - finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. Scenario 2 - flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. Scenario 3 - finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15. Scenario 3 - flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Scenario 4 - finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. Scenario 4 - flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18. Power domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19. STANDBY transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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AN3316 |
Power consumption factors |
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As SPC560B is a CMOS digital logic device, total power consumption is:
PTOTAL = PDYNAMIC + PSTATIC
Where:
●PDYNAMIC is the dynamic power contribution that depends on the supply voltage and the clock frequency through following formula:
PDYNAMIC = α · CV2f with:
–C is the CMOS load capacitance
–V is the 5 V supply voltage
–f is the clock frequency
●PSTATIC is the static power contribution that depends mainly on the transistor polarization and leakage as in the following formula:
PSTATIC = ISTATICV
So to minimize total power consumption, it is needed to minimize each dynamic/static contribution which strongly depends on clock frequency and the clock structure implemented.
SPC560B adopts a very smart clock tree architecture in which all the clock sources are not directly routed to peripherals. In fact, a peripheral bus block is located in the middle to divide or disable all the clocks connected to the peripherals to save power consumption.
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System clk |
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So, looking at the global clock tree architecture:
Doc ID 18232 Rev 1 |
5/42 |
Power consumption factors |
AN3316 |
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OSC |
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system_clk |
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div 1 to 32 |
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SWT |
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CLOCK OUT |
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It is possible to decrease power consumption through following features:
●Reduced number of directly clocked lines (see red circle on Figure 2)
●Reduced local clock rates through peripheral bus division (see blue circle on Figure 2)
ModeEntry Module is also structured to help reduce dynamic power consumption as:
●Allows to clock-gate each peripheral independently. So, power saving can be achieved by clock-gating peripherals not used in the application.
●Allows to switch-off the CPU which is the most power-hungry part in the device. For example, while waiting for an ADC conversion to complete.
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AN3316 |
Power consumption factors |
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The two main system/market constraints that influenced SPC560B definition:
●Request for more performance/integration and cost reductions leading to the usage of more and more advanced and small technologies
●Carmakers’ constraints to maintain functions even when the car is switched off with a max consumption of 100µA to 1mA for the overall ECU and depending on its type, BCM, door module etc.
In order to match these two constraints, ST developed the SPC560B with following features:
●Adopting 90nm technology to meet integration/costs but with using a low leakage technology (Leakage minimization)
●Subdividing device into following different PD0, PD1, PD2, PD3 power domains to meet LP function/consumption (Power Segmentation)
These domains are individually disconnected from Power and so eliminates the leakage from the areas they are turned off.
Vreg
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power gating
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LV = Low Voltage(1.2V on SPC560B) |
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RAM Domain 2 |
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HV = High Voltage(3.3V on SPC560B) |
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PD = Power Domain |
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RD = RAM Power Domain |
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PCU = Power Control Unit |
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RGM = Reset Generation Module |
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CGM = Clock Generation Module |
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CGL = Clock Gating Logic |
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ME = mode Entry unit |
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RAM Domain 1 |
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ZO core |
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API/ |
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Wake-up |
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Reset & |
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128KHz |
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16 Mhz |
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PCU |
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8K |
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32KHz |
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RTC |
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Logic |
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XTAL |
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Sampler |
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Doc ID 18232 Rev 1 |
7/42 |
Power consumption factors |
AN3316 |
|
|
Notice that Power Domains shown on Figure 3 are related to SPC560B54/6x, where:
●Power Domain PD0:
–always on
–wakeup peripheries like the CAN sampler, the RTC, API, etc.
–minimum RAM segment (8 K)
●Power Domain PD1:
–contains all cores and the majority of peripherals
–can be turned off in STOP or STANDBY modes
–must be turned on in RUN modes (although there is a clock gating option for all peripherals and also a WAIT instruction for the cores to reduce power)
●Power Domain PD2:
–additional RAM segment (24 K)
●Power Domain PD3:
–additional RAM segment (64 K)
–not supplied in standby mode, but implemented to use it in other LP-modes to reduce leakage
On the other hand, to minimize static power contribution on application side, user should
●Turn-off CPU when possible, using the following autonomous "smart" peripherals:
–API — Autonomous Periodic Interrupt that allows device to recover from very low power state at selected time intervals
–RTC — Real Time Clock that offers precision time keeping functionality in very low power state
–ADC — Analog Digital Converter with continuous conversion while running in low power and triggering wake-up when signal reaches certain level
–DMA — Direct Memory Access that allows data transfer between peripherals minimising CPU activity
–SCI — Intelligent LIN management that minimizes CPU interrupts and CPU clock
8/42 |
Doc ID 18232 Rev 1 |
AN3316 |
Device modes |
|
|
Mode Entry Module is a smart module implemented in SPC560B that intends at saving total device consumption. In fact it allows to manage different level of low-power modes that can reach, at minimum, few µA.
Mode Entry (MC_ME) is a SPC560B module that allows the user to centralize the control of all device modes and related modules/parameters within a unique module. In this way, it simplifies the implementation of mode management and thus increases its robustness.
The MC_ME is based on several device modes corresponding to different usage models of the device. Each mode is configurable and can define a policy for energy and processing power management to fit particular system requirements. An application can easily switch from one mode to another depending on the current needs of the system.
SPC560B modes can be subdivided in the following groups:
●System modes:
All the modes (RESET, TEST, SAFE, DRUN) in which the device must be initialized and properly configured
●Running modes:
All the modes (RUN0:3) used to obtain the full device performance
●Low Power modes:
All the modes (HALT, STOP, STANDBY) used to minimize the power consumption
Doc ID 18232 Rev 1 |
9/42 |
Device modes |
AN3316 |
|
|
SYSTEM MODES |
|
USER MODES |
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recoverable |
RUN0 |
software |
hardware |
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failure |
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request |
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HALT0 |
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SAFE |
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RUN1 |
RESET |
DRUN |
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RUN2 |
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STOP0 |
non-recoverable |
TEST |
RUN3 |
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faliure |
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STANBY0 |
2.2.1System modes
RESET mode
This is a chip-wide virtual mode during which the application is not active.
The system remains in this mode until all resources are available for the embedded software to take control of the device. It manages hardware initialization of chip configuration, voltage regulators, oscillators, PLLs, and Flash modules.
DRUN mode
This is the entry mode for the embedded software.
It provides full accessibility to the system and enables the configuration of the system at startup. It provides the unique gate to enter USER modes.
10/42 |
Doc ID 18232 Rev 1 |
AN3316 |
Device modes |
|
|
SAFE mode
This is a chip-wide service mode which may be entered on the detection of a recoverable error. It forces the system into a pre-defined safe configuration from which the system may try to recover.
TEST mode
This is a chip-wide service mode which is intended to provide a control environment for device self-test. It may enable the application to run its own self-test like Flash checksum.
RUNx (x=0:3) modes
These are software running modes where most processing activity is done. These modes are intended to be used by software to execute full performance application routines.
The availability of 4 running modes allow to enable different clock and power configurations of the system with respect to each other.
SPC560B device supports WAIT instruction to stop the core with the capability to restart with very short latency (< 4 system clocks)
HALT mode
This mode is intended as a first level low-power mode in which the platform is stopped but system clock can remain the same as in running mode. This is a reduced-activity low-power mode during which the clock to the core is disabled. It can be configured to switch off analog peripherals like PLL, Flash, main regulator etc. for efficient power management at the cost of higher wakeup latency.
STOP mode
This mode is intended as an advanced low-power mode during which the clock to the platform is stopped. It may be configured to switch off most of the peripherals including oscillator for efficient power management at the cost of higher wakeup latency.
STANBY mode
This is a reduced-leakage low-power mode in which only PD0 is connected and power supply is cut off from most of the device. Wakeup from this mode takes a relatively long time, and content is lost or must be restored from backup.
Doc ID 18232 Rev 1 |
11/42 |
Device modes |
AN3316 |
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Part of |
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PD0 |
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(Always On |
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Magic carpet |
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domain) |
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HV |
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API/ |
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Wake-up |
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RESET & |
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128KHz |
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16 MHz |
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PCU |
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RGM |
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8K |
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32KHz |
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CAN |
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RTC |
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Logic |
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RAM |
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Sampler |
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Wake-up |
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IRC |
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IRC |
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XTAL |
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vector |
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The purpose of the Mode Entry (ME) is to centralize the control of all device modes and related parameters within a unique module.
Following main advantages:
●Controls the target mode’s parameters and mode transition without CPU intervention (see Section 2.3.1: Transition control)
●Power modes managment centralaized (see Section 2.3.2: Modules/peripherals configuration)
●Provides a SAFE mode to manage HW failure (see Section 2.3.3: HW failure and error modes management)
Mode transition is performed by writing ME_MCTL register twice:
●1st write: TARGET_MODE + KEY
●2nd write: TARGET_MODE + INVERTED KEY
Once the double writing is done, the complete transition could be triggered by following bits:
●S_MTRANS bit of Global Status Register (ME_GS)
–S_MTRANS = 0 (Transition not active)
–S_MTRANS = 1 (Transition ongoing)
●I_MTC bit of Interrupt Status Register (ME_IS)
–I_MTC = 0 (No transition complete)
–I_MTC = 1 (Transition complete)
Note: |
Bit I_MTC is not set in case of transition to low power modes (HALT / STOP) |
Either modules or peripherals are managed by ME.
12/42 |
Doc ID 18232 Rev 1 |
AN3316 |
Device modes |
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Modules management
Each mode has a configuration register (ME_XXX_MC) that allows to configure the following modules:
●Output Configuration
For some modes it is possible to put the IO in power-down status (PDO), forcing outputs of pads to high impedance state or switching off the pads’ power sequence driver
●Main Voltage Regulator (MVREG) Configuration
For some modes it is possible to switch-off the MVREG in order to minimize the consumption
●FLASHs Configuration
For some modes it is possible to configure the code and data Flash in normal, low power and power down
●Clocks Configuration
ME module is in charge of:
–Main XOSC switching on/off
–IRC fast switching on/off
–FMPLL switching on/off
–System Clock selecting
Not all modules can be configured in each mode. Following a table that describes all the possible modules configurations for each mode:
Table 1. |
Module configuration(1) |
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Module |
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Mode |
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PDO |
MVR |
DATA FLASH |
CODE FLASH |
PLL |
OSC |
IRC |
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RESET |
Reset |
Off |
On |
Normal |
Normal |
Off |
Off |
On |
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TEST |
User |
√ |
On |
√ |
√ |
√ |
√ |
√ |
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Reset |
Off |
Normal |
Normal |
Off |
Off |
On |
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SAFE |
User |
√ |
On |
Normal |
Normal |
Off |
Off |
On |
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Reset |
On |
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DRUN |
User |
Off |
On |
√ |
√ |
√ |
√ |
On |
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Reset |
Normal |
Normal |
Off |
Off |
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RUNx |
User |
Off |
On |
√ |
√ |
√ |
√ |
On |
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Reset |
Normal |
Normal |
Off |
Off |
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HALT |
User |
Off |
√ |
√ |
√ |
√ |
√ |
√ |
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Reset |
On |
Low Power |
Low Power |
Off |
Off |
On |
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STOP |
User |
√ |
√ |
√ |
√ |
Off |
√ |
√ |
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Reset |
Off |
On |
Power Down |
Power Down |
Off |
On |
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STBY |
User |
Off |
Off |
Power Down |
Power Down |
Off |
Off |
√ |
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Reset |
On |
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1.√ : module configurable
gray cell: module not configurable
Doc ID 18232 Rev 1 |
13/42 |