ST AN2484 APPLICATION NOTE
AN2484
Application note
STOTG04 in power down mode
Introduction
A standard USB bus is based on a host-peripheral topology, where the host is typically a PC
which manages the peripherals connected to the bus.
The need to interconnect mobile devices is the purpose for the development of the "OTG
supplement to the USB 2.0 specification" the main target of which is to add host functionality
to devices originally intended as peripherals in USB 2.0.
Battery-powered equipment, such as PDAs and mobile phones, are typical applications for
USB OTG, and therefore for the STOTG04 USB OTG transceiver.
Because increasing battery life is a constant challenge in these products, the STOTG04
implements a power-down operating mode to decrease power consumption. The amount of
current drawn by the transceiver in this mode is dependent on its configuration. This
document is intended to assist in the programming of the STOTG04's internal registers to
achieve minimum power consumption.
April 2007 Rev 1 1/10
www.st.com
Contents AN2484
Contents
1 STOTG04 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Driver biasing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2/10
AN2484 STOTG04 Description
1 STOTG04 Description
The STOTG04 is a LS/FS USB OTG transceiver integrating a charge pump for V
generation, an ID line detector and interrupt generator, V
comparators, and integrated
BUS
BUS
voltage
switchable data line pull-up/pull-down resistors. The device is also capable of UART and
Audio Mode operation (refer to AN2148 for more information regarding STOTG04 in an
Audio Carkit Environment).
The device can be fully controlled through programming some internal registers through the
2
I
C serial bus. Figure 1 shows a simplified block diagram which can be useful to identify the
internal blocks described in the paragraphs that follow.
Refer to the STOTG04 datasheet for a detailed description of each block.
Figure 1. STOTG04 block diagram
VBAT
ADR_PSW
SCL
SDA
SPEED
SUSPEND
I2C
Interface
Oscillator
Charge
Pump
CAP2CAP1
VBUS
VBAT
Bandgap
Reference
OE_TP_INT/
DAT_VP
SE0_VM
RCV
VP
VM
INT/
RESET/
and
Register Set
Control Logic
VBAT
VTRM
VBAT
Voltage
Regulator
D+
D-
VTRM
ID
3/10
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