ST AN2476 Application note
AN2476
Application note
STR75x low power modes
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the low power modes of the STR75x product family. It describes
how to use the STR75x product family and details the components of supply circuitry, clock
systems, register settings and low power management in order to optimize the use of
STR750 in applications where low power is key.
July 2007 Rev 2 1/49
www.st.com
Contents AN2476
Contents
1 Power supply and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Power scheme 1: single external 3.3V power source . . . . . . . . . . . . . . . 5
1.3.2 Power scheme 2: dual external 3.3V and 1.8V power sources . . . . . . . . 7
1.3.3 Power scheme 3: single external 5.0V power source . . . . . . . . . . . . . . . 8
1.3.4 Power scheme 4: dual external 5.0V and 1.8V power sources . . . . . . . . 9
1.4 Main voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Low power voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Regulator startup monitor (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7.1 Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7.2 Peripheral clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.8.1 Low power bit writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.8.2 SLOW mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.8.3 PCG mode: peripherals clocks gated mode . . . . . . . . . . . . . . . . . . . . . 16
1.8.4 WFI mode: Wait For Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.8.5 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.8.6 STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8.7 Auto-Wake-Up (AWU) from low power mode . . . . . . . . . . . . . . . . . . . . . 25
2 STR750 library low power mode functions . . . . . . . . . . . . . . . . . . . . . . 26
2.1 MRCC_CKSYSConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2 MRCC_HCLKConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 MRCC_CKTIMConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.4 MRCC_PCLKConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 MRCC_EnterWFIMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6 MRCC_EnterSTOPMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.7 MRCC_EnterSTANDBYMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.8 MRCC_PeripheralClockConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/49
AN2476 Contents
3 Operating measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Setup board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.1 Measurement with STR750_EVAL Board . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.2 Measurements with Uniboard QFP 100 in single supply (3.3V or 5V) . . 34
3.2 Software provided with this application note . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.3 WFI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Measurement and typical value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
Power supply and clocks AN2476
1 Power supply and clocks
1.1 Introduction
The device can be connected in any of the following schemes, depending on the application
requirements:
● Power scheme 1: Single external 3.3V power source
● Power scheme 2: Dual external 3.3V and 1.8V power sources
● Power scheme 3: Single external 5.0V power source
● Power scheme 4: Dual external 5.0V and 1.8V power sources
1.2 Power supplies
The device has five power pins:
● V
STANDBY mode.
Two embedded regulators are available to supply the internal 1.8V digital power:
● V
SRAM and Flash: 1.8V ± 0.15V.
● V
V
and V
18
The Main Voltage Regulator (MVREG) supplies V
of 1.8V.
: power supply for I/Os (3.3V ±0.3V or 5V ±0.5V). Must be kept on, even in
DD_IO
(pins V
18
: Backup Power Supply for STANDBY or STOP Mode
18_BKP
18_BKP
and V18 which are internally shorted): Power Supply for Digital,
18REG
are normally generated internally by the embedded regulators:
18
and V
. It delivers a power supply
18_BKP
The Low Power Voltage Regulator (LPVREG) can supply V
or V18 in STOP or
18_BKP
STANDBY mode (see Section 1.8: Low power modes on page 14). It delivers a power
supply of 1.6V ± 0.2V.
When the embedded regulators are used, the Main Digital part of the chip (V
powered off (meaning V
(V
18_BKP
).
It is also possible to supply V
left hi-Z) while keeping the backup circuitry powered on
18
18
and V
18_BKP
externally.
) can be
18
Two sensitive analog blocks have dedicated power pins:
● V
● V
DDA_PLL
DDA_ADC
: Analog Power supply for PLL (must have the same voltage level as V
: Analog Power supply for ADC (must have the same voltage level as V
DD_IO
DD_IO
)
)
4/49
AN2476 Power supply and clocks
1.3 Power supply schemes
1.3.1 Power scheme 1: single external 3.3V power source
In this configuration, the internal voltage regulators are switched on by forcing the
VREG_DIS pin to low level. The V
supply required for the backup circuitry are generated internally by the Main Voltage
Regulator or the Low Power Voltage Regulator (depending on the selected low power
mode). This scheme has the advantage of requiring only one power source. Refer to
Figure 1 on page 5.
At power-up and during NORMAL mode (all operating modes except STOP and STANDBY
Modes):
● The Main Voltage Regulator powers both V
and the V
BACKUP
supply required for the backup circuitry.
● The Low Power Regulator is not used
Figure 1. Power supply scheme 1 (single 3.3V supply VREGDIS=0) in NORMAL
mode
supply required for the kernel logic and the V
CORE
supply required for the kernel logic
CORE
BACKUP
33nF
3.3V
+/-0.3V
1µF
10µF
V
18_BKP
V
SS_BKP
VREG_DIS
V
V
SS18
V
18REG
V
SS18
V
DD_IO
1µF
V
SS_IO
GP I/Os
V
DD_PLL
V
SS_PLL
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
NORMAL
MODE
LOW POWER
VOLTAGE
VIO=3.3V
3.3V
REGULATOR
V
18
MAIN
VOLTAGE
REGULATOR
OUT
IN
PLL
18
V
LPVREG
V
MVREG
~1.4V
= 1.8V
I/O LOGIC
POWER
SWITCH
V
BACKUP
V
CORE
BACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
V
DD_ADC
V
SS_ADC
ADC
3.3V
ADC
IN
5/49
Power supply and clocks AN2476
In STANDBY mode (see Section 1.8.6: STANDBY mode on page 22):
● the Main Voltage Regulator is disabled (output V
● the Low Power Voltage Regulator powers the backup circuitry.
is hi-Z), the kernel is powered-off
CORE
Figure 2. STANDBY mode in power supply scheme 1
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
V
18_BKP
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
UNPOWERED
V
DD_IO
V
STANDBY
MODE
LOW POWER
VOLTAGE
REGULATOR
V
18
V
LPVREG
~1.4V
POWER
SWITCH
BACKUP
~1.6V
= HI-Z
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
OFF
MAIN
VOLTAGE
REGULATOR
V
MVREG
= HI-Z
V
CORE
In STOP mode (where all clocks are disabled), it is possible to disable the Main Voltage
Regulator and to power both the backup circuitry and the kernel logic with the Low Power
Voltage Regulator (see Section 1.8.5: STOP mode on page 18)
Figure 3. Stop mode in power supply scheme 1 when MVREG is off
V
18_BKP
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
DISABLED (NO CLOCKS)
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
V
V
DD_IO
V
STOP
LOW POWER
VOLTAGE
REGULATOR
18
OFF
MAIN
VOLTAGE
REGULATOR
V
LPVREG
V
MVREG
= HI-Z
MODE
POWER
SWITCH
BACKUP
V
CORE
6/49
AN2476 Power supply and clocks
1.3.2 Power scheme 2: dual external 3.3V and 1.8V power sources
In this configuration, the internal voltage regulators are switched off by forcing the
VREG_DIS pin to high level. This scheme has the advantage of saving power consumption
when the 1.8V power supply is already available in the application. V
provided externally through the V
18REG
, V18 and V
18_BKP
power pins.
VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the Low
Power Voltage Regulator.
18
and V
18_BKP
are
All digital power pins (V
1.8V power supply source. Internally, V
18REG
, V18 and V
CORE
) must be externally shorted to the same
18_BKP
and V
BACKUP
are shorted by the Power Switch.
In this scheme, STANDBY Mode is not available.
Figure 4. Power supply scheme 2 (3.3V and 1.8V supplies, VREGDIS=1)
V
18_BKP
V
SS_BKP
V
DD_IO
3.3V
+/-0.3V
VREG_DIS
V
18REG
1.8V
V
SS18
V
DD_IO
V
SS_IO
GP I/Os
OFF
LOW POWER
VIO=3.3V
VOLTAGE
REGULATOR
OFF
MAIN
VOLTAGE
REGULATOR
OUT
IN
V
18
V
LPVREG
V
MVREG
I/O LOGIC
POWER
SWITCH
V
BACKUP
V
CORE
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
BACKUP
CIRCUITRY
KERNEL
(CORE &
DIGITAL &
MEMORIES)
V
DD_PLL
V
SS_PLL
V
DD_ADC
V
SS_ADC
ADC
3.3V
PLL
3.3V
ADC
IN
NOTE : THE EXTERNAL 3.3V POWER SUPPLY MUST ALWAYS BE KEPT ON
7/49
Power supply and clocks AN2476
1.3.3 Power scheme 3: single external 5.0V power source
This power scheme is equivalent to Power Scheme 1 with the exception that:
● The external power supply is 5.0V +/-0.5V instead of 3.3V
● USB functionality is not available
STANDBY mode is supported in this scheme.
Figure 5. Power supply scheme 3 (single 5.0V supply VREGDIS=0) in NORMAL
mode
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
NORMAL
MODE
~1.4V
LPVREG
POWER
SWITCH
= 1.8V
V
BACKUP
V
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
KERNEL LOGIC
CORE
MEMORIES)
BACKUP
(CPU &
DIGITAL &
33nF
5.0V
+/-0.5V
1µF
10µF
V
18_BKP
V
SS_BKP
VREG_DIS
V
V
SS18
V
18REG
V
SS18
V
DD_IO
1µF
V
SS_IO
LOW POWER
VOLTAGE
18
REGULATOR
V
18
MAIN
VOLTAGE
REGULATOR
V
V
MVREG
GP I/Os
V
DD_PLL
V
SS_PLL
V
DD_ADC
V
SS_ADC
ADC
VIO=5.0V
OUT
IN
I/O LOGIC
5.0V
PLL
5.0V
ADC
IN
8/49
AN2476 Power supply and clocks
1.3.4 Power scheme 4: dual external 5.0V and 1.8V power sources
In this configuration, the internal voltage regulators are switched off, by forcing the
VREG_DIS pin to high level. This scheme has the advantage of saving power consumption
when the 1.8V power supply is already available in the application and providing 5V I/O
capability. V
power pins.
VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the Low
Power Voltage Regulator.
18
and V
18_BKP
are provided externally through the V
18REG
, V18 and V
18_BKP
All digital power pins (V
1.8V power supply source. Internally, V
18REG
, V18 and V
18_BKP
CORE
) must be externally shorted to the same
and V
BACKUP
are also shorted by the power
switch shown in Figure 6: Power supply scheme 4 (5V and 1.8V supplies, VREGDIS=1) on
page 9.
In this scheme:
● STANDBY mode is not available
● USB functionality is not available
Figure 6. Power supply scheme 4 (5V and 1.8V supplies, VREGDIS=1)
V
18_BKP
V
SS_BKP
V
DD_IO
5.0V
+/-0.5V
VREG_DIS
V
18REG
1.8V
V
SS18
V
DD_IO
V
SS_IO
OFF
LOW POWER
VIO=5.0V
VOLTAGE
REGULATOR
OFF
MAIN
VOLTAGE
REGULATOR
V
18
V
LPVREG
V
MVREG
POWER
SWITCH
V
BACKUP
V
CORE
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
KERNEL
(CORE &
DIGITAL &
MEMORIES)
GP I/Os
V
DD_PLL
V
SS_PLL
V
DD_ADC
V
SS_ADC
ADC
OUT
IN
5.0V
PLL
5.0V
ADC
IN
NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON
I/O LOGIC
9/49
Power supply and clocks AN2476
1.4 Main voltage regulator
In power scheme 1 or 3 (see Section 1.3: Power supply schemes on page 5) the Main
Voltage Regulator provides the 1.8V power supply starting from V
DD_IO
. The V
18REG
pin
must be connected to external stabilization capacitors (min. 10 uF Tantalum, low series
resistance, and 33nF ceramic). The V
capacitor of 1µF must be added on the V
pin must be left unconnected. A decoupling
18
pin which is closest to the V
DD_IO
18REG
pin. Refer
to the diagram in the application note, AN2419, STR75x hardware development getting
started.
1.5 Low power voltage regulator
In power scheme 1 or 3 (see Section 1.3: Power supply schemes on page 5) the Low Power
Voltage Regulator is used in STANDBY Mode and in STOP Mode (when MVREG is OFF in
STOP mode).
The V
pin must be connected to an external stabilization capacitor of 1µF. It
18_BKP
generates a non-stabilized and non-thermally-compensated voltage of approximately 1.4V.
The output current is enough to power the backup circuitry (RTC and Wakeup Logic) or the
V
supply required for the kernel logic in STOP mode (with the low power control
CORE
parameters FLASH and OSC4M OFF, see Section 1.8.5: STOP mode on page 18).
● In STANDBY mode, it provides the power supply starting from V
to the backup
DD_IO
circuitry while the Kernel Logic is un-powered.
● In STOP mode, if you program the LP_PARAM13 control bit (MVREG OFF) to disable
the Main Voltage Regulator, the Low Power Voltage Regulator powers the whole digital
circuitry, saving the static consumption of the Main Voltage Regulator (~100µA typical).
1.6 Regulator startup monitor (RSM)
The Main Voltage Regulator and the Low Power Voltage Regulator have an internal
Regulator Startup Monitor (RSM) which monitors the regulated power supply.
At power-up, the RSM extends the assertion of the RESET until the regulators are operating
(until V
If there is a drop in the regulated power supply, the RSM automatically generates a RESET.
This enhances the security of the system by preventing the MCU from going into an
unpredictable state.
Note: An external reset circuit must be used to provide the RESET at VDD_IO power-up. It is not
sufficient to rely on the RESET generated by the RSM in this case. This is because RSM
operation is guaranteed only when VDD_IO is within the specification (minimum 3.0V).
18_BKP
and V18 are at the right level).
When regulators are not used (VREG_DIS pin is tied to high level), the RSM is disabled.
10/49
AN2476 Power supply and clocks
1.7 Clocks
The Clock controller provides the internal clocks needed by the different parts of the MCU:
● HCLK clocks all the peripherals mapped on the AHB bus
● PCLK clocks all the peripherals mapped on the APB bus
● CK_TIM clocks several timer counters independently from the APB clock
● CK_USB clocks the USB interface kernel
1.7.1 Clock overview
Figure 7. Clock overview
~5 MHz
FREEOSC
4 MHz
PLL
UP TO 64 MHz
48 MHz
NCKD FLAG
4/8MHz
XT1
XT2
XRTC1
XRTC2
USB_CK
DIV2
1
0
OSC4M
OSC32K
LPOSC
CLOCK
DETECTOR
/128
32 kHz
300 kHz
NCKD FLAG
RTC
ALARM
WAKE UP
CK_SYS
AHB & APB
DIVIDERs
HCLK
UP TO 64 MHz
PCLK
UP TO 32 MHz
CK_TIM
UP TO 64 MHz
CK_USB
48 MHz
11/49
Power supply and clocks AN2476
Several on-chip oscillators can feed the MCU system clock (CK_SYS) from which the HCLK
and PCLK derive:
● FREEOSC: Internal Free Running Oscillator providing a clock of approximately 5 MHz,
also used as emergency clock. It consists of the internal VCO of the PLL configured in
free running mode
● OSC4M: 4 MHz Main Oscillator, based on:
– a 4 MHz Crystal/Ceramic oscillator connected to XT1/XT2
– or an 8 MHz Crystal/Ceramic oscillator to XT1/XT2 followed by an embedded
divider by 2
– or external clock connected to XT1
which can be multiplied by the PLL to provide a wide range of frequencies (up to 64
MHz)
● OSC32K: 32.768kHz Oscillator (Crystal or Ceramic oscillator) which can drive either
the system clock and/or the RTC.
● LPOSC: Internal Low Power RC Oscillator providing a clock around 300 kHz which can
drive either the system clock and/or the RTC.
Several configurable dividers provide a high degree of flexibility to the application in the
choice of the APB or AHB frequency, while keeping a fixed frequency value for the USB
clock (48 MHz).
The Clock Detector (CKD) protects the Microcontroller against OSC4M or external clock
failures.
The RTC provides calendar, alarm and wake-up functions and can be clocked by any of the
oscillators other than FREEOSC.
12/49
AN2476 Power supply and clocks
1.7.2 Peripheral clock scheme
Figure 8. Peripheral clock Scheme
CK_SYS
(UP TO 64MHz)
CK_USB (48MHz)
AHB PRESC
/(1,2,4,8)
APB PRESC
/(1,2,4,8)
CK_TIM
CK_TIM
HCLK (UP TO 64MHz)
CK_TIM (UP TO 64MHz)
/2
PCLK (UP TO 32MHz)
PCLK
PCLK
PCLK
MRCC_PCLKEN(5)
CK_TIM
PCLK
MRCC_PCLKEN(4)
CK_TIM
PCLK
PCLK
MRCC_PCLKEN(3)
CK_TIM
PCLK
MRCC_PCLKEN(2)
CK_TIM
PCLK
MRCC_PCLKEN(1)
CK_TIM
HCLK
PCLK
ATM7TDMI-S
GP-DMA
7-BIT
PRESC
REGISTERS
PWM
REGISTERS
SRAM
FLASH
SMI
REGISTERS
SMI_CK
EIC
MRCC
REGISTERS
16-BIT
PRESC
TIM2
REGISTERS
16-BIT
PRESC
TIM1
REGISTERS
16-BIT
PRESC
TIM0
REGISTERS
16-BIT
PRESC
TB
16-BIT
PRESC
UP TO 48MHz
16-BIT
COUNTER
16-BIT
COUNTER
16-BIT
COUNTER
16-BIT
COUNTER
16-BIT
COUNTER
MRCC_PCLKEN(22)
MRCC_PCLKEN(21)
MRCC_PCLKEN(20)
MRCC_PCLKEN(14)
PCLK
MRCC_PCLKEN(13)
MRCC_PCLKEN(9)
MRCC_PCLKEN(18)
MRCC_PCLKEN(16)
PCLK
MRCC_PCLKEN(0)
MRCC_PCLKEN(28)
MRCC_PCLKEN(24)
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
CK_USB (48MHìz)
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PRESCALER
/1,2,4,6,8,10,12,14
UART2
REGISTERS
DIVIDER
16-BIT INTEGER
/16
6-BIT FRACTIONAL
UART1
REGISTERS
DIVIDER
16-BIT INTEGER
/16
6-BIT FRACTIONAL
UART0
REGISTERS
DIVIDER
16-BIT INTEGER
/16
6-BIT FRACTIONAL
SSP1
REGISTERS
/(CPSDVR(1+SCR)
CPSDVR=2,4,6,8,10,12,...,254 (even number)
SCR=0,1,2,3,.., 255
- IN MASTER MODE: BIT RATE MAX = PCLK/2
- IN SLAVE MODE: BIT RATE MAX = PCLK/12
/(CPSDVR(1+SCR)
CPSDVR=2,4,6,8,10,12,...,254 (even number)
SCR=0,1,2,3,.., 255
- IN MASTER MODE: BIT RATE MAX = PCLK/2
- IN SLAVE MODE: BIT RATE MAX = PCLK/12
SSP0
REGISTERS
BIT RATE
BIT RATE
USB
REGISTERS & USB SRAM
/4 or /8
CC=2,3,4,..,4095
CC=2,3,4,..,4095
4 BITS
BAUD-RATE PRESCALER
FULL SPEED : 12Mbps
I2C
REGISTERS
/2(CC)+7
/3(CC)+9
CAN
REGISTERS & CAN SRAM
6 BITS BIT
WATCHDOG
REGISTERS
8-BIT
PRESC
16-BIT
COUNTER
BAUD RATE IN
STD MODE
UP TO 100kHz
BAUD RATE IN
FAST MODE
UP TO 400kHz
QUANTUM
BAUD RATE
UP TO 1MBps
ADC
REGISTERS
CK_ADC
T
CONV
up to
10MHz
EXTIT REGISTERS
GPIO REGISTERS
ADC
=30xT
BAUD
RATE
BAUD
RATE
BAUD
RATE
RESET
ADC
CK_RTC
MRCC_PCLKEN(9)
PCLK
CK_RTC
RTC
REGISTERS
20-BIT
PRESC
CK_RTC MUST BE AT LEAST
4X TIMES SLOWER THAN PCLK
32-BIT
COUNTER
DATE
ALARM
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Power supply and clocks AN2476
1.8 Low power modes
Several low power modes are implemented to reach the best compromise between lowest
power consumption, fastest start-up time and available wake-up sources:
● SLOW MODE: System clock speed is reduced
● PCG MODE: APB Peripherals Clock Gating
● WFI MODE: Wait For Interrupts
● STOP MODE: All clocks are disabled
● STANDBY MODE: Part of the chip is unpowered
Software has to execute the low power bit writing sequence (see below) to enter WFI, STOP
or STANDBY modes. This sequence protects the application from entering a low power
mode unintentionally.
1.8.1 Low power bit writing sequence
WFI, STOP or STANDBY modes are entered by software writing the following specific
sequence to the LP bit in the MRCC_PWRCTRL register.
Before executing the sequence, LP_DONE bit status must be previously cleared.
● Write LP bit to ‘1’
● Write LP bit to ‘1’
● Write LP bit to ‘0’
● Write LP bit to ‘1’
● Read LP: if successful, LP is first read at 1 and then cleared by hardware when
entering in Low Power Mode.
This sequence is performed by internal function of the library Section 2: STR750 library low
power mode functions on page 26.
If this sequence is not performed correctly or if LP_DONE was not cleared, the sequence is
automatically reset and must be re-executed from the beginning.
To abort the sequence, simply write twice the LP bit to ‘0’.
The LP_DONE status flag is set after a successful LP bit writing sequence (meaning that
the system has entered and exited the low power mode). This information is useful to know
if the low power mode has been effectively entered or not.
As soon as the LP bit writing sequence is initiated:
● The MRCC_PWRCTRL register is locked (any write access other than to the LP bit will
be discarded) until the sequence is completed or aborted
● Interrupts are masked (IRQ and FIQ signals to the ARM CPU are gated) until the
sequence is completed or aborted
Any interrupts which occur during this sequence will not be lost: they will be served after the
sequence is completed or aborted.
Before performing the sequence, all pending bit interrupts used to wake-up from STOP
mode should be cleared.
If any interrupts from an external interrupt line, an RTC alarm or NCKDF (no clock detected)
event are still pending, the sequence will not performed correctly.
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AN2476 Power supply and clocks
If an interrupt occurs during this sequence, the MCU will not enter Low Power Mode after
completing the sequence, but will serve the interrupt instead.
In both cases, software must then reexecute the low power bit writing sequence to
effectively go into low power mode. It is possible to determine if the low power mode was
entered by reading the LP and LP_DONE bits status after wake-up.
It is mandatory to follow this flow chart to manage the low power mode:
Figure 9. Mandatory software flow for entering low power mode
Main Program
Write LP to ‘1’
Write LP to ‘1’
1
Write LP to ‘0’
Write LP to ‘1’
Read LP
LP=’0’ ?
Read LP_DONE
N
Y
Dedicated LP entry sequence
1
Wait for Low Power entry time
2
2
Low Power not executed, sequence
3
should be re-done
IRQ during sequence)
Low Power successfully executed
4
LP_DONE should cleared.
(bad sequence or
3
N
Interrupt Routine
LP_DONE=’1’ ?
Y
4
Write LP_DONE to ‘0’
Main Program
to be continued
The choice of low power mode entered with this sequence depends on the state of the
LPMC bits described in the Table 1 on page 15.
These bits can be set in the MRCC_PWRCTRL register. See Reference Manual for more
detail.
Table 1. Low Power mode selection
Control bits
Low Power Mode Selected
LPMC[1:0] BURST WFI_FLASH_EN
0 0 - - STOP Mode
0 1 - - Software Reset
0 0 WFI, Flash disabled (DMA not allowed in WFI)
10
1 1 - - STANDBY Mode
0 1 WFI, Flash enabled (DMA allowed in WFI)
10Forbidden
1 1 WFI, Flash enabled (DMA allowed in WFI)
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