ST AN2442 Application note

AN2442

Application note

Using the STR91xFA DMA controller

Introduction

This application note provides information on how to use and take full advantage of the
STR91xFA DMA controller. It is intended for anyone getting started with DMA.

While it is impossible to cover every possible control scenario of each peripheral DMA
transfer, those considered to be the most typical and useful are described.

Software is available with this application note and can be downloaded separately from
www.st.com.

June 2008 Rev 2 1/22

www.st.com

Contents AN2442

Contents

1 DMA unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Peripheral DMA support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 DMA request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 DMA transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.1 DMA channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.2 Source and destination addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.3 Source and destination data width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.4 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.5 Transfer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.6 Transfer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.7 Source and destination burst size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.8 Incrementing source/destination address . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.9 Terminal count interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4.10 DMA linked lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 Programming the DMAC using the STR9 software library . . . . . . . . . . . . 12

2 DMA transfer examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Memory to memory transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.1 Transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Memory to SPP transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 SSP DMA interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.2 Memory to SSP example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.3 Transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.4 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 UART to memory transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 UART-Rx DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.2 UART to memory example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.3 Transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.4 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4 Memory to UART transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.1 UART-TX DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.2 Memory to UART example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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AN2442 Contents

2.4.3 Transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.4 Use of linked lists for DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.5 Terminal count interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5 DMA transfer triggered by external DMA request . . . . . . . . . . . . . . . . . . . 18

2.5.1 External request example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5.2 Transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 Timer to memory transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.1 Timer DMA interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.2 Timer to memory example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.3 Transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.4 Use of linked lists for DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.5 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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DMA unit AN2442

1 DMA unit

The STR91xFA DMA controller (DMAC) is an AMBA AHB module, and connects to the
Advanced High-performance Bus (AHB). It allows devices to transfer data to or from the
system's memory and registers without the intervention of the CPU. While the transfer takes
place the CPU is free to do other things. As a result, the STR9 core is not overloaded to
serve all peripherals and there is an overall speed-up in CPU operation chiefly when
transferring a large amount of data.

1.1 DMA features

The DMAC offers:

● Eight DMA channels. Each channel can support a unidirectional transfer.

● Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 7 has the lowest. If requests from
two channels become active at the same time, the channel with the highest priority is
serviced first.

● The DMAC provides 14 peripheral DMA request lines (refer to Table 1.).

● Single DMA and burst DMA request signals. Each peripheral connected to the DMAC

can assert either a burst DMA request or a single DMA request. Note that peripherals
without FIFO inside can not generate a DMA burst request.

● Programmable DMA burst size. The DMA burst size can be programmed to transfer

data more efficiently. Therefore, up to 256 data per block can be reached (note that the
data width can be configured to byte, half-word or word).

● Support for memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

● Incrementing or non-incrementing addressing for source and destination.

● DMA Linked list support: the DMAC is able to perform a chained list of DMA transfers

without need for CPU intervention

● Separate and combined DMA error and DMA Terminal Count interrupt requests: An

interrupt can be generated to the processor on a DMA error or when a DMA count has
reached 0 (Terminal Count event, usually used to indicate that a transfer has finished).

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AN2442 DMA unit

ARM Core

USB

VIC

EMI

APB

External

TIM0SSP0 UART0

Bridge

SSP1 UART1 TIM1

Memory

Channel7

2xExternal DMA Requests 1)

AHB Bus

APB Bus

RAM

IRQ

FIQ

FIFO

Channel6 Channel5

Channel2Channel3 Channel1

Channel4

Channel0

FIFO FIFO FIFO

FIFO FIFO FIFO FIFO

DMA Interrupt Request

DMA Controller

DMA Request0:Pin 3.0
DMA Request1:Pin 3.1

1.2 Peripheral DMA support

Peripherals supporting the DMA are shown in this block diagram:

Figure 1. DMAC and peripherals with DMA support

Note: 1 An external DMA request can be generated from 2 GPIO pins going to high levels.

The DMAC requests and triggering events are summarized in the following table:

Table 1. STR91x DMA requests

DMA request signal

0 USB RX

1 USB TX

2TIM0

3TIM1

4UART0 RX

5UART0 TX

6UART1RX

7 UART1TX

8 External DMA Req0 Rising edge of P3.0

9 External DMA Req1 Rising edge of P3.1

10 -

11 -

Associated peripheral

function

DMA trigger

USB correct transfer event

Input Capture and Output Compare

events

FIFO watermark level reached

Reserved

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DMA unit AN2442

DMAC

Peripheral

Single DMA request

1)

Burst DMA request

Last single DMA request

3)

Last burst DMA request

3)

DMA request clear

4)

2)

DMA request signal

12 SSP0 RX

13 SSP0TX

14 SSP1RX

15 SSP1 TX

Associated peripheral

1.3 DMA request signals

The following figure describes the signals used for peripherals to request a DMA transfer:

Figure 2. DMA request signals

function

DMA trigger

Half FIFO level reached

1. Single DMA requests are asserted when the peripheral has to transfer one data item.

2. Burst DMA requests are asserted when the peripheral has multiple data items to
transfer. Note that the single and burst requests are not mutually exclusive, they could
be asserted together by the peripheral.

3. Last burst and last single requests can be asserted only when the peripheral is the flow
controller in order to indicate the last transfer request to the DMAC (in STR91xFA, only
the USB has these signals).

4. DMA request clear is asserted by the DMAC to indicate to peripheral that the request
has been serviced.

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AN2442 DMA unit

1.4 DMA transfer properties

A DMA transfer is characterized by the following properties:

● DMA Channel

● Source and destination addresses

● Source and destination data width

● Flow control

● Transfer type

● Transfer size (only when DMAC is the flow controller)

● Source / destination burst size

● Source / destination address incrementing or non-incrementing

● Terminal count interrupt generation

● Next linked list item address

In the following paragraphs, a detailed description of each DMA transfer property is provided.

1.4.1 DMA channel

A DMA channel needs to be allocated by the user (8 channels are available) for the DMA
request. The choice of the channel depends on the required priority (0 to 7) and on the
availability of the channel (not already allocated to another request).

1.4.2 Source and destination addresses

A DMA transfer is defined by a source address and a destination address. Both the source and
destination should be in the AHB or APB memory ranges.

1.4.3 Source and destination data width

Data width for source and destination can be defined as:

● Byte

● Half word (16-bit)

● Word (32-bits)

1.4.4 Flow control

The flow controller is the unit that controls the data transfer length and which is responsible for
stopping the DMA transfer.

The flow controller can be either the DMAC or the peripheral.

● With DMAC as flow controller:

In this case, it is necessary to define the transfer size value.

When a DMA request is served, the transfer size value decreases by the amount of
transferred data (depending of the type of request: burst or single).

When the transfer size value reaches 0, the DMA transfer is then finished and the DMA
channel is disabled in case of no next linked list item, otherwise a new linked list descriptor
will be fetched from SRAM into DMA registers.

For further details about linked lists, refer to Section 1.4.10.

● With the peripheral as flow controller:

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