ST AN2439 Application note

AN2439

Application note

27 W Output power ultra wide range input flyback converter

Introduction

As the telecommunications market grows, the need for suitable PSUs (Power Supply Unit) for equipment grows as well. For products used in telecommunications, the available

voltage is either the mains voltage (from 88 VAC to 265 VAC) or 48 VDC (from 36 VDC to 72 VDC). Power supplies that are able to manage input AC voltage in the full range of 88Vrms

to 265Vrms are quite common while ultra wide range (from 36 VDC to 264 VAC) power supplies are not as common. The main advantage in using a UWR PSU is the savings in design and qualification. Instead of designing and qualifying two PSUs, the work is done once. Cost advantages come from bigger volume production as there is just one product that meets a larger range of electrical specifications.

Disadvantages are the difficulties in having a high performance system in working condition. This application note describes a UWR flayback converter that can be used to supply a DSLM (DSL Multiplexer).

The advantage in using a flyback converter in this application is the moderate variation of the duty cycle with the input voltage. The main drawback is the high value of the rms current in the secondary winding, in the output diode and in the output capacitor.

June 2007

Rev 1

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Contents	AN2439

Contents

1	Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
	1.1	Active start-up with external high voltage current source [2.] . . . . . . . . . . .	4
	1.2	Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.3	Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	1.4	Buck DC-DC converter post regulator [3.] . . . . . . . . . . . . . . . . . . . . . . . . .	7
	1.5	Flyback converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	1.6	Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	1.7	Board tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	1.8	Start-up tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	1.9	Dynamic load regulation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	1.10	Steady state tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	1.11	Static load and line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
2	Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
3	References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
4	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19

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AN2439	Board description

1 Board description

The electrical specifications for this converter are listed in the table below:

Table 1.	Electrical specifications
	Item	Value
	Isolated	Yes
	Input	AC and DC voltage
	Minimum DC input voltage	36 V
	Maximum DC input voltage	72 V
	Minimum AC input voltage	88 V
	Maximum AC input voltage	265 V
	Number of outputs	2
	Output voltage 1	5 V
	Output voltage 2	3.3 V
	Maximum output current 1	2 A
	Maximum output current 1	5 A
	Maximum precision error on output 1	3%
	Maximum precision error on output 2	3%
	Total output power	27 W

As already specified, the selected topology is a flyback converter. In continuous mode the relation between output and input voltage of the converter is:

Equation 1

VOUT	=	n •		D	D =	n • VOUT	VR
-------------VIN -			1------------	– D-		V---------------------------------------IN + n • VOUT	= ----------------------
							VIN + VR

Where n is the turn ratio and VR the reflected voltage. It is easy to verify that for an input voltage that changes between 36 V and 375 V (375V = 2 • 265)Vand 70 V as reflected voltage, the duty cycle changes from about 70% (at minimum input voltage) to about 16%.

Buck type topologies are not suitable because the duty cycle varies widely (from 9%- to 90% for a forward converter in the same condition for example), worsening the efficiency and making the design very complex.

A second design choice was to use a switching post regulator that has, as input voltage, the output voltage of the flyback and the output as 3.3 V. The purpose of this is to meet the requested precision in both outputs and to avoid using another secondary winding where the root mean square current would be very high. Assuming a 90% of efficiency for this step down converter, the total current sunk from the output of the flyback is 5.7 A. The buck converter for the post regulation is described in Section 1.4 on page 7.

In order to limit the high root mean square current at the secondary side, another design choice was to have a flyback converter that works, most of the time, in continuous conduction mode. The controller used in this application is the L5991 [1.] which is a current

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Board description	AN2439

mode controller. In continuous conduction mode for the lower input voltages, the duty cycle is greater than 50% which requires a slope compensation to ensure stable operation of the current loop. The slope compensation is implemented through a circuit described in

Section 1.2 on page 5.

The switching frequency was selected to be equal to 70 kHz and the reflected voltage to be equal to 70 V.

In order to have the same wake-up time for the different input voltages, an active start-up was implemented instead of the most commonly used passive circuits. The active start-up circuit is described in Section 1.1.

In order to improve efficiency, the converter has two different inputs, one for the AC voltage

(88 VACrms to 265 VACrms) and one for the DC voltage (36 VDC to 72 VDC). The input stage of the converter is described in Section 1.3 on page 7.

1.1Active start-up with external high voltage current source [2.]

The circuit of the active start-up is shown in Figure 1. Through R1 and R2 the 600 V MOSFET M1 (STQ1NK60ZR) is switched on. The back-to-back diodes (D1 is a 15 V zener diode and D2 is a standard diode 1N4148) are used to set the voltage between the gate and the resistor R3 pin not connected with the source of M1. The resistor R3 is used to limit the current provided to the capacitor connected to VCC of the L5991. The circuit behaves as a constant current generator and its current can be calculated according to the following equation:

Equation 2

IVZ – Vd – VTH

=------------------------------------

R3

Where VZ is the D1 zener break-down voltage, Vd the diode D2 voltage drop when forward biased and VTH is the gate to source on threshold voltage of the MOSFET M1.

Figure 1. Active start up circuit

To Bulk Capacitor +

R1

R2

		M1
To VREF Pin of the L5991	D1
		R3 To VCC Pin of the
	D2
		L5991
T1		I

When we connect the converter to the mains, the controller (L5991) is initially off, and the small signal bipolar transistor T1 is also off. The gate of the MOSFET M1 is biased through R1 and R2 and the current generator starts to work charging the VCC capacitor. As the VCC voltage exceeds its On Threshold, the L5991 starts to operate and sets the VREF pin (pin 4) to 5 V. This voltage turns on the small bipolar transistor T1 that pulls down the gate of M1

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AN2439	Board description

switching it off. As a result, as the controller is on, the current generator stops working, and the controller is supplied by the auxiliary winding of the flyback converter.

1.2Slope compensation

The circuit for slope compensation is shown in Figure 2. When the main MOSFET (STP10NK70Z) is switched on, the GD pin (Gate Driver) of the L5991 goes high up to a voltage of about 14 V. Capacitor C2 is charged through resistor R2. If the time constant RC is large enough, compared to the switching period, we can assume that the voltage across capacitor C2 is a linear ramp. This voltage is added to the CS pin (Current Sense) through the partition divider R3, R1+RSENSE and provides the needed slope compensation. When the MOSFET M1 is switched off, the gate driver pin of the L5991 pulls down the anode of diode D1. Capacitor C2 is then fast discharged and ready for the next cycle.

Figure 2. Slope compensation circuit

			STP10NK70
GD Pin of L5991	R2 22k		RGATE
			M1
	C2	R3	Bat49
	1.8 nF	15k	D1
CS Pin of L5991			R1 1.5k
			C1

RSENSE

100 pF

Equation 3 gives the waveform expression of the voltage across the capacitor C2. In this formula VD is the forward voltage drop on diode D1 and VGD is the voltage on gate driver pin of the L5991 (Pin 10), when it is high. As a rule of thumb, in order to have approximately a linear ramp across C2, the time constant C2RT is selected in the range of ten times the switching period.

Equation 3

				–t	RT		–t
		R1 + R3 + RSENSE		C-------------------2 •		-------------------
VC(t)	= VGD					C2	•	RT
		• -------------------------------------------------------------	• 1	– e		+ VD • e
		R1 + R2 + R3 + RSENSE

Neglecting RSENSE it can be simplified as:

Equation 4

				–t	RT		–t
		R1 + R3		C-------------------2 •		-------------------
VC(t)	VGD					C2	•	RT
		• ---------------------------------	•	1 – e		+ VD • e
		R1 + R2 + R3

RT is the equivalent resistance across capacitor C2:

Equation 5

	Rτ	=	R2 • (R1 – R3		– RSENSE)		R2 • (R1		– R3)
			-----------------------------------------------------------------R1	+ R2 + R3	+ RSENSE		-------------------------------------R1	+ R2	+ R3

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Board description	AN2439

The slope compensation voltage added on CS Pin of the L5991 is:

Equation 6

	Vs	(t) =	R1 – RSENSE		• VC	(t)	R1		• VC	(t)
			R------------------------------------------------2	+ R3 + RSENSE			R-------------------2	+ R3-

We know that if we add a ramp whose slope is one half of the primary side equivalent demagnetizing current slope (ma), the current loop is stable for any duty cycle lower than one. As consequence the requested amount of slope compensation needed to guarantee stable operation is:

Equation 7

mS =	1	VR	• RSENSE
	--	• ------
	2	Lm

In the last equation VR is the reflected voltage and Lm the magnetizing inductance at

primary side. The value of RSENSE has to be calculated taking into account the slope compensation we add and of course the maximum peak current at the primary side (IPKP).

Equation 8

RSENSE	=			1V
			1	•	VR	•	DMAX
	IPKP	+
			2--		------Lm		--------------fsw

The maximum value of the voltage we add at the current sense pin is:

Equation 9

VSMAX = ms •	DMAX		= R	R1			DMAX
	--------------f	sw		2	+ R	3-	• VC --------------f	sw

Figure 3 shows the gate driver signal and the slope compensation signal measured at the CS pin.

Figure 3. Slope compensation signal

Ch1 (yellow): gate driver signal

Ch4 (green): slope compensation ramp on current sense pin

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