ST AN2424 APPLICATION NOTE

AN2424

Application note

STMPE2401 - Port expander

PWM controller

Introduction

STMPE2401 is the first in the family of ST port-expander logic products. The principle of a basic expander logic is to provide additional I/Os that can be used by the host processor to implement additional features such as increasing the number of control signals and mixed signal lines, or controlling more number of peripherals.

In addition to the above mentioned basic features, STMPE2401 comes with integrated intelligence to implement advanced features like Keypad scanning, PWM control, and Rotator dial control. These features enable the processor load to be reduced.

There is also a provision for using a single crystal clock to drive multiple STMPE2401 devices by cascading the devices and using the CLKOUT mode to drive the clock of the cascaded devices.

STMPE2401 can be widely used in the fields of Mobile Communications, Portable media players, Game console, Mobile Phones, Smart Phones, Consumer Electronics and computer peripherals like state-of-the-art printers, Advanced embedded systems etc.

This application note explains the setup and programming of the integrated PWM controller in STMPE2401 to do LED backlighting, brightness control, and LED blinking patterns.

April 2007 Rev 1 1/22

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Contents AN2424

Contents

1 Advantages of an integrated PWM controller . . . . . . . . . . . . . . . . . . . . . 4

1.1 STMPE2401 default power-up configuration . . . . . . . . . . . . . . . . . . . . . . . 4

2 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Operation modes and clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 PWM instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1 PWM Controller operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Registers in the PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 PWM control and status register (PWMCS) . . . . . . . . . . . . . . . . . . . . . . . 12

5.2 PWM instruction channel_x (PWMICx) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Alternate function register (GPAFR_U_msb) . . . . . . . . . . . . . . . . . . . . . . 14

5.4 Interrupt control register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.5 Interrupt enable mask register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6 Interrupt status register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.7 Programming sequence - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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AN2424 List of tables

List of tables

Table 1. Valid STMPE2401 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. SYSCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. SYSCON description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. RAMP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. RAMP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. SMAX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 7. SMIN instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 8. GTS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 9. BRANCH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 10. BRANCH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 11. END instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 12. END description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 13. TRIG instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 14. TRIG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 15. PWM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 16. PWMCS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 17. PWM instruction description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 18. GPAFR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 19. ICR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 20. IER description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 21. ISR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 22. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Advantages of an integrated PWM controller AN2424

1 Advantages of an integrated PWM controller

– Low CPU utilization

– Lower power consumption

– Simpler driver software

– Simpler connection to CPU (only two I

– Advanced programmable ramping/blinking patterns for lighting effects

– Analog/PWM output

– Application: Mobile phone backlighting, LED brightness control

1.1 STMPE2401 default power-up configuration

STMPE2401 operates at a supply voltage of 1.8 V. The clock can be supplied through a 32 KHz crystal connected across XTALIN, XTALOUT pins or through an external oscillator clock on XTALIN pin. The external oscillator can be low accuracy (16 KHz ~ 32 KHz) and the clock frequency for normal operation should not exceed 32 KHz. The Reset pin should be pulled high for the device to come out of reset and operate in the normal operating mode.

The device can be accessed through the I can be connected to the same I

Philip I

C specification Ver 2.1. The slave address is selected by the state of two pins (GPIO15 and GPIO23). The state of the pins is latched into STMPE2401 at power on and this address setting is retained until the power is switched off.

C bus. STMPE2401 supports 7-bit addressing as per the

C lines)

C interface and up to four STMPE2401 devices

The address can be changed and latched-in again using the soft_reset bit in the SYSCON register.

The I

C Read/Write is done byte by byte. The R/W bit is added as the LSB to the 7-bit slave address to make up one byte to be sent through the I slave address is configured and responding correctly, the internal registers can be accessed through I and the I

C read and write commands. Ta bl e 1 lists the slave addresses that can be used

C Read/Write protocol to access the device registers.

C interface from the Master. Once the

Table 1. Valid STMPE2401 slave address

ADDR1

(GPIO23)

0 0 42h (1000010b) 84h

0 1 43h (1000011b) 86h

1 0 44h (1000100b) 88h

1 1 45h (1000101b) 8Ah

ADDR0

(GPIO15)

7-bit slave

addressing

8-bit format to be

used (including R/W

bit in LSB)

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AN2424 PWM controller

Figure 1. I2C Read/Write protocol

One Byt e Re ad

More than One Byt e Re ad

One Byt e Write

ore than One Byt e Write

Dev

Addr

Start

Dev

Addr

Start

Dev

Addr

Start

Dev

Addr

Start

Master Slave

At power-up all GPIOs function as inputs and by default the interrupt is configured as an Active Low Level interrupt. The interrupt however remains low irrespective of the settings until the Global Interrupt bit in the ICR register is enabled (set to '1').

2 PWM controller

Reg

Addr

RnW=0

Ack

Reg

Addr

RnW=0

Ack

Reg

Addr

RnW=0

Ack

Reg

Addr

RnW=0

Ack

Dev

Addr

reStart

Dev

Addr

reStart

Dat a t o

Written

Dat a t o

Write

RnW=1

top

Ack

Data to

Write + 1

Ack

Data

Rea d

Ack

Data

Rea d

Ack

NoAck

Ack

Data to

Write + 2

top

Dat a

Read + 1

Ack

top

Read + 2

Ack

Data

NoAck

Stop

STMPE2401 comes with an integrated PWM controller that can provide three independent PWM outputs. These outputs can be used to generate light effects like rapid blinking or dimming in LEDs. There are three PWM channels and they can be triggered independently. Each PWM channel can be triggered by the other two channels. The unused PWM output pins can be used as GPIO.

Each channel comes with a maximum 64 words x 16-bit command memory. The instructions to be stored in the command memory can be downloaded through the I

C connections. Any attempt to load beyond 64 words causes the internal address pointer to roll-over (0x1f -> 0x00) and the excess instructions overwrite the first address location of the channel and onwards.

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Operation modes and clocking AN2424

3 Operation modes and clocking

The PWM controller can be enabled only in the normal operational mode. In operational mode, the PWM controller output is generated using the 32 KHz clock. The instruction fetching and execution is also derived from the 32 KHz clock domain. The internal 5 MHz clock is used only for the I PWM is enabled, there is no interruption in the PWM output even though the internal 5 MHz clock is cut-off in the sleep mode. However, the I mode and therefore the PWM should be enabled before entering sleep mode.

C interface. Therefore, if the device enters sleep mode while the

C interface does not function during sleep

During Hibernate mode, the 32 KHz clock is also shut down and all modules are disabled. The device resumes normal operation only after an I

C wake-up or Reset.

When the PWM function is not in use, power consumption can be reduced by gating off the clock to the PWM Controller. This can be done by setting the 'Enable_PWM' bit in the SYSCON register to zero.

Table 2. SYSCON register

Bit 7 6 5 4 3 2 1 0

Soft_Reset - Disable_32KHz Sleep Enable_GPIO Enable_PWM Enable_KPC Enable_ROT

Read/Write (IIC)

Read/Write (HW)

Reset value

WRWRWRWRWRWRW

RW R RW R R R R

00 01111

Table 3. SYSCON description

Bit Name Description

2 Enable_PWM

4 Sleep

Writing a ‘0’ to this bit gates off the clock to the PWM Controller module, thus stopping its operation

Writing a ‘1’ to this bit puts the device in sleep mode. When in sleep mode, all the units which need to work on clocks synchronous to 32 KHz get the clocks derived from the 32 KHz domain.The internal RC Oscillator shuts down.

Set this bit to disable the 32 KHz Clk, thus putting the device in hibernate

5 Disable_32 KHz

7 Soft_Reset

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mode. Only a Reset or a wakeup on I2C resumes normal operation of the device.

Writing a ‘1’ to this bit does a soft reset of the device. Once the reset is done, this bit is cleared to ‘0’ by the Hardware.

AN2424 PWM instruction set

4 PWM instruction set

The STMPE2401 PWM controller works as a simple MCU, with a program space of 64 instructions and a simple instruction set. The instructions are all 16-bits in length. The three most significant bits are used to identify the command.

● RAMP

This instruction starts the PWM counters and the pwm_output depends on the counter value.

Table 4. RAMP instruction

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 Prescale Step time Sign Increment

Table 5. RAMP description

Bits Name Description

6:0 Increment Increment size. Takes value between 1-126. ‘0’ setting is not allowed.

7Sign

13:8 Step Time

14 Prescale

‘0’ – Step up counter ‘1’ – Step Down counter

‘0’ – Immediate action 1-63 – Step time per increment

‘0’ – Divide clock by 16 ‘1’ – Divide clock by 512 clock

Each increment is broken down into the number of steps specified by the 'Step time' parameter and the time taken for each step is based on the prescale clock. (refer : Example

2: in section 4.1)

● SMAX (Set Maximum)

This instruction loads the PWM counter with the maximum value of 0xff and the resulting pwm_output is logic level low.

Table 6. SMAX instruction

Bits 1514131211109876543210

Note: 1 “x“ don‘t care

● SMIN (Set Minimum)

This instruction loads the PWM counter with the minimum value of 0x0 and the resulting pwm_output is logic level high.

Table 7. SMIN instruction

Bits 1514131211109876543210

Note: 1 “x“ don‘t care

00000001111111

00000011111111

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