ST AN2419 Application note

AN2419

Application note

STR75x hardware development

getting started

Introduction

This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the STR75x product family and describes the minimum hardware resources required to develop an STR75x application.

Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes.

July 2007 Rev 2 1/22

www.st.com

Contents AN2419

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Power scheme 1: single external 3.3V power source . . . . . . . . . . . . . . . 4

1.2.2 Power scheme 2: dual external 3.3V and 1.8V power sources . . . . . . . . 5

1.2.3 Power scheme 3: single external 5V power source . . . . . . . . . . . . . . . . . 6

1.2.4 Power scheme 4: dual external 5.0V and 1.8V power sources . . . . . . . . 7

1.3 Reset and power startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.1 Power startup specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Main 4MHz or 8MHz oscillator (OSC4M) . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Low power 32.768 kHz oscillator (OSC32K) . . . . . . . . . . . . . . . . . . . . . . 11

2.4 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 PLL, FREEOSC, and AHB/APB prescalers . . . . . . . . . . . . . . . . . . . . . . . 12

2.6 Clock-out capability: MCO (Main Clock Output) . . . . . . . . . . . . . . . . . . . . 13

2.7 Clock detector (CKD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 External memory (SMI) boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 ICE debug tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 JTAG / ICE connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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AN2419 Contents

5.2 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Power supplies AN2419

1 Power supplies

1.1 Introduction

The device has five power pins:

● V

STANDBY mode.

● V

SRAM and Flash: 1.8V ± 0.15V.

● V

Two embedded regulators are available to supply the internal 1.8V digital power:

and V

The Main Voltage Regulator (MVREG) supplies V of 1.8V ± 0.15V.

: power supply for I/Os (3.3V ±0.3V or 5V ±0.5V). Must be kept on, even in

DD_IO

(pins V

: Backup Power Supply for STANDBY or STOP Mode

18_BKP

and V18 which are internally shorted): Power Supply for Digital,

18REG

are normally generated internally by these regulators.

and V

. It delivers a power supply

18_BKP

The Low Power Voltage Regulator (LPVREG) can supply V

18_BKP

STANDBY mode. It delivers a power supply of around 1.4V.

Two sensitive analog blocks have dedicated power pins:

● V

DDA_PLL

DDA_ADC

: Analog Power supply for PLL (must have the same voltage level as V

: Analog Power supply for ADC (must have the same voltage level as V

1.2 Power supply schemes

The device can be connected in any of the following configurations depending on your application requirements:

● Power Scheme 1: Single external 3.3V power source

● Power Scheme 2: Dual external 3.3V and 1.8V power sources

● Power Scheme 3: Single external 5.0V power source

● Power Scheme 4: Dual external 5.0V and 1.8V power sources

1.2.1 Power scheme 1: single external 3.3V power source

In this configuration, the internal voltage regulators are switched on by forcing the VREG_DIS pin to low level.

● The V

Tantalum, low series resistance).

● The V

● A decoupling capacitor of 1µF must be added on the V

18REG

pin must be connected to external stabilization capacitors (min. 10 uF

18REG

pin must be connected to external stabilization capacitors (33nF ceramic).

pin must be connected to an external stabilization capacitor of 1µF.

18_BKP

DD_IO

pin.

or V18 in STOP or

DD_IO

pin which is closest to the

)

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AN2419 Power supplies

Figure 1. Power supply scheme 1 (single 3.3V supply, VREGDIS=0) in NORMAL mode

STR750

+3.3V

1µF

33nF

10µF

18_BKP

SS_BKP

VREG_DIS

SS18

18REG

SS18

DD_PLL

SS_PLL

DD_ADC

SS_ADC

DD_IO

SS_IO

1.2.2 Power scheme 2: dual external 3.3V and 1.8V power sources

In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. This scheme has the advantage of saving power consumption when the 1.8V power supply is already available in the application. V provided externally through the V

● The external 3.3V power supply must always be kept on.

● VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and

18REG

, V18 and V

18_BKP

power pins.

the Low Power Voltage Regulator.

and V

18_BKP

are

Caution: When powered by 5.0V, the USB peripheral cannot operate.

● All digital power pins (V

18REG

, V18 and V

) must be externally shorted to the

18_BKP

same 1.8V power supply source.

● In this scheme, STANDBY Mode is not available.

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Power supplies AN2419

Figure 2. Power supply scheme 2 (3.3V and 1.8V supplies, VREGDIS=1)

STR750

18_BKP

+3.3V

+1.8V

NOTE : THE EXTERNAL 3.3V POWER SUPPLY MUST ALWAYS BE KEPT ON

SS_BKP

VREG_DIS

SS18

18REG

SS18

DD_PLL

SS_PLL

DD_ADC

SS_ADC

DD_IO

SS_IO

+3.3V+1.8V

+3.3V

1.2.3 Power scheme 3: single external 5V power source

In this configuration, the internal voltage regulators are switched on by forcing the VREG_DIS pin to low level.

● The V

pin must be connected to external stabilization capacitors (min. 10 uF

18REG

Tantalum, low series resistance).

● The V

● A decoupling capacitor of 1µF must be added on the V

pin must be connected to external stabilization capacitors (33nF ceramic).

pin must be connected to an external stabilization capacitor of 1µF.

18_BKP

DD_IO

pin.

18REG

Caution: When powered by 5.0V, the USB peripheral cannot operate.

Figure 3. Power supply scheme 3(single 5V supply, VREGDIS=0) in NORMAL mode

STR750

+5V

1µF

33nF

10µF

18_BKP

SS_BKP

VREG_DIS

SS18

18REG

SS18

DD_PLL

SS_PLL

DD_ADC

SS_ADC

DD_IO

SS_IO

pin which is closest to the

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AN2419 Power supplies

1.2.4 Power scheme 4: dual external 5.0V and 1.8V power sources

In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. This scheme has the advantage of saving power consumption when the 1.8V power supply is already available in the application and providing 5V I/O capability. V power pins.

● VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the

Low Power Voltage Regulator.

● All digital power pins (V

same 1.8V power supply source.

In this scheme:

● STANDBY Mode is not available

● USB functionality is not available

Figure 4. Power supply scheme 4 (5.0V and 1.8V supplies, VREGDIS=1)

and V

18_BKP

+5.0V

are provided externally through the V

18REG

, V18 and V

) must be externally shorted to the

18_BKP

STR750

+1.8V

18_BKP

SS_BKP

VREG_DIS

SS18

18REG

SS18

DD_PLL

SS_PLL

DD_ADC

SS_ADC

DD_IO

SS_IO

+5.0V

18REG

, V18 and V

18_BKP

NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON

1.3 Reset and power startup

1.3.1 Power startup specifications

To ensure the MCU starts-up cleanly, the rise time of the V comprised between 20µs/V and 20ms/V.

In addition, you must provide an external RESET for at least 20µs after the V supply has reached its minimum working value (3.0V). It is recommended to use an external Power-On-Reset circuit monitoring V

During V state, assuming external RESET is asserted.

If you are using an external 1.8V power supply, the rise time of power supply V comprised between 20µs/V and 20ms/V.

power-up (from 0V to 3.3V or 5.0V), all I/Os are guaranteed to be in HiZ

DD_IO

power supply must be

DD_IO

power

DD_IO

to assert the RESET at power-up .

DD_IO

must be

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