ST AN2381 APPLICATION NOTE

AN2381

Application note

LIS3LV02DL: 3-Axis - ±2g/±6g digital output

low voltage linear accelerometer

Introduction

This document is intended to give application notes for the low-voltage 3-axis digital output
linear MEMS accelerometer provided in LGA package.

The LIS3LV02DL is a three axes digital output linear accelerometer that includes a sensing
element and an IC interface able to take the information from the sensing element and to
provide the measured acceleration signals to the external world through an I
interface.

The sensing element, capable of detecting the acceleration, is manufactured using a
dedicated process developed by ST to produce inertial sensors and actuators in silicon.

The IC interface instead is manufactured using a CMOS process that allows high level of
integration to design a dedicated circuit which is factory trimmed to better match the sensing
element characteristics.

The LIS3LV02DL has a user selectable full scale of ±2g, ±6g and it is capable of measuring
acceleration over a bandwidth of 640 Hz for all axes. The device bandwidth may be selected
accordingly to the application requirements. A self-test capability allows the user to check
the functioning of the system.

2

C/SPI serial

The device may be configured to generate an inertial wake-up/free-fall interrupt signal when
a programmable acceleration threshold is crossed at least in one of the three axes.

The LIS3LV02DL is available in plastic SMD package and it is specified over a temperature
range extending from -40°C to +85°C.

The small size and weight of this package make it an ideal choice for handheld portable
applications such as cell phones and PDAs or any other application where size, weight and
package performance are required.

June 2006 Rev 1 1/47

www.st.com

Contents AN2381

Contents

1 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Electrical connection and board layout hints . . . . . . . . . . . . . . . . . . . . . 9

2.1 Electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Power supply and board layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 I2C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1.2 I2C Subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1.3 I2C Read and Write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 SPI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.1 Read & Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.2 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2.3 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2.4 SPI Read in 3-wires Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Registers Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.1 Reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.2 Registers loaded at Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2.1 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2.2 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2.3 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 Data and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.2 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.3 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.4 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.5 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/47

AN2381 Contents

5.3.6 OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.7 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.8 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4 Free-Fall and Wake-Up Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4.1 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4.2 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4.3 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4.4 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.5 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.6 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.7 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5 Direction-Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.5.1 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.5.2 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5.3 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.4 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.5 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.6 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.7 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2 Reading acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2.1 Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2.2 Using the Data-Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2.3 Using the Block Data Update feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3 Understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3.1 Data Alignment: 12 and 16 bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3.2 Big-Little Endian Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3.3 Example of Acceleration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.4 Interrupt generation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.5 Inertial wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.5.1 HP filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.5.2 Using the HP filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.6 Free-Fall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.7 Direction detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/47

Contents AN2381

6.8 Output data rate selection and reading timing . . . . . . . . . . . . . . . . . . . . . 44

6.9 Data Ready vs. Interrupt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.10 Using the external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4/47

AN2381 List of tables

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. I2C/SPI signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. I2C Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Output Data Registers Content vs. Acceleration (FS= 2g) . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7. Output data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 8. Timing Value to Avoid Loosing the Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5/47

List of figures AN2381

List of figures

Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. LIS3LV02DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. I2C Subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. Read & Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. SPI Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. Multiple Bytes SPI Read Protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. SPI Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. Multiple Bytes SPI Write Protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. SPI Read Protocol In 3-wires Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. HP Filter Transfer Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11. Block diagram of data output path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. FF_WU_CFG High and Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 13. DD_CFG High and Low Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 14. Free-Fall, Wake-Up Interrupt Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 15. Direction Detector Interrupt Generator for X axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16. Reading Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17. Interrupt and DataReady Signal Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18. Data Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6/47

AN2381 Theory of operation

1 Theory of operation

The LIS3LV02DL is a high performance, low-power, LGA packaged, digital output 3-axis
linear accelerometer. The complete device includes a sensing element and an IC interface
able to take the information from the sensing element and to provide a signal to the external
world through an I

A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.

When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the sense capacitor.

At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is up to 100fF.

The complete measurement chain is composed by a low-noise capacitive amplifier which
converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by
three Σ∆ analog-to-digital converters, one for each axis, that translate the produced signal
into a digital bit stream. The Σ∆ converters are tightly coupled with dedicated reconstruction
filters which remove the high frequency components of the quantization noise and provide
low rate and high resolution digital words. The charge amplifier and the Σ∆ converters are
operated respectively at 61.5 kHz and 20.5 kHz. The data rate at the output of the
reconstruction depends on the user selected Decimation Factor (DF) and spans from 40 Hz
to 2560 Hz.

The acceleration data may be accessed through an I
device particularly suitable for direct interfacing with a microcontroller.

2

C/SPI serial interface.

2

C/SPI interface thus making the

The LIS3LV02DL features a Data-Ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in digital
system employing the device itself. The LIS3LV02DL may also be configured to generate an
inertial Wake-Up, Direction Detection or Free-Fall interrupt signal accordingly to a
programmed acceleration event along the enabled axes.

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).

The trimming values are stored inside the device by a non volatile structure. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during the normal operation. This allows the user to employ the device without
further calibration.

7/47

Theory of operation AN2381

Figure 1. Device block diagram

a

SELF TEST

X+

Y+

Z+

Z-

Y-

X-

MUX

REFERENCE

CHARGE

AMPLIFIER

DE

MUX

TRIMMING

CIRCUIT

Σ∆

Σ∆

Σ∆

Reconstruction

Filter

Reconstruction

Filter

Reconstruction

Filter

CLOCK

Regs

Array

CONTROL LOGIC

&

INTERRUPT GEN.

SPI

I2C

CS

SCL/SPC

SDA/SDIO

SDO

RDY/INT

8/47

AN2381 Electrical connection and board layout hints

2 Electrical connection and board layout hints

2.1 Electrical connection

The typical electrical connection of the LIS3LV02DL is shown in Figure 2

Figure 2. LIS3LV02DL electrical connection

Z

Vdd_IO

CS

SCL/SPC

SDO

RDY/INT

SDA/SDI/SDO

1

Y

14

1

16

15

100nF

DIRECTION OF THE
DETECTABLE
ACCELERATIONS

Vdd

10uF

X

6

LIS3LV02DL

7

(TOP VIEW)

8

9

GND

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

The device core is supplied through Vdd line (Vdd typ=2.5V) while the I/O pads are supplied
through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should
be placed as near as possible to the pin 13 of the device.

Both the voltage supplies must be present at the same time to have proper behavior of the
IC. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication
bus.

The central die pad and pin #1 indicator are physically connected to GND.

The functionality of the device and the measured acceleration data are
selectable/accessible through the I

When using the I

2

C, CS must be tied high while SDO must be left floating.

2

C/SPI interface.

2.2 Power supply and board layout hints

The LIS3LV02DL is designed for a voltage supply spanning from 2.16V up to 3.6V.
The typical current consumption in normal mode at 2.5V is 600µA.

Adequate power supply decoupling is required to ensure IC performances. The optimum
decoupling is achieved by using two capacitors of different types that target different kinds of
noise on the power supply leads. To attenuate high frequency transients, spikes, or digital

9/47

Electrical connection and board layout hints AN2381

hash on the line it is recommended the use of one 100nF ceramic or polyester capacitor
which must be placed as close as possible to device Vdd lead. For filtering lower-frequency
noise signals, a larger aluminum capacitor of 10µF or greater should be placed near the
device in parallel to the former capacitor.

It is recommended that the afore capacitors are placed as close as possible to pin 13.

2.3 Soldering information

The LGA-16 package is lead free and green package qualified for soldering heat resistance
according to JEDEC J-STD-020C. Land pattern and soldering recommendations are
available upon request.

10/47

AN2381 Absolute maximum ratings

3 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 1. Absolute maximum ratings

Symbol Ratings Maximum Value Unit

Vdd Supply voltage

Vdd_IO I/O pins Supply voltage

(1)

(1)

-0.3 to 6 V

-0.3 to Vdd +0.1 V

Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, CK)

-0.3 to Vdd_IO +0.3 V

3000g for 0.5 ms

Acceleration (Any axis, Powered, Vdd=2.5V)

10000g for 0.1 ms

3000g for 0.5 ms

Acceleration (Any axis, Unpowered)

10000g for 0.1 ms

Operating Temperature Range -40 to +85 °C

OP

Storage Temperature Range -40 to +125 °C

A

A

T

Vin

POW

UNP

T

STG

4.0 (HBM) kV

ESD Electrostatic discharge protection

200 (MM) V

1.5 (CDM) kV

1. Supply voltage on any pin should never exceed 6.0V.

Warning: This is a ESD sensitive device, improper handling can cause

permanent damages to the part.

Warning: This is a mechanical shock sensitive device, improper

handling can cause permanent damages to the part.

11/47

Digital interfaces AN2381

4 Digital interfaces

The registers embedded inside the LIS3LV02DL may be accessed through I2C and SPI
serial interfaces. They are mapped onto the same pads. To select/exploit the I

CS line must be tied high.

Table 2. I

Pin Name Description

CS SPI chip select (CS)

SCL/SPC SPI CK line (SPC)

SDI/SDA/SDO SPI data in (SDI)

SDO SPI data out (SDO) -when not in 3-wire mode-

2

C/SPI signals mapping

I2C/SPI selector (1: I2C mode; 0: SPI enabled)

2

C clock line (SCL)

I

I2C serial data (SDA)
SPI data out (SDO) -when in 3-wire mode-

4.1 I2C Bus interface

The LIS3LV02DL I2C is a bus slave. The I2C is employed to write/read the data into/from the
registers.

The relevant I

Table 3. Terminology

2

C terminology is shown in Tabl e 3 :

2

C interface,

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master The device which initiates a transfer, generates clock signals and terminates

a transfer

Slave The device addressed by the master

There are two signals associated with the I2C bus: SCL and SDA.

These pins are described in the subsequent table:

Table 4. I2C Pin Description

Term Description

SCL Serial CLock Line

SDA Serial DAta Line

SDA is a bidirectional line. Both SCL and SDA are connected to a positive supply voltage
via a pull-up resistor. When the bus is free both lines are HIGH.

12/47

AN2381 Digital interfaces

4.1.1 I2C Operation

The transaction on the bus is started through a START signal. A START condition is defined
as a HIGH to LOW transition on the data line while the SCL line is held HIGH (refer to ST
condition in the following paragraph). After this has been transmitted by the Master, the bus
is considered busy. The next byte of data transmitted after the start condition contains the
address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving
data from the slave or transmitting data to the slave (SA subsequence). When an address is
sent, each device in the system compares the first seven bits after a start condition with its
own address. If they match, the device considers itself addressed by the Master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse (SAK
subsequence). A receiver which has been addressed is obliged to generate an
acknowledge after each byte of data has been received.

2

The I

C embedded inside the LIS3LV02DL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a salve address is sent (SA),
once a slave acknowledge has been returned (SAK), a 8-bit sub-address will be transmitted
(SUB): the 7 LSB represent the actual register address while the MSB enables address
autoincrement.

If the MSB of the SUB field is ‘1’, the SUB (register address) will be automatically increased
by one to allow multiple data read/write at increasing addresses.

Otherwise if the MSB of the SUB field is ‘0’, the SUB will remain unchanged and multiple
read/write on the same address can be performed.

If the LSB of the slave address was ‘1’ (read), a repeated START (SR) condition will have to
be issued after the sub-address byte; if the LSB is ‘0’ (write) the Master will transmit to the
slave with direction unchanged.

4.1.2 I2C Subsequences

In order to better define subsequences and to clarify line SCL and SDA behavior, a
description containing discrete value of SCL and SDA will follow. In column there is the
value present on line SCL and SDA in discrete timing. These simple subsequences are
used to realize complex commands described in the following paragraph.

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Digital interfaces AN2381

Figure 3. I2C Subsequences

ST: START condition

SCL 1111

SDA 1100

SR: Repeated START condition

SCL 1111

SDA 1100

SAD: Slave address (binary address: abcdefgh. In LIS3LV02DL "abcdefg" = "0011101")

SCL 00110 0110 0110 0110 0110 0110 0110 0110

SDA 0aaaa bbbb cccc dddd eeee f f f f gggg hhhh

Bit h=0 => write, h=1 => read

SAK: Slave acknowledge (Z means high impedance)

SCL 0011

SDA (force) ZZZZ Check that SDA is 0 after SCL=1

SDA (read) XX00

SUB: Sub address (binary address: abcdefgh)

SCL 00110 0110 0110 0110 0110 0110 0110 0110

SDA 0aaaa bbbb cccc dddd eeee f f f f gggg hhhh

Bit a=0 => do not increment address in multiple mode

a=1 => increment address in multiple mode

DATA (Master): send DATA byte (binary number: abcdefgh)

SCL 00110 0110 0110 0110 0110 0110 0110 0110

SDA 0aaaa bbbb cccc dddd eeee f f f f gggg hhhh

DATA (Slave): read DATA byte (binary number: abcdefgh)

SCL 00110 0110 0110 0110 0110 0110 0110 0110

SDA (force) ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ

SDA (read) a b c d e f g h

SP: STOP condition

SCL 1111

SDA 0011

MAK: Master Acknowledge

SCL 0011

SDA 0000

NMAK: No Master Acknowledge

SCL 0011 or 00011

SDA ZZZZ or 1111

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AN2381 Digital interfaces

4.1.3 I2C Read and Write sequences

The previous subsequences are used to realize actual write and read sequences described
in the tables below.

Transfer when Master is writing one byte to slave:

Master ST SA + W SUB DATA SP

Slave SAK SAK SAK

Transfer when Master is writing multiple bytes to slave:

Master ST SA + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Transfer when Master is receiving (reading) one byte of data from slave:

Master ST SA + W SUB SR SA + R

NMAK SP

Slave SAK SAK SAK DATA

Transfer when Master is receiving (reading) multiple bytes of data from slave:

Master ST SA + W SUB SR SA + R MAK

Slave SAK SAK SAK DATA

Master MAK NMAK SP

S la ve DATA DATA

Data are transmitted in byte format. Each data transfer contains 8 bits. The number of bytes
transferred per transfer is unlimited. Data is transferred with the Most Significant Bit (MSB)
first. If a receiver can’t receive another complete byte of data until it has performed some
other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state.
Data transfer only continues when the receiver is ready for another byte and releases the
data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition (SP). Each data transfer must be
terminated by the generation of a STOP condition.

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