ST AN2354 Application note
AN2354
Application note
ST10 UART recommendations
Introduction
This application note gives advice on using the ASC peripherals present in the ST10 and in
particular, the asynchronous operations will be considered. A brief guide in the configuration
of the peripheral and how to connect it to an RS232 interface or RS485 network is followed
by an analysis of the sources of timing problems and how to minimize them to allow correct
and error-free communications.
Please refer to the product user manual and datasheet for a full and detailed description of
the functionality.
April 2006 Rev 1 1/21
www.st.com
Contents AN2354
Contents
1 ST10 ASC peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Register linked with ASC modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.2 Transmit and receive buffer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Asynchronous data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Asynchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.3 Asynchronous reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.4 Hardware error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.5 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 ASCx interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Connecting an ASC to an RS232 interface . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Connecting ST10F27x to a PC UART RS232 interface . . . . . . . . . . . . . . 12
3 Connecting ASC to an RS485 network . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 RS485 versus RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Connecting ST10F27x to an RS485 network . . . . . . . . . . . . . . . . . . . . . 14
4 UART communication and ST10 clock generation . . . . . . . . . . . . . . . . 15
4.1 Arithmetic error in baud rate setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Send/receive jitter problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Clock issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Communication channel effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Timing limit of UART communications . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
AN2354 ST10 ASC peripherals
1 ST10 ASC peripherals
Unlike the old microcontrollers of the ST10 family, two Asynchronous/Synchronous Serial
(ASC) Interfaces are implemented on the latest ST10F27x and ST1025x, one as a standard
peripheral and the other one mapped on the XBUS. The so-called standard module,
instead, is present on all the devices of the ST10 family. The main differences between the
two interfaces are limited to the programming model and interrupt management; in terms of
general functionality and performance the two modules are equivalent.
The rest of the document refers only to the ST10F27x, recalling that all discussion regarding
the standard module is still valid for all the other ST10 microcontrollers.
These peripherals provide serial communication between the ST10F27x and other
microcontrollers, microprocessors or external peripherals. We refer to standard ASC
interface as ASC0 and XBUS ASC interface as ASC1.
The ASC interfaces provide two kind of operations: Asynchronous and Synchronous. In
synchronous mode, data is transmitted or received synchronously to a shift clock. In
asynchronous mode, 8- or 9-bit data transfer, parity generation and a number of stop bits
can be selected. Parity, framing and overrun error detection is provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered.
For multiprocessor communication, a mechanism to distinguish address from data byte is
included. Testing is supported by a loop-back option. A 13-bit baud rate generator provides
the ASC with a separate serial clock signal.
1.1 Register linked with ASC modules
While ASC0 is enabled by default after the reset, ASC1 must be enabled by setting XPEN
(bit 2 of SYSCON register) and bit 8 of XPERCON register. ASC0 is connected as an
alternate function of bit 10 and bit 11 of PORT3 (P3.10/TXD0, P3.11/RXD0). ASC1 is
connected as an alternate function of bit 6 and bit 7 of PORT8 (P8.6/TXD1 P8.7/RXD1).
Obviously , RX pins must be set as input and TX pins as output, using the standard direction
port register (DP3 ) for AS C0 and XS1PORT register for ASC1.
1.1.1 Control register
A control register controls the operating mode: S0CON for ASC0 and XS1CON for ASC1.
The first one is bit addressable; the second one is not bit addressable. However, two
additional registers (XS1CONSET and XS1CONCLR) are provided to set and clear single
bits. Setting a bit in XS1CONSET register sets the corresponding bit in XS1CON register;
clearing a bit has no effect. Likewise, setting a bit in XS1CONCLR register clears the
corresponding bit in XS1CON register; clearing a bit has no effect.
SxCON (0 for ASC0 and 1 for ASC1) Reset value: 0000h
1514131211109876543210
SxR SxLB SxBRS SxODD - SxOE SxFE SxPE SxOEN SxFEN SxPEN SxREN SxSTP SxM
RW RW RW RW RW RW RW RW RW RW RW RW RW
3/21
ST10 ASC peripherals AN2354
Table 1. SxCON register description
Bit Function
ASCx mode control
0 0 0:8-bit data - synchronous operation
0 0 1:8-bit data - synchronous operation
0 1 0:Reserved. Do not use this combination
SxM
SxSTP
SxREN
SxPEN
0 1 1:7-bit data + parity - asynchro nous operation
1 0 0:9-bit data - asynchronous operation
1 0 1:8-bit data + wake up bit - asynchronous operation
1 1 0:Reserved. Do not use this combination
1 1 1:8-bit data + parity - asynchro nous operation
Number of stop bit selection asynchronous operation
0:One stop bit
1:Two stop bit
Receiver enable bit
0:Receiver disabled
1:Receiver enabled
Reset by hardware after reception of byte in synchronous mode)
Parity check enable bit: asynchronous operation
0:Ignore parity
1:Check parity
SxFEN
SxOEN
SxPE
SxFE
SxOE
SxODD
SxBRS
SxLB
SxR
Framing check enable bit - asynchronous operation
0:Ignore framing errors
1:Check framing errors
Overrun chec k ena ble bit
0:Ignore overrun errors
1:Check overrun errors
Parity error flag
Set by hardware on a parity error (SxPEN=’1’). Must be reset by software.
Framing error flag
Set by hardware on a framing error (SxFEN=’1’). Must be reset by software.
Overrun error flag
Set by hardware on an overrun error (SxOEN=’1’). Must be reset b y softw are.
Parity selection bit
0:Even parity (parity bit set on odd number of ‘1’s in data)
1:Odd parity (parity bit set on even number of ‘1’s in data)
Baud rate selection bit
0:Divide clock by reload-value + constant (depending on mode)
1:Additionally reduce serial clock to 2/3rd
Loopback mode enable bit
0:Standard transmit/receive mode
1:Loopback mo de ena bled
Baud rate generator run bit
0:Baud rate generator disabled (ASCx inactive)
1:Baud rate generator enabled
4/21
AN2354 ST10 ASC peripherals
1.1.2 Transmit and receive buffer registers
Writing to the Transmit buffer register SxTBUF (via an instruction or a PEC data transfer)
starts a transmission.
SxTBUF Reset value: 0000h
1514131211109876543210
------- Transmit Data Buffer
------- RW
SxRBUF Reset value: 0xxxh
1514131211109876543210
------- Received Data
R
Only the number of data bit which is determined by the selected operating mode is actually
transmitted. Bits written to positions 9 through 15 of register SxTBUF are always
insignificant. After a transmission is completed, the transmit buffer register is cleared to
0000h.
Data transmission is double-buffered, so a new character may be written to the transmit
buffer register before the transmission of the previous character is complete. This allows
back-to-back transmission of characters without gaps.
Data reception is enabled by the Receiver Enable bit SxREN. After reception of a character
is completed, the received data and, if provided by the selected operating mode, the
received parity bit can be read from the (read-only) Receive Buffer register SxRBUF.
Bits in the upper half of SxRBUF which are not valid in the selected operating mode are read
as zeros.
Data reception is double-buffered, so that reception of a second character may already
begin before the previously received character is read out of the receive buffer register.
The Loop-Back option (selected by bit SxLB) allows the data currently being transmitted to
be received simultaneously in the receive buffer.
5/21
ST10 ASC peripherals AN2354
1.2 Asynchronous operation
In this document only Asynchronous Operation is considered; to use the ST10F27x ASC
peripherals in synchronous mode, refer to the user manual. Asynchronous mode supports
full-duplex communication, where both transmitter and receiver use the same data frame
format and the same baud rate.
1.2.1 Asynchronous data frames
8-bit data frames either consist of 8 data bits D7...D0 (SxM = ‘001b’) or of 7 data bits
D6...D0 plus an automatically generated parity bit (SxM = ‘011b’). Parity may be odd or
even, depending on bit SxODD in register SxCON. An even parity bit is set if the modulo-2sum of the 7 data bits is ‘1’, in which case an odd parity bit is cleared. Parity checking is
enabled via bit SxPEN (always OFF in 8-bit data mode). If a wrong parity bit is received, the
parity error flag SxPE is set along with the error interrupt request flag. The parity bit itself is
stored in bit SxRBUF.7.
Figure 1. Asynchronous 8-bit data frames
(1st)
Start
bit
D0
(LSB)
D1
D2 D3 D4 D5
D6
D7 /
Parity
Stop
bIt
2nd
Stop
bit
9-bit data frames either consist of 9 data bits D8...D0 (SxM = ‘100b’), or of 8 data bits
D7...D0 plus an automatically generated parity bit (SxM = ‘111b’) or of 8 data bits D7...D0
plus a wake-up bit (SxM = ‘101b’). Parity may be odd or even, depending on bit SxODD in
register SxCON. An even parity bit is set, if the modulo-2-sum of the 8 data bits is ‘1’, in
which case an odd parity bit is cleared. Parity checking is enabled via bit SxPEN (always
OFF in 9-bit data and wake-up mode). If a wrong parity bit is received, the parity error flag
SxPE is set along with the error interrupt request flag. The parity bit itself is stored in bit 8 of
SxRBUF.
In wake-up mode, received frames are only transferred to the receive buffer register if the
9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request is activated and no
data is transferred.
This feature may be used to control communication in a multiprocessor system. When the
master proces sor wan ts to t ran smi t a bl ock of data to o ne of sev era l sla ves, it first send s out
an address byte which identifies the target slave. An address byte differs from a data byte in
that the additional 9th bit is a '1' for an address byte and a '0' for a data byte, so no slave is
interrupted by a data byte. An address byte interrupts all slaves (operating in 8-bit data +
wake-up bit mode), so each slave can examine the 8 LSBs of the received character (the
address).
The addressed slave switches to 9-bit data mode (by clearing bit SxM.0), which enables it to
also receive the data byte that will be coming (having the wake-up bit cleared). The slaves
that were not being addressed remain in 8-bit data + wake-up bit mode, ignoring the
following data byte.
6/21
AN2354 ST10 ASC peripherals
Figure 2. Asynchronous 9-bit data frames
(1st)
Start
bit
D0
(LSB)
D1
D2 D3 D4 D5 D7D6
9th
bit
• Data bit D8
• Parit y
• Wake-up bit
Stop
bIt
2nd
Stop
bit
1.2.2 Asynchronous transmission
The ASCx module uses a modulo 16 counter clocked by f
the next overflow of this counter provided that SxR is set and data has been loaded into
SxTBUF. The transmitted data frame consists of three basic elements:
1. the start bit
2. the data field (8- or 9-bit, LSB first, including a parity bit, if selected)
3. the delimiter (1- or 2-stop bit)
Data transmission is double-buffered. When the transmitter is idle, the transmit data loaded
into SxTBUF is immediately moved to the transmit shift register, thus freeing SxTBUF for the
next data to be sent.This is indicated by the transmit buffer interrupt request flag being set.
SxTBUF may now be loaded with the next data, while transmission of the previous one is
still going on.
The transmit interrupt request flag is set before the last bit of a frame is transmitted, that is,
before the first or the second stop bit is shifted out of the transmit shift register.
1.2.3 Asynchronous reception
A reception is initiated by a falling edge (1-to-0 transition) on pin RX, provided that bit SxR
and SxREN are set. The receive data input pin is sampled at 16 times the rate of the
selected baud rate. A majority decision of the 7th, 8th and 9th samples determines the
effective bit value. This avoids erroneous results that may be caused by noise.
Figure 3. ASCx asynchronous mode interrupt generation
/ 2. A transmission begins at
CPU
7/21
Loading...