ST AN2352 Application note

AN2352

Application note

PLL jitter effects on C-CAN modules of the ST10F27x

Introduction

PLL (Phase Locked Loop) is increasingly used in microcontrollers to achieve higher internal clock frequencies. This improves performance while reducing overall noise. One drawback in the use of PLL circuits is that they create a small but still measurable level of transient phase shifts, or CAN modules present in the devices of the family ST10F27x.

This document begins with a brief guide on configuring the bit time of the CAN protocol and then goes on to cover the characteristics of the PLL as implemented in the ST10F27x. The last section shows the results of the effect of the ST10F27x PLL on the C-CAN.

The information contained in this document is valid for the ST10F27x, ST10R27x, ST10F25x and ST10F296 devices.

jitter

. The aim of this note is to describe the effects of PLL jitter on the C-

April 2006 Rev 1 1/20

www.st.com

Contents AN2352

Contents

1 Configuration of the CAN bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Bit time and bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Propagation time segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Phase buffer segments and synchronization . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 System clock tolerance range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 Configuration of the CAN protocol controller . . . . . . . . . . . . . . . . . . . . . . 10

1.6 Calculation of the bit timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.1 Example for bit timing at high baud rate . . . . . . . . . . . . . . . . . . . . . . . . 13

1.6.2 Example for bit timing at low baud rate . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.1 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.2 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 ST10F27x PLL jitter effect in CAN protocol . . . . . . . . . . . . . . . . . . . . . 17

3.1 System clock tolerance range reduction in presence of PLL jitter . . . . . . 17

3.1.1 Range reduction percentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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AN2352 Configuration of the CAN bit timing

1 Configuration of the CAN bit timing

Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly.

In many cases, the CAN bit synchronization compensates a faulty configuration of the CAN bit timing to such a degree that an error frame is generated only occasionally. In the case of arbitration however, when two or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive.

The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.

1.1 Bit time and bit rate

CAN supports bit rates in the range of less than 1 Kbit/s up to 1000 Kbit/s. Each member of the CAN network has its own clock generator, usually a quartz oscillator. The timing parameter of the bit time (that is, the reciprocal of the bit rate) can be configured individually for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator periods (f

The frequencies of these oscillators are not absolutely stable. Small variations are caused by changes in temperature or voltage and by deteriorating components. As long as the variations remain within a specific oscillator tolerance range (df), the CAN nodes can compensate the different bit rates by resynchronizing to the bit stream.

) may be different.

osc

According to the CAN specifications, the bit time is divided into four segments (

● Synchronization segment

● Propagation time segment

● Phase buffer segment 1

● Phase buffer segment 2

Each segment consists of a specific, programmable number of time quanta (see The length of the time quantum (t the CAN controller’s system clock f

The C-CAN’s system clock f

),which is the basic time unit of the bit time, is defined by

and the Baud Rate Prescaler (BRP):

sys

= BRP / f

is the f

sys

CPU

or f

sys

/ 2 according to bit 2 of the XMSIC

CPU

Figure 1

Table 1

CAN bus level are expected to occur; the distance between the Sync_Seg and an edge that occurs outside of Sync_Seg is called the phase error of that edge. The propagation time segment (Prop_Seg) is intended to compensate the physical delay times within the CAN network. The phase buffer segments (Phase_Seg1 and Phase_Seg2) surround the sample point. The (Re)synchronization jump width (SJW) defines how far a resynchronization may move the sample point within the limits defined by the phase buffer segments to compensate edge phase errors.

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Configuration of the CAN bit timing AN2352

Figure 1. Bit timing

Nominal CAN bit time

Sync_ Prop_Seg Phase_Seg1 Phase_Seg2

Seg

1 Time quantum

(tq)

Sample point

Table 1

Table 1. Parameters of the CAN bit time

describes the minimum programmable ranges required by the CAN protocol.

Parameter Range Remark

BRP [1 .. 32] Sync_Seg 1 Prop_Seg [1 .. 8] Phase_Seg1 [1 .. 8] Phase_Seg2 [1 .. 8] SJW [1 .. 4]

Defines the length of the time quantum Fixed length, synchronizat ion of bus input to system clock

Compensates the physical delay times

May be lengthene d temporarily by synch roni za tion

May be shortened tempora rily b y sy nc hron iz ati on

May not be longer than either phase buffer segment

A given bit rate may be met by different bit time configurations but for the proper functioning of the CAN network, the physical delay times and the oscillator’s tolerance range must be taken into consideration.

1.2 Propagation time segment

This part of the bit time compensates physical delay times within the network. These delay times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes.

Any CAN node synchronized to the bit stream on the CAN bus will be out of phase with the transmitter of that bit stream due to the signal propagation time between the two nodes. The CAN protocol’s nondestructive bit-wise arbitration and the dominant acknowledge bit provided by the receivers of CAN messages require a CAN node transmitting a bit stream to also receive dominant bits transmitted by other CAN nodes that are synchronized to that bit stream. The example in

Figure 2

shows the phase shift and propagation times between two

CAN nodes.

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AN2352 Configuration of the CAN bit timing

Figure 2. Propagation time segment

Sync_Seg

Node B

Delay A_to_B Delay B_to_A

Node A

Delay A_to_B >= node output delay(A) + bus line delay(AÆB) + node input delay(B) Prop_Seg >= Delay A_to_B + Delay B_to_A Prop_Seg >= 2 • [max(node output delay + bus line delay + node input delay)]

Prop_Seg Phase_Seg1 Phase_Seg2

In this example, both nodes A and B are transmitters performing an arbitration for the CAN bus. Node A has sent its start of frame bit less than one bit time earlier than node B, therefore node B has synchronized itself to the received edge from recessive to dominant. Since node B has received this edge delay (A_to_B) after it has been transmitted, B’s bit timing segments are shifted in relation to A. Node B sends an identifier with a higher priority and therefore will win the arbitration at a specific identifier bit when it transmits a dominant bit while node A transmits a recessive bit. The dominant bit transmitted by node B arrives at node A after the delay (B_to_A).

Due to oscillator tolerances, the actual position of node A’s sample point can be anywhere inside the nominal range of node A’s phase buffer segments, so the bit transmitted by node B must arrive at node A before the start of Phase_Seg1. This condition defines the length of Prop_Seg.

If the edge from recessive to dominant transmitted by node B would arrive at node A after the start of Phase_Seg1, it is possible that node A samples a recessive bit instead of a dominant bit, resulting in a bit error and the destruction of the current frame by an error flag.

The error occurs only when two nodes with oscillators at opposite ends of the tolerance range and separated by a long bus line arbitrate for the CAN bus; this is an example of a minor error in the bit timing configuration (Prop_Seg too short) that causes sporadic bus errors.

1.3 Phase buffer segments and synchronization

The phase buffer segments (Phase_Seg1 and Phase_Seg2) and the synchronization jump width (SJW) are used to compensate the oscillator tolerance. The phase buffer segments may be lengthened or shortened by synchronization.

Synchronizations occur on edges from recessive to dominant; their purpose is to control the distance between edges and sample points.

Edges are detected by sampling the actual bus level in each time quantum and comparing it with the bus level at the previous sample point. A synchronization is possible only if a

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Configuration of the CAN bit timing AN2352

recessive bit was sampled at the previous sample point and if the actual time quantum’s bus level is dominant.

An edge is synchronous if it occurs inside of Sync_Seg, otherwise the distance between an edge and the end of Sync_Seg is the edge phase error, measured in time quanta. If the edge occurs before Sync_Seg, the phase error is negative, otherwise, it is positive.

Two types of synchronization exist: hard synchronization and resynchronization. A hard synchronization occurs once at the start of a frame. Resynchronizations occur only inside a frame.

● Hard synchronization

After a hard synchronization, the bit time is restarted at the end of Sync_Seg, regardless of the edge phase error. Thus hard synchronization forces the edge which placed the hard synchronization into the synchronization segment of the restarted bit time.

● Bit resynchronization

Resynchronization leads to a shortening or lengthening of the bit time such that the position of the sample point is shifted in relation to the edge.

When a positive phase error of the edge causes resynchronization, Phase_Seg1 is lengthened. If the magnitude of the phase error is less than the SJW, Phase_Seg1 is lengthened by the magnitude of the phase error, otherwise it is lengthened by the SJW.

When a negative phase error of the edge causes resynchroni z ati on, Pha se_ Se g2 is shortened. If the magnitude of the phase error is less than SJW, Phase_Seg2 is shortened by the magnitude of the phase error, otherwise it is shortened by the SJW.

When the magnitude of the phase error of the edge is less than or equal to the programmed value of the SJW, the results of hard synchronization and resynchronization are the same. If the magnitude of the phase error is greater than the SJW, the resynchronization cannot entirely compensate the phase error and an error of (phase error - SJW) remains.

Only one synchronization occurs between two sample points. The synchronizations maintain a minimum distance between edges and sample points, giving the bus level time to stabilize and filtering out spikes that are shorter than (Prop_Seg + Phase_Seg1).

Apart from noise spikes, most synchronizations are caused by arbitration. All nodes synchronize “hard” on the edge transmitted by the “leading” transceiver that started transmitting first, but due to propagation delay times, they are not ideally synchronized. The “leading” transmitter does not necessarily win the arbitration, therefore the receivers must synchronize themselves to different transmitters that subsequently “take the lead” and that are synchronized differently to the previously “leading” transmitter. The same happens at the acknowledge field, where the transmitter and some of the receivers must synchronize to the receiver that “takes the lead” in the transmission of the dominant acknowledge bit.

Synchronizations after the end of the arbitration are caused by oscillator tolerance, when the differences in the oscillator’s clock periods of transmitter and receivers sum up during the time between synchronizations (maximum 10 bits). These summarized differences may not be longer than the SJW, limiting the oscillator’s tolerance range.

The examples in

Figure 3

show how the phase buffer segments compensate phase errors. There are three drawings of each two consecutive bit timings. The upper drawing shows the synchronization on a “late” edge, the lower drawing shows the synchronization on an “early” edge and the middle drawing is the reference without synchronization.

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