ST AN2335 APPLICATION NOTE
AN2335
Application note
LIS302DL: 3-Axis - ±2g/±8g digital output
ultracompact linear accelerometer
Introduction
This document is intended to give application notes for the low-voltage 3-axis digital output
linear MEMS accelerometer provided in LGA package.
The LIS302DL is an ultra compact low-power three axes linear accelerometer that includes
a sensing element and an IC interface able to take the information from the sensing element
and to provide the measured acceleration to the external world through I
interface.
The sensing element, capable of detecting the acceleration, is manufactured using a
dedicated process developed by ST to produce inertial sensors and actuators in silicon.
The IC interface instead is manufactured using a CMOS process that allows high level of
integration to design a dedicated circuit which is factory trimmed to better match the sensing
element characteristics.
The LIS302DL has a user selectable full scale of ±2g, ±8g and it is capable of measuring
accelerations with an output data rate of 100Hz or 400Hz. A self-test capability allows the
user to check the correct operation of the system.
2
C/SPI serial
The device features two independent highly programmable interrupt sources that can be
configured either to generate an inertial wake-up interrupt signal when a programmable
acceleration threshold is exceeded along one of the three axes or to detect a free-fall event.
Two independent pins can be configured to provide interrupt signals to connected devices.
The LIS302DL is available in plastic SMD package and it is specified over a temperature
range extending from -40°C to +85°C.
The ultra small size and weight of this package make it an ideal choice for handheld portable
applications such as cell phones and PDAs or any other application where reduced package
size and weight are required.
October 2006 Rev 2 1/40
www.st.com
Contents AN2335
Contents
1 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical connection and board layout hints . . . . . . . . . . . . . . . . . . . . . 7
2.1 Electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 I2C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.1 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 I2C Subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.2 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.3 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.4 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.2 Registers loaded at Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 About control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 OUTX (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4 OUTY (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/40
AN2335 Contents
7.5 OUTZ (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Free-Fall and Wake-Up Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.4 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.5 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.6 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.7 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.8 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.9 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1 START-UP SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2 READING ACCELERATION DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2.1 Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2.2 Using the Data-Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3 Understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4 Interrupt generation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.5 INERTIAL WAKE-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5.1 HP Filter Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5.2 Using the HP Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.6 Free-Fall Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6.1 Roll function not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6.2 Roll function applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.7 Output data rate selection and reading timing . . . . . . . . . . . . . . . . . . . . . 37
9.8 Data ready vs. interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
List of tables AN2335
List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Output Data Registers content vs. Acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6. Output Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Timing Value to Avoid Loosing the Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4/40
AN2335 List of figures
List of figures
Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. LIS302DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. I2C Subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. SPI Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Multiple Bytes SPI Write Protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. SPI Read Protocol In 3-wires Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Digital Processing Chain Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. FF_WU_CFG_1,2 High and Low value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. DCRM bit function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. Interrupt Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. Free-Fall, Wake-Up Interrupt Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. Reading Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. Interrupt and dataready signal generation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 17. Data Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5/40
Theory of operation AN2335
1 Theory of operation
The LIS302DL is an ultracompact, low-power, digital output 3-axis linear accelerometer
packaged in a LGA package. The complete device includes a sensing element and an IC
interface able to take the information from the sensing element and to provide a signal to the
external world through an I
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the sense capacitor.
At steady state the nominal value of the capacitors are few pico Farad and when an
acceleration is applied the maximum variation of the capacitive load is of few femto Farad.
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by and
by analog-to-digital converters.
The acceleration data may be accessed through an I
device particularly suitable for direct interfacing with a microcontroller.
2
C/SPI serial interface (Figure 1).
2
C/SPI interface thus making the
Data synchronization in digital system employing the device is made simpler through the
usage of the Data-Ready signal (RDY) which indicates when a new set of measured
acceleration data is available thus simplifying data synchronization in digital system
employing the device itself.
The LIS302DL features also two independent fully programmable interrupt sources which
can be programmed to generate an interrupt signal when a programmable acceleration
threshold is exceeded along one of the three axes or to detect a free-fall event.
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).
The trimming values are stored inside the device by a non volatile structure. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during the normal operation. This allows the user to employ the device without
further calibration.
Figure 1. Device block diagram
X+
I2C
SPI
CS
SCL/SPC
SDA/SDO/SDI
SDO
INT 1
INT 2
Y+
Z+
a
MUX
Z-
Y-
X-
REFERENCESELF TEST
CHARGE
AMPLIFIER
TRIMMING
CIRCUITS
A/D
CONVERTER
CONTROL LOGIC
CLOCK
CONTROL LOGIC
&
INTERRUPT GEN.
6/40
AN2335 Electrical connection and board layout hints
2 Electrical connection and board layout hints
2.1 Electrical connection
The typical electrical connection of the LIS302DL is shown in Figure 2
Figure 2. LIS302DL electrical connection
Vdd
10uF
100nF
GND
6
Top VIEW
8
CS
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
INT1
INT2
1
SDO
Vdd_IO
13
SDA/SDI/SDO
SCL/SPC
Z
Y
6
TOP VIEW
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
1
8
X
13
The LIS302DL is designed to operate with a voltage supply spanning from 2.16V up to 3.6V
while the serial interface can work down to 1.8V.
The device core is supplied through Vdd line (Vdd typ=2.5V) while the I/O pads are supplied
through Vdd_IO line. The typical current consumption in normal mode at 2.5V is 400μA.
Both the voltage supplies must be present at the same time to have proper behavior of the
IC. It is possible to remove Vdd mantaining Vdd_IO without blocking the communication bus.
Adequate power supply decoupling is required to ensure IC performances. The optimum
decoupling is achieved by using two capacitors of different types that target different kinds of
noise on the power supply leads. To attenuate high frequency transients, spikes, or digital
hash on the line it is recommended the use of one 100nF ceramic or polyester capacitor
which must be placed as close as possible to device Vdd lead. For filtering lower-frequency
noise signals, a larger aluminum capacitor of 10μF or greater should be placed near the
device in parallel to the former capacitor. It is recommended to place these capacitors as
near as possible to the pin 6 of the device.
The functionality of the device and the measured acceleration data are selectable and
accessible through the I
SDO allows to select among two device addresses in case two sensors must be connected
on the same bus. Whenever one single sensor is present on the same I
2
C/SPI interface. When using the I2C, CS must be tied high while
2
C bus it is
recommended either to connect SDO to Vdd_IO or to leave it floating.
7/40
Absolute maximum ratings AN2335
2.2 Soldering information
The LGA-14 package is lead free and green package qualified for soldering heat resistance
according to JEDEC J-STD-020C. Land pattern and soldering recommendations are
available upon request.
3 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 1. Absolute maximum ratings
Symbol Ratings Maximum Value Unit
Vdd Supply voltage
Vdd_IO I/O pins Supply voltage
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, CK)
Acceleration (Any axis, Powered, Vdd=2.5V)
Acceleration (Any axis, Unpowered)
A
A
Vin
POW
UNP
(1)
(1)
-0.3 to 6 V
-0.3 to 6 V
-0.3 to Vdd_IO +0.3 V
3000g for 0.5 ms
10000g for 0.1 ms
3000g for 0.5 ms
10000g for 0.1 ms
T
T
STG
Operating Temperature Range -40 to +85 °C
OP
Storage Temperature Range -40 to +125 °C
ESD Electrostatic discharge protection Class 1: 0 - 2KV HBM
1. Supply voltage on any pin should never exceed 6.0V
Warning: This is a ESD sensitive device, improper handling can cause
permanent damages to the part.
Warning: This is a mechanical shock sensitive device, improper
handling can cause permanent damages to the part.
8/40
AN2335 Digital interfaces
4 Digital interfaces
The registers embedded inside the LIS302DL may be accessed through I2C and SPI serial
interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface
mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I
line must be tied high (i.e connected to Vdd_IO).
Table 2. Serial interface pin description
Pin Name Pin Description
2
C interface, CS
CS
SCL/SPC
SDI/SDA/SDO
SDO
SPI chip select (CS)
I2C/SPI selector (1: I2C mode; 0: SPI enabled)
SPI CK line (SCL)
2
C clock line (SPC)
I
2
I
C serial data (SDA)
SPI data in (SDI)
SPI data out (SDO) -for 3-wire SPI mode-
2
C less significant bit of device address
I
SPI data out (SDO) -for 4-wire SPI mode-
4.1 I2C Bus interface
The LIS302DL I2C is a bus slave. The I2C is employed to write/read the data into/from the
registers.
The relevant I
Table 3. Terminology
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
2
C terminology is shown in Tab l e 3 :
Term Description
Master
Slave The device addressed by the master
The device which initiates a transfer, generates clock signals and terminates
a transfer
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the
Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the
data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS302DL. When the bus is free both the lines are high.
2
The I
C interface is compliant with Fast Mode (400 kHz) I2C standards as well as the
Normal Mode.
9/40
Digital interfaces AN2335
4.1.1 I2C Operation
The transaction on the bus is started through a START (ST) condition which is defined as a
HIGH to LOW transition on the data line while the SCL line is held HIGH. After the START
condition has been generated by the Master, the bus is considered busy. The next byte of
data transmitted contains the address of the slave in the first 7 bits and the eighth bit tells
whether the Master is receiving data from the slave or transmitting data to the slave (SAD
subsequence). When an address is sent, each device in the system compares the first
seven bits after a start condition with its own address. If they match, the device considers
itself addressed by the Master.
The Slave ADdress (SAD) associated to the LIS302DL may be selected among the two
predefined values 0011100b or 0011101b depending on the logic level present on SDO pin.
In details, if SDO pin is either connected to Vdd_IO or left unconnected the slave address is
0011101b, otherwise when it is connected to GND the slave address is 0011100b.
Whenever it is not needed to place two sensors on the same bus it is recommended to use
the slave address 0011101b by either connecting the SDO pin to Vdd_IO or leaving it
floating.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
2
The I
C embedded inside the LIS302DL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a salve address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write. Otherwise if the MSB of the SUB field is ‘0’, the SUB will
remain unchanged and multiple read/write on the same address can be performed.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged.
Transfer when Master is writing one byte to slave
Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK
Transfer when Master is writing multiple bytes to slave:
Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK
Transfer when Master is receiving (reading) one byte of data from slave:
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA
10/40
AN2335 Digital interfaces
Transfer when Master is receiving (reading) multiple bytes of data from slave
Master ST SAD + W SUB SR SAD + R MAK
Slave SAK SAK SAK DATA
Master MAK NMAK SP
S la ve DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
4.1.2 I2C Subsequences
In order to better define subsequences and to clarify line SCL and SDA behavior, a
description containing discrete value of SCL and SDA will follow. In column there is the
value present on line SCL and SDA in discrete timing. These simple subsequences are
used to realize complex commands described in the following paragraph.
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Digital interfaces AN2335
Figure 3. I2C Subsequences
ST: START condition
SCL 1111
SDA 1100
SR: Repeated START condition
SCL 1111
SDA 1100
SAD: Slave address (binary address: abcdefgh. In LIS302DL “abcdef” = “001110”)
SCL 00110 0110 0110 0110 0110 0110 0110 0110
SDA 0aaaa bbbb cccc dddd eeee f f f f gggg hhhh
Bit g=0 if SDO connected to GND, g=1 if SDO pad connected to Vdd
Bit h=0 => write, h=1 => read
SAK: Slave acknowledge (Z means high impedance)
SCL 0011
SDA (force) ZZZZ Check that SDA is 0 after SCL=1
SDA (read) XX00
SUB: Sub address (binary address: a0cdefgh)
SCL 00110 0110 0110 0110 0110 0110 0110 0110
SDA 0aaaa 0000 cccc dddd eeee f f f f gggg hhhh
Bit a=0 => do not increment address in multiple mode
a=1 => increment address in multiple mode
DATA (Master): send DATA byte (binary number: abcdefgh)
SCL 00110 0110 0110 0110 0110 0110 0110 0110
SDA 0aaaa bbbb cccc dddd eeee f f f f gggg hhhh
DATA (Slave): read DATA byte (binary number: abcdefgh)
SCL 00110 0110 0110 0110 0110 0110 0110 0110
SDA (force) ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ
SDA (read) a b c d e f g h
SP: STOP condition
SCL 1111
SDA 0011
MAK: Master Acknowledge
SCL 0011
SDA 0000
NMAK: No Master Acknowledge
SCL 0011
SDA ZZZZ or 1111
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