Reference design: high performance, L6599-based HB-LLC
adapter with PFC for laptop computers
Introduction
This note describes the performances of a 90 W, wide-range mains, power-factor-corrected
AC-DC adapter reference board. Its electrical specification is tailored on a typical hi-end
portable computer power adapter. The peculiarities of this design are the very low no-load
input consumption (<0.4 W) and the very high global efficiency.
The architecture is based on a two-st age approach: a front -end PFC pre-regulato r based on
the L6563 TM PFC controller and a downstream multi-resonant half-bridge converter that
makes use of the new L6599 resonant controller. The Standby function of the L6599,
pushing the DCDC converter upon recognition of a light load to work in burst mode and the
logic dedicated to stop the PFC stage allows meeting the severe no-load consumption
requirement.
The PFC TM operation and the top-level efficiency performance of the HB-LLC topology
provide also a very good overall efficiency of the circuit.
AN2321Main characteristics and circuit description
1 Main characteristics and circuit description
The main characteristics of the SMPS are listed here below:
●Universal inpu t mains range: 90÷264 Vac - frequency 45 to 65 Hz
●Output v oltage: 19 V@4.7 A continuous operation
●Mains harmonics: Compliance with EN61000-3-2 specifications
●Standby mains consumption: Typ. 0.4 W @230 Vac; Max 0.5 W @265 Vac
●Overall efficiency: better than 90%
●EMI: Compliance with EN55022-class B specifications
●Safety: Compliance with EN60950 specifications
●Low profile design: 25 mm maximum height
●PCB single layer: 78x174 mm, mixed PTH/SMT technologies
The circuit consists of two stages: a front - end PF C imp l eme nt ing the L65 63 and a r eson ant
DC/DC converter based on the new resonant controller, the L6599. The Power Factor
Corrected (PFC) stage delivers a stable 400 VDC and provides for the reduction of the
mains harmonic, allowing to meet European standard EN61000-3-2. The controller is the
L6563 (U1), working in transition mode and integrating all functions needed to control the
PFC and interface the downstream resonant converter. The power stage of the PFC is a
conventional boost converter, connected to the output of the rectifier bridge. It includes coil
L2, diode D4 and capacitor C9. The boost s witch is re presented by the po w er MOSFET Q1.
The L2 secondary winding (pins 8-10) is dedicated to provide to the L6563 the information
about the PFC coil core demagnetization, necessary to the controller for the TM operation.
The divider R1, R2 and R14 provides to the L6563 the information of the instantaneous
voltage that is used to modulate the boost current, and to derive some further information
like the average value of the AC line, used by the V
function keeps the ou tput voltage almost independent of the mains on e . The divide r R7, R8 ,
R9, R10 detects the output voltage . The second divider R11, R12, R13 and R28 protects the
circuit in case of voltage loop fail. The second stage is a resonant converter, half bridge
topology, working in ZVS. The controller is the new L6599, incorporating the necessary
functions to drive properly the Half-bridge by a 50 percent fixed duty cycle with dead-time,
working with variable frequency.
(voltage feed-forward) function. This
FF
The main features of the L6599 are a non-linear soft-start, a new current protection pin
(ISEN, pin 6) that programs the hiccup mode timing, a dedicat ed pin for sequencing or
brown-out (LINE) and a stand-by pin (STBY) for burst mode operation at light load. The
transformer uses the integrated magnetic approach, incorporating the resonant series
inductance. Thus, no any external additional coil is needed for the resonance. The
transformer configuration chosen for the secondary winding is centre tap, using two
Schottky rectifiers, type STPS10L60FP. The feedback loop is implemented by means of a
typical circuit using a TL431 modifying the current in t he optocoupler diode . The optocoupler
transistor modulates the current from pin 4, so the frequency will change accordingly, thus
achieving the output voltage regulation. Resistor R34 sets the maximum operating
frequency and the load at which the controller starts to work in Burst mod e. In case of a
short circuit, the current into the primary winding is detected by the lossless circuit R41,
C27, D11, D10, R39, and C25 and it is fed into the pin 6. In case of o v erload, th e v oltage on
pin #6 will overpass an internal threshold that will trigger a protection sequence via pin #2,
keeping the current flo wing in the circuit at a safe lev el. In case of output v oltage loo p f ailure,
the intervention of the zener diode connected to pin #8 (DIS) will activate the latched
protection of the L6599. The DIS pin can be also activated by the L6563 via the
PWM_LATCH pin in case of PFC loop failure.
5/29
Main characteristics and circuit descriptionAN2321
Figure 1.Electrical diagram
+19V
RTN
J2
1
2
C32
100N
C31
L3
2u2
100uF-35V YXF
C21
C20
2N2 - Y1
R11
3M0
R12
3M0
R13
5K1
R28
27K
R7
1M0
R8
1M0
R10
15K
R9
82K
C9
R6
NTC_1 0R S23 6
47uF-450V
D4
STTH2L06
D3
1N4005
2-35
L2
86A-5158C
810
R3
2M4
D1
GBU4J
C5
470N-400V
R69
4K7
D20
BZV55- B15
Q9
BC847C
D7
LL4148
R70
100K
R71
Q10
R4
2M4
Q8
6K8
BC847C
D16
D17
BZV55 -B1 2
LL4148
STQ1HNK60R
R20
10K
2N2 - Y1
C18
2u2-6.3V
R44
2K7
R101
R19
56K
C39
100N
R66
2K2
Q6
BC847C
Q5
BC847C
R65
+19V@4.7A
D18
U2
*
39R
47K
D15
BZV5 5-C18
R56
1K8
R62
4K7
470uF-35V YXF
C30
470uF-35V YXF
C29
STPS10L60FP
D12
13
14
2
Q3
STP9NK50Z
LL4148
C19
100N
16
VBOOT
L6599D
CSS
1
Q1
4
C26
R58
100K
10uF-50V
R25
56R
13
14
15
NC
OUT
HVG
CF
DELAY
3
2
4
C45
220NF
C17
470PF
R24
1M0
R31
R30
STP12 NM50 FP
R46
100K
R27
470R
R21
39R
D13
STPS10L60FP
11
12
5
C28
22N
R59
100K
Q4
STP9N K50Z
R38
56R
C40
100N
D19
11
10
12
VCC
LVG
GND
LINE
STBY5RFmin
ISEN
7
6
R34
3K3
15K
10R
R23
R22
C43
0R47
0R47
C16
2N2
R49
39K
R43
51R
C36
1uF-50V
R42
5K6
T1
86A-5166A
6
R41
100R
C27
220PF
D10
LL4148
LL4148
4N7
D11
LL4148
9
R39
130R
PFC_STOP
C25
DIS
8
100N
C44
3N9
R32
47R
D8
BZV55 -B2 4
R29
1K0
R47
1K0
12
43
R60
10K
C23
10N
Q2
BC847C
R51
120K
R50
6K2
R48
47K
C34
220N
U4
TL431AIZ
U3
SFH617A-2
R40
6R8
D9
LL4148
220uF-35V
C24
R35
0R0
R37
100K
R52
6K8
C15
C4
470N-X2
L1
86A-5163
C3
C2
2N2
F1
FUSE 4A
1
J1
INPUT CONN.
2N2
C1
470N-X2
2
3
R1
1M0R21M2
90-264Vr ms
10uF-50V
U1
L6563
C14
100N
6/29
14
VCC
INV
1
C13
1uF
11
13
12
GD
ZCD
RUN
GND
MULT
COMP
3
2
R18
56K
PWM_STOP
PWM_LATCH
C10
PFC_OK
VFF5CS
TBO
4
C11
R14
18K
7
6
C12
470N
10N
150K
R15
22N
C22
220PF
R26
240K
*: R101 MOUNTED BY REWORKING
8
10
9
AN2321Test results
2 Test results
2.1 Efficiency measurements
Table 1 and Table 2 show the output voltage measurements at nominal mains with different
load conditions. Efficiency is then calcu lated . For all measurements, both at full load and no
load operation, the input pow er has been mea sured b y a digita l po wer meter, Yokogawa WT-
210. Particular attention has to be paid when measuring input power at full load in order to
avoid measurem ent errors due to the voltage drop on cables and connections. Therefore
please connect the WT210 voltmeter termination to the board inpu t connector . F or the same
reason please measure the output voltage at the output connector or use th e r emot e d etect
option of your active load for a correct voltage measurement.
Table 1.Efficiency measurements -
Vout [V]Iout [A]Pout [W]Pin [W]Efficiency (%)
18.954.7189.2599.1390.04
18.953.7270.4978.0090.38
18.972.751.2256.5590.57
18.981.7132.4636.0090.16
18.991.018.9921.7087.51
18.990.59.5011.3084.03
Vin=115 Vac
19.000.254.755.8681.06
Table 2.Efficiency measurements - Vin=230 Vac
Vout [V]Iout [A]Pout [W]Pin [W]Efficiency (%)
18.954.7189.2597.2391.80
18.963.7270.5376.7491.91
18.972.751.2255.8591.71
18.981.7132.4635.5791.24
18.991.018.9921.3089.15
19.000.59.5010.8787.40
19.000.254.755.7782.32
In Table 1,Table 2 and Figure 2, the overall circuit efficiency is measured at different loads,
powering the board at the tw o nominal input mains v oltages. The measures hav e been do ne
after 30 minutes of warm-up at maximum load. The high efficiency of the PFC working in
transition mode and the very high efficiency of the resonant stage w orking in ZVS , provides
for an overall efficiency better than 90%. This is a significant high number for a two-stage
converter delivering an output current of 4.7 amps, especially at low input mains voltage
where the PFC conduction losses increase. Even at lower loads, the efficiency remains still
high.
7/29
Test resultsAN2321
Figure 2.Efficiency vs. Pout
Effi ci en cy v s P out
Eff. @115Vac
Eff. @230Vac
O/P P o wer
Efficiency
94.00
92.00
90.00
88.00
86.00
84.00
82.00
80.00
78.00
76.00
74.00
8971513219105
The global efficiency at full load has been measured with good results even at the limits of
the input voltage range :
Vin = 90Vac - full load
Pin = 100.5 W
Efficiency = 88.9%
Vin = 264 Vac - Full load
Pin = 96.3 W
Efficiency = 92.6%
2.2 Resonant stage operating waveforms
Figure 3.Resonant circuit primary side waveforms
CH1: L6599 - V
CH2: L6599 - V
(HB voltage)
PIN14
(CF)
PIN3
CH3: +400 V PFC Output voltage
CH4: T1 primary winding current
In Figure 3 are reported some waveforms during steady state operation of the circuit at full
load. The CH2 waveform is the oscillator signal at pin #3 of the L6599, while the CH3
waveform is the PFC output voltage , po wering th e resonant stage . The CH1 tra ce is the ha lf
bridge waveform, driving the resonant circuit. In the picture it is not obvious, but the
switching frequency is normally slightly modulated following the PFC 100 Hz ripple that is
rejected by the resonant control circuitry. The switching frequency has been chosen around
90 kHz, in order to have a good trade off between transformer losses and its dimensions.
8/29
AN2321Test results
The transformer primary current wave shape is the CH4 trace. As shown, it is almost
sinusoidal, because the operating frequency is slightly above the resonance of the leakage
inductance and the resonant capacitor (C28).
In this condition, the circuit has a good margin for ZVS operations providing good efficiency
and the almost sinusoidal wave shape provides for an extremely low EMI generation.
Figure 4.Resonant circuit secondary side waveforms
CH2: +19V Output voltage ripple and noise
CH3: D12 rectifiers anode voltage
CH4: D12 rectifiers current
In Figure 4 are represented some waveforms relevant to the secondary side: the rectifiers
reverse voltage is measured by CH3 and the peak to peak value is indicated on the right of
the picture. It is a bit higher than the theoretical value that would be 2(V
about 40 V. It is possible to observe a small ringing on the bottom side of the waveform,
responsible for this difference. The channel CH4 (green in the picture) shows the current in
the diode D12, equal to that one flowing in D13. Even this current shape is almost a sine
wave, its average value is half of the output current. The ripple and noise on the output
voltage is measured by CH2.
Thanks to the advantages of the resonant converter, the high frequency ripple and noise of
the output voltage is o nly 100mV (0.52%) including spik es, whi le the resi dual ripple at mains
frequency is 130 mV at maximum load and any line condition.
2.3 Stand-by & no load power consumption
The board is specifically designed for li ght load and zero load operation, like during
operation with load disconnected. The result s are reported in the diagram ofFigure 5, he re
following. As high lighted in the diagram of Figure 4, the input power at no load is always
below 0.4 W for any input mains voltage. Thanks to the L6599 stand-by function, at light load
conditions both the resonant converter and the PFC work skipping switching cycles,
according to the load. In fact, the L6599 via the PFC_ST OP pin (#9) stops the operation of
the L6563 during the burst mode off-time.
OUT+VF
), hence
9/29
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