ST AN2281 Application note

AN2281

Application note

Low cost self-synchronizing PMAC

motor drive using ST7FLITE35

Introduction

Due to their high efficiency, power by size ratio and silent operation, Permanent Magnet AC (PMAC) motors are increasingly used in many applications. They are becoming the predominant type of motor used in applications where the above advantages are required, especially fans, compressors and pumps.

Since PMAC motors are synchronous machines, to get the best efficiency from them, the excitation must be switched from one motor phase to another in exact synchronism with the rotor motion. This concept, commonly known as self-synchronization, uses direct feedback of the rotor angular position to ensure that the PMAC machine never loses synchronization.

This application note describes a low-voltage single-sensor three-phase AC permanent magnet motor, also known as PMAC or BLAC (brushless AC) control system.

It includes a depiction of:

● Reference schematics, which can be used for up to 12V-50W PMAC motors and based

on ST7LITE35 microcontroller and on STS8C5H30L complementary P-channel and Nchannel MOSFETs,

● Firmware library, developed with the Cosmic C compiler and STVD7 release 3.x.x. It is

composed of several C modules containing a set of convenient functions for sinusoidal waveform generation, synchronization mechanism and closed loop control of PMAC motors.

March 2006 Rev 1 1/38

www.st.com

Contents AN2281

Contents

1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 PMAC motor control basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Implementation on the ST7Lite35 microcontroller . . . . . . . . . . . . . . . . . 6

3.1 ST7Lite3x 12-bit Autoreload timer (ART) in PWM mode . . . . . . . . . . . . . . 6

3.2 Lite Timer for measuring the rotor speed . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Lite Timer configuration for measuring the Hall sensor period . . . . . . . . . 10

4 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Gate driving and dead time insertion circuit . . . . . . . . . . . . . . . . . . . . . . . 14

5 Library parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Phase synchronization and Phase angle optimization . . . . . . . . . . . . . . . 16

5.2 Start-up phase parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Getting started with the ST7FLITE35-based PMAC motor control

system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 Hardware connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 Library source code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 How to set the library parameters to run a PMAC motor for the first time 23

7 Conclusion and results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Motor control related CPU load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2 Code memory size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.3 Example oscilloscope captures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Appendix A List of software functions and Interrupt Service Routines . . . . . . 31

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AN2281 Theory of operation

1 Theory of operation

Standard induction motors, normally designed to run at base speeds between 850 to 3500 rpm, are not particularly well suited to low-speed operation, as their efficiency drops with the reduction in speed. They may also be unable to deliver sufficient smooth torque at low speeds.

The use of a gearbox is the traditional mechanical solution to this problem. However, the gearbox is a complicated piece of machinery that takes up space, reduces efficiency, and needs both maintenance and significant quantities of oil. Replacing the gearbox with permanent magnet motors/drive configurations saves space and installation costs, energy and maintenance, and provides more flexibility in production and facility design. These motors use magnets to produce the magnetic rotor field rather than the magnetizing component of the stator current like in the induction motor.

Figure 1 shows a cross section of a typical permanent magnet (PM) motor. The rotor has an

iron core on the surface of which is mounted a thin permanent magnet. An alternating magnet of opposing magnetization produces radial directed flux density across the air gap. This flux then reacts with currents in the stator windings to produce torque.

The two most common types of brushless PM motors are classified as:

● Synchronous, with a uniformly rotating stator field as an induction motor. This type is

also referred to as PMAC (BLAC)

● Switched or trapezoidal, with stator fields that are switched in discrete steps. This type

is also referred to as PMDC (BLDC)

Figure 1. Cross-section of PM motors

-b

-a

1 pole pair

-c

-b

-c

-a

3 pole pairs

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Theory of operation AN2281

Figure 2 provides a direct comparison of ideal current excitation waveforms for typical three-

phase sinusoidal and trapezoidal PM motors.

Figure 2. Sinusoidal (PMAC) and trapezoidal (PMDC or 6-step) current excitation

123456

Phase A

120°

240°

(a) Sinusoidal

Phase B

Phase C

120°

240°

(b) Trapezoidal

PMDC motors are specifically designed to develop nearly constant output torque when excited with a six-step switched current waveform. Their stator windings are concentrated into narrow phase belts. The resulting back-EMF voltage, induced in each stator phase winding during rotation, can be modeled quite accurately as a trapezoidal waveform.

PMAC motors are, on the contrary, specifically designed to be excited with a sinusoidal current waveform. Their stator windings are typically distributed over multiple slots in order to approximate a sinusoidal distribution so that the resulting back-EMF waveforms generated are sinusoidal shaped.

Except for the intrinsic characteristics of stator windings, a PM machine can be excited with both drive methods without any great loss of efficiency. The main difference between the two types of excitation consists of the acoustic noise generated. The abrupt variation of the trapezoidal phase current, in fact, generally introduces a great amount of acoustic and electronic noise in comparison to the sinusoidal phase current.

In the 6-step PMDC method, one of the three phases is always unexcited, making it possible to access back-EMF zero-crossing (i.e. rotor position) information, while in a PMAC motor drive the three phases are always excited during the electrical period, making it necessary to use at least one rotor position sensor.

Nevertheless, the relatively reduced amount of noise when a PM motor is excited with sinusoidal current in comparison to 6-step excitation makes it the preferred choice for all applications in which audible noise is a critical issue.

Actually, some complex algorithms for driving PMAC sensorless motors have been developed, but they require more computational power than would be available from an 8-bit microcontroller.

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AN2281 PMAC motor control basics

2 PMAC motor control basics

PMAC machines are synchronous so the average torque can be produced only when the excitation is synchronized with the rotor frequency and instantaneous position. By continuously detecting the rotor angular position and rotational speed, the excitation can be properly switched among the PMAC motor phases in exact synchronism with the rotor motion.

This concept, commonly known as self-synchronization, uses direct feedback of the rotor angular position to ensure that the PMAC machine never loses synchronization. Generally, Hall sensors are used to get information about the angular position of rotor, detecting the magnetic field direction generated by the rotor. In particular, the usage of only one sensor is supported with the system presented in this document.

Figure 3 shows the block diagram of the PMAC self-synchronization algorithm implemented

in the software library.

Figure 3. PMAC motor control basics: the block diagram

Phase

synchronization

Each of the three phases of the motor is supplied by a sinusoidal waveform whose frequency, amplitude and phase have been respectively indicated with f, A* and Φ.

Every time an Hall sensor signal transition occurs, the algorithm estimates the rotor frequency f* and utilizes this value as statorical frequency (f) for the successive electrical semi-period. Meanwhile, the phase of the sine wave is also updated and set equal to phase angle Φ or Φ+π depending on the Hall sensor edge transition (rising or falling). Generally, for a large operating speed range, the proper value of Φ is strongly dependent on the motor speed affecting the driving efficiency. The provided library allows you to set the optimum Φ as a linear function of the speed (in rpm).

V/F

Limitation

A* sin(2πf+Φ)

Motor

f=f*

Rotor Position

Phase angle optimization

Hall

sensor

Since there are no direct information on current and torque, a V/F limitation has also been implemented in order to allow you to limit the maximum flowing current for a given speed.

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Implementation on the ST7LITE35 microcontroller AN2281

3 Implementation on the ST7LITE35 microcontroller

The algorithm presented in the previous paragraph has been implemented on the ST7FLITE35 microcontroller. Although they belong a family of low-cost ST microcontrollers, ST7FLITE3x devices nevertheless have all the necessary features to be able to drive a PMAC motor using one Hall sensor.

● The Lite Timer has been used to measure the period (or better the semi-period) of the

Hall sensor signal and the 12-bit autoreload Timer with its 4 PWM outputs has been used to generate the three voltage phases.

● The internal RC oscillator with 1% tolerance allows you to further reduce the cost and

the size of the overall system and avoid PCB layout optimization issues related to the presence of external oscillators.

3.1 ST7LITE3x 12-bit autoreload timer (ART) in PWM mode

3.1.1 Block diagram and functional description

The 12-bit ART is based on one or two free-running 12-bit upcounters with an input capture register and four PWM output channels.

The PWM mode of the dual 12-bit autoreload timer allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins. The four PWM signals can have the same frequency (f

) or two different frequencies depending on the ENCNTR2 bit which

PWM

enables single timer or dual timer mode (see Figure 4 and Figure 5).

Figure 4. The dual 12-bit autoreload timer: single timer mode (ENCNTR2=0)

ATIC

Edge Detection Circuit

12-Bit Autoreload Register 1

Clock Control

CPU

from Lite Timer

1ms

12-Bit Upcounter 1

12-bit Input Capture

PWM0 Duty Cycle Generator

PWM1 Duty Cycle Generator

PWM2 Duty Cycle Generator

PWM3 Duty Cycle Generator

OVF1 Interrupt

Output Compare

Dead Time

Generator

DTE bit

CMP Interrupt

OE0

OE1

OE2

OE3

Break Function

BPEN bit

PWM0

PWM1

PWM2

PWM3

The PWM frequency is controlled by the counter period and the ATR register value following formula

PWM

= f

COUNTER

/ (4096 - ATR) (3.1)

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AN2281 Implementation on the ST7LITE35 microcontroller

In dual timer mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2 and ATR2.

The duty cycle is selected by programming the DCRx registers. These are preload registers. The DCRx values are transferred in active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set.

The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls the PWMx outputs driven by counter 2.

PWM generation and output compare are done by comparing these active DCRx values with the counter.

Figure 5. The dual 12-bit autoreload timer: dual timer mode (ENCNTR2=1)

ATIC

Edge Detection Circuit

12-Bit Autoreload Register 1

Clock Control

12-Bit Autoreload Register 2

CPU

1ms

12-Bit Upcounter 1

12-Bit Upcounter 2

12-bit Input Capture

PWM0 Duty Cycle Generator

PWM1 Duty Cycle Generator

OVF1 interrupt OVF2 interrupt

PWM2 Duty Cycle Generator

PWM3 Duty Cycle Generator

Output Compare

Dead Time

Generator

DTE bit

CMP Interrupt

OE0

OE1

OE2

OE3

Break Function

BPEN bit

PWM0

PWM1

PWM2

PWM3

At reset, the counter starts counting from 0. When an upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to the active Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the active DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active DCRx register must be greater than the contents of the ATR register.

The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set.

The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register.

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Implementation on the ST7LITE35 microcontroller AN2281

3.1.2 Three-phase sinusoidal waveform generation

In order to produce the three-phase sinusoidal voltages, three of the four available PWM outputs have been enabled. Since these three PWM signals must have the same frequency, single timer mode has been selected (ENTNCR2=0).

To allow the necessary duty cycle updating, the OVFIE bit of the ATCSR register has been set. This way an interrupt is generated every 1/f

Furthermore, to reduce the acoustical noise introduced by the switching of the three-phase inverter, a PWM frequency out of the audible range has been chosen. In particular, to achieve the selected 15.625 KHz switching frequency, f f

(8 MHz) and, consequently, using formula (3.1), the ATR1 registers have been written

CPU

with value 3584.

To reduce the contribution of the OVF interrupt service routine to the overall CPU load, the calculations necessary for computing the three sinusoidal varying duty cycles are carried out once per two PWM periods (that is once every two interrupts). This way, the number of traced points per sine wave period (NP) is given by:

2 * f

PWM

SINE

NP =

Since at least 18 samples per sine wave cycle must be traced to generate a sine wave with a Total Harmonic Distortion minor than 5%, (3.2) limits the maximum sine wave frequency to 434 Hz that is equivalent to about 26,000 rpm for an one poles pair motor.

PWM

seconds.

COUNTER

has been fixed equal to

(3.2)

3.1.3 Third harmonic modulation

Basically, to provide the voltage needed for the PMAC motor, the reference PWM signal could be a pure sine wave, but this kind of modulation has the drawback that it makes poor usage of the DC bus voltage.

Adding a third harmonic modulation to the reference sine wave, allows the phase-to-phase voltage amplitude to be increased without deteriorating current and phase-to-phase voltage THD (a 120-degree phase-shift on the fundamental corresponds to a 360-degree shift for the third harmonic). On this subject, the literature demonstrates that, if the third harmonic amplitude is equal to one sixth of the fundamental one, it is possible to increase the phaseto-phase voltage amplitude by 15% with respect to the pure sine wave approach.

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AN2281 Implementation on the ST7LITE35 microcontroller

3.2 Lite timer for measuring the rotor speed

3.2.1 Block diagram and functional description

The Lite timer (LT) can be used for general-purpose timing functions. It is based on two freerunning 8-bit upcounters and one 8-bit input capture register.

Figure 6 shows the Lite timer block diagram.

Figure 6. The Lite timer block diagram

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OSC

LTCNTR

8-bit TIMEBASE

COUNTER 2

LTCSR2

TB2IE

LTTB2

Interrupt request

TB2F

LTARR

8-bit AUTORELOAD

8-bit TIMEBASE

LTICR

LTIC

INPUT CAPTURE

After an MCU reset, counter 1 starts incrementing from 0 at a frequency of f overflow event occurs when the counter rolls over from F9h to 00h. If f

COUNTER 1

8-bit

LTIMER

LTCSR1

LTIMER

Timebase 1 or 2 ms (@ 8MHz f

)

OSC

TB1F TB1IETBICFICIE

LTTB1 INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

To 12-bit AT TImer

OSC/32

=8 MHz, then the

OSC

. An

time period between two counter overflow events is 1 ms. This period can be optionally doubled by setting the TB bit in the LTCSR1 register.

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is generated if the TB1IE bit is set.

The Counter 2 functions in a similar way to Counter 1 but, after an MCU reset, it increments starting from the value stored in the LTARR register instead of starting from 0.

As you can see in Figure 6, Counter 1 is associated with an 8-bit input capture register, used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin.

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Implementation on the ST7LITE35 microcontroller AN2281

When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of Counter 1. An interrupt is generated if the ICIE bit is set.

3.3 Lite timer configuration for measuring the Hall sensor period

As mentioned in the previous paragraph, the LTICR register can be used to latch Counter 1 every time an edge is detected on the LTIC pin. This characteristic of the Lite Timer, together with the possibility of generating an interrupt when the upcounter overflows (LTTB1 Interrupt), allows you to precisely measure the semi-period of the Hall sensor signal.

Based on Figure 7, it is possible to draw the following mathematical relationship:

= ((250-Capture 1)+Capture 2+250*(N-1))*

OSC

N>0

(3.3)

where t

represents the Hall sensor signal period, Capture 1 and Capture 2 indicate the

values of Counter 1 at the edges of the Hall sensor signal and N is the number of LTTB1 interrupt events between the two Hall sensor output transitions taken into account.

Figure 7. Hall sensor signal semi-period measuring (N>0)

LTT B 1 I n t

LTTB1 Int LTTB1 Int

249

Counter 1

Capture 1

Capture 2

LTIC Int

Hall sensor

output

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AN2281 Implementation on the ST7LITE35 microcontroller

The relationship (3.3) is valid only under the condition N>0 and, then it can not be used to measure frequencies higher than 500Hz. In this case the formula to be used, as can be deduced from Figure 8, is the (3.4):

Figure 8. Hall sensor signal semi-period measuring (N=0)

LTT B 1 I n t

LTTB1 Int

249

Capture 2

Counter 1

Capture 1

LTIC Int

Hall sensor

output

= (Capture 2-Capture 1)*

OSC

Please note that in both (3.3) and (3.4) t

OSC

that is 4µsec at 8 MHz f

OSC

LTIC Int

(3.4)

/2 is computed with a resolution equal to:

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Implementation on the ST7LITE35 microcontroller AN2281

You can observe that, in order to measure the Hall sensor semi-period correctly, the LTIC and LTTB1 ISRs must be executed by the microcontroller core in the same order in which the related interrupts events occurred. This would normally happen if no other interrupts service routines are executing. However in our software, a third interrupt source is enabled (PWM update event), so a potentially erroneous situation could arise due to the interrupt priority mechanism.

Figure 9 describes two possible situations:

Figure 9. Multiple interrupt pending situation

249

Counter 1

LTTB1

Captured value << 125

LTIC Int

249

Counter 1

LTTB1

Captured value >> 125

LTIC Int

Hall sensor

output

PWM OVF ISR execution

Due to the higher interrupt priority of LTIC with respect to LTTB1, in both cases the LTIC ISR is executed before LTTB1 ISR.

In this case, the value stored in the LTICR is used to reconstruct the correct sequence: if the content of the LTICR is lower than 125, it is assumed that the LTTB1 event occurred just before a LTIC event so that the Lite Timer overflow counter must be incremented before the semi-period computation. On the contrary, if the LTICR contains a value higher than 125, it is assumed that the LTIC occurred just before a Lite timer overflow (LTTB1 event). In this case, the overflow counter must not be incremented before the semi-period computation but it will be taken into account at the next LTIC event.

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