ST AN2267 Application note

AN2267
Application note
Implementation of current regulator for BLDC
motor control with ST7FMC
Introduction
A conventional method of controlling BLDC motors is to implement an inner current loop for torque / current control. Reference to this inner loop is provided either by an outer speed loop or by some other means based on application requirement. The linearity of inner current / torque loop is greatly affected by the faithfulness of current feedback. In the first section, an outline to various approaches for obtaining current feedback is presented and analyzed with the limitations of each. In the subsequent sections, a presentation is given of a simple, linear and cost effective approach of implementing the inner current loop by sampling the DC link current at the mid-point of PWM “on time” with ST7FMC. Experimental results are also discussed.
An accompanying software file is available with this application note and can be downloaded from www.st.com/mcu
June 2006 Rev 1 1/19
www.st.com
Contents AN2267
Contents
1 Outline to various approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Obtaining the average current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 BLDC motor control using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Implementation using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Appendix A Sampling inner current loop procedure . . . . . . . . . . . . . . . . . . . . . 14
Appendix B Event U interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Appendix C ST7MC 3-phase motor control schematics . . . . . . . . . . . . . . . . . . . 16
2/19
AN2267 Outline to various approaches

1 Outline to various approaches

A BLDC motor driven in a conventional 6-step method greatly resembles a brushed DC motor. Hence, one may choose to regulate the average DC link current. But this actually results in constant power operation for the motor because at constant DC link voltage, if the average link current is regulated at a certain value, it effectively regulates the power at that point for any variation in motor load, and the average load current / motor torque varies inversely with speed depending on the load. Any effort to compensate the average DC link current data with the duty cycle to obtain average phase current will be impaired by a filter time constant, rendering this option ineffective.
Since the DC link current does not reveal winding currents during PWM “off time”, one may choose to monitor all 3 winding currents and build a regulator. But this requires two current sensors to monitor any two phase currents, while the third phase current can be reconstructed from these two. However, the cost of these sensors makes this option expensive.
A third option would then be to regulate the peak current per PWM period. Though it is inexpensive and easy to implement, it is not exactly linear. During PWM on time, at lower duty cycles, when both speed and BEMF are small, the phase current rises much faster than at higher duty cycles when the speed and BEMF are large. The same peak currents per PWM period represent different average currents at different duty cycles. An intuitive geometric approach will reveal this as shown in Figure 1. A typical variation in average current vs duty cycle at a given peak current reference is shown in Figure 2.
Figure 1. Peak current regulation at different duty cycles with BEMF load
I
phase
I
peak
I
phase
I
peak
tt
Figure 2. I
vs duty cycle at a given I
ave
I
ave
I
peak
peak
dutycycle
00.51.0
3/19
Obtaining the average current AN2267

2 Obtaining the average current

For linear torque control, it is important that we sample the average phase current as feedback to the current regulator. It is best to get this information from the DC link current using only a shunt resistor because of its low cost and simplicity. However, the DC link current is not continuous and is present only during PWM on time. As a simple model for current control, assume a simple buck converter feeding an RL load as shown in Figure 3.
Figure 3. Buck converter feeding an RL load
PWM CONTROL
SW1
1
BT1
2
R1
D1
V
L
R
sh
I
sh
I
L
L1
The switching frequency, PWM on time and load inductance are such that the load current is continuous. Figure 4 shows the load voltage, load current and DC link current waveforms. A close look at the load current waveform reveals that its average value is equal to its instantaneous value during the middle of PWM on time or off time. Since the load current flows through the DC link during PWM on time, sampling the DC link current during the middle of PWM on time gives the average load current.
Figure 4. Buck Converter - Waveforms
V
I
L
I
L(ave
I
S
4/19
T
o
T
off
AN2267 BLDC motor control using ST7FMC
(
g
C
g
d

3 BLDC motor control using ST7FMC

The main feature of ST7FMC is its powerful motor control macro cell, capable of generating control signals to drive a sensorless or sensored 3 phase BLDC or AC motor. STMicroelectronics application notes AN1946 [1] and AN2030 [2] explain, in detail, the procedure to control a 3 phase BLDC motor using ST7FMC.
Figure 5 shows the simplified block diagram of the hardware motor control macro cell. The
macrocell has multiple timers performing various functions in parallel to generate control pulses for the motor. An auto scalable 8-bit timer (MTIM) monitors the time difference between successive phase back EMF zero crossings (Z events) of the motor. When a Z event occurs, the timer value is captured into MZREG and the timer restarts counting from zero, and, the previous content of MZREG is transferred to MZPRV. This timer is a part of what is called DELAY MANAGER that, based on this time difference and a delay coefficient (MWGHT), identifies the timing for next phase commutation instant (C events). All in parallel, a 12-bit free running counter generates the PWM carrier for inverter switching.
Figure 5. Simplified block diagram of Motor control Macro cell for BLDC motors
or SPEED MEASURE UNIT (not
WEIGH
DELAY = WEIGHT x
MEASUREMENT
WINDOW
GENERATOR
PWM
12-bit
Phase
Phase V
Phase W
[Z] : Back EMF Zero-crossin
: Time elapsed between two consecutive Z
Z
n
[C] : Commutation
: Time delayed after Z event to generate C
n
(I): Current
e
(V): Volta
DELAY
(I
CAPTURE
(V
Phase
CURRENT
VOLTAGE
MOD
(V
MTI
TIME
=
COMMUTE
PCN
BEMF ZERO-CROSSING
BEMF=
[Z
TACH
Encoder
INPUT DETECTION
P H A
U, V, Phase
CFAV
CHANNEL
12-bit THREE-PHASE
PWM GENERATOR
Vre
OAON
MCI MCI MCI
Ex
In
+
-
AD
MCO MCO MCO MCO MCO MCO
NMCE
MCAO
MCAO
MCCRE
C
MCPWM
MCPWM
MCPWM
MCVRE
MCAOZ/ MCCFI
(V
Vd
I
R
3
5/19
BLDC motor control using ST7FMC AN2267
Figure 6. Motor Control Macro cell - BLDC motor control configuration
HV
C
C
ext
Board + Motor
MCPWMU / V/ W
V
DD
(I)
R
(V)
R
1ext
2ext
Microcontroll er
Z
H
D
H
Fcpu
+1
ST3-0 bits
-1
Z
H
MZREG Reg [ Zn]
Z
S,H
MZP RV Reg [Z
DCB bit
MWGHT R eg [a
SWA bi t
MCOMP Reg [C
EF[2: 0]
Filte r / D
SR bit
X T16 bi t
+
R
MTIM
= FFh?
MZREG
< 55h?
-
R
MTIM [8-bit Up Counter]
]
n-1
]
n+1
A x B / 256
n+1
+
-
S,H
D
S,H
D
V
REF
VR2- 0
SR b it
S,H
Filt er / PWM
Reg
MPHST
CFF[2:0] bit
ISn bit
12- bit P WM ge nera tor
n
bits
OS
MREF
3
n
6 6
Reg
Ch0Ch1Ch2Ch3Ch4
Dead
Time
Dead
Time
High Frequency Chopper
Dead
Time
Ch5
8
2
6
PCN bi t =0
DTG register
MPAR Reg
+
CL
-
x6 x6
AO bit
+
-
CFA V bi t
MCIA
MCIB
MCIC
MCVREF
MPWME Reg
MCPWMU
MCPWMV
MCPWMW
MCO0
MCO2
MCO4
MCO1
MCO3
MCO5
1
NM CE S
MOE bi t
MPOL Reg
MCAOP
MCAON
MCAOZ
MCCFI
MCCREF
B
A
A
CP Bn bit
1 / 2
1 / 2
nn-1
88
Compare
EF[2:0] Filter / C
Rat i o
ck
C
HDMn bit
1 / 4
8
Compare
S,H
ororor
SA3- 0 &
OT1-0 bits
SZn
bit
Z
S
PZ bit
1 ¾ 1/128
Filter / C
EF[2 :0]
or
CP Bn bit
1 /20
REO bi t
cl r
D
S,H
C
2
1
SPLG
SWA bi t
1
0
D
H
MDREG Reg [ Dn]
Com p a re
SDMn bit
EF[2:0 ]
F ilter / C
CL
-/+
R
E
Z
S,H
D
S,H
C
S,H
S,H
DQ
CP
C
2
1
V
I
Com p ar e U
Z
V
I
C
H
SQ
R
D
S
MISR R eg
MI MR Reg
ZVD bit
4
8
]
A PWM output is generated as a result of comparison between this carrier and a compare register (MCPUH:MCPUL) that carries pulse width (duty cycle) information. This PWM signal is directed to one of the six inverter switches by a CHANNEL MANAGER that acts as a traffic diverter on the PWM output. The channel manager also selects a complementary switch, as programmed by the user, which together with the switch receiving PWM will force current into the motor windings. Based on the motor terminal voltages or Hall sensor outputs, an analog block identifies the motor phase BEMF Z events and captures the contents of MTIM timer into MZREG and the previous value of MZREG into MZPRV and this cycle repeats all over again.
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