ST AN2267 Application note

AN2267

Application note

Implementation of current regulator for BLDC motor control with ST7FMC

Introduction

A conventional method of controlling BLDC motors is to implement an inner current loop for torque / current control. Reference to this inner loop is provided either by an outer speed loop or by some other means based on application requirement. The linearity of inner current / torque loop is greatly affected by the faithfulness of current feedback. In the first section, an outline to various approaches for obtaining current feedback is presented and analyzed with the limitations of each. In the subsequent sections, a presentation is given of a simple, linear and cost effective approach of implementing the inner current loop by sampling the DC link current at the mid-point of PWM “on time” with ST7FMC. Experimental results are also discussed.

An accompanying software file is available with this application note and can be downloaded from www.st.com/mcu

June 2006

Rev 1

1/19

www.st.com

Contents	AN2267

Contents

1	Outline to various approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 3
2	Obtaining the average current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
3	BLDC motor control using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
4	Implementation using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
5	Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
6	Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
7	References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Appendix A Sampling inner current loop procedure . . . . . . . . . . . . . . . . . . . . .		14
Appendix B Event U interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
Appendix C ST7MC 3-phase motor control schematics . . . . . . . . . . . . . . . . . . .		16

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AN2267	Outline to various approaches

1 Outline to various approaches

A BLDC motor driven in a conventional 6-step method greatly resembles a brushed DC motor. Hence, one may choose to regulate the average DC link current. But this actually results in constant power operation for the motor because at constant DC link voltage, if the average link current is regulated at a certain value, it effectively regulates the power at that point for any variation in motor load, and the average load current / motor torque varies inversely with speed depending on the load. Any effort to compensate the average DC link current data with the duty cycle to obtain average phase current will be impaired by a filter time constant, rendering this option ineffective.

Since the DC link current does not reveal winding currents during PWM “off time”, one may choose to monitor all 3 winding currents and build a regulator. But this requires two current sensors to monitor any two phase currents, while the third phase current can be reconstructed from these two. However, the cost of these sensors makes this option expensive.

A third option would then be to regulate the peak current per PWM period. Though it is inexpensive and easy to implement, it is not exactly linear. During PWM on time, at lower duty cycles, when both speed and BEMF are small, the phase current rises much faster than at higher duty cycles when the speed and BEMF are large. The same peak currents per PWM period represent different average currents at different duty cycles. An intuitive geometric approach will reveal this as shown in Figure 1. A typical variation in average current vs duty cycle at a given peak current reference is shown in Figure 2.

Figure 1.	Peak current regulation at different duty cycles with BEMF load
I	Iphase
phase

Ipeak

t

Ipeak

t

Figure 2. Iave vs duty cycle at a given Ipeak

Iave

Ipeak
		dutycycle
0	0.5	1.0

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Obtaining the average current	AN2267

2 Obtaining the average current

For linear torque control, it is important that we sample the average phase current as feedback to the current regulator. It is best to get this information from the DC link current using only a shunt resistor because of its low cost and simplicity. However, the DC link current is not continuous and is present only during PWM on time. As a simple model for current control, assume a simple buck converter feeding an RL load as shown in Figure 3.

Figure 3. Buck converter feeding an RL load

PWM

CONTROL

SW1

1 2

R1

BT1

D1

VL

L1

Rsh

					Ish	IL

The switching frequency, PWM on time and load inductance are such that the load current is continuous. Figure 4 shows the load voltage, load current and DC link current waveforms. A close look at the load current waveform reveals that its average value is equal to its instantaneous value during the middle of PWM on time or off time. Since the load current flows through the DC link during PWM on time, sampling the DC link current during the middle of PWM on time gives the average load current.

Figure 4. Buck Converter - Waveforms

V

IL

IL(ave

IS

To Toff

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AN2267	BLDC motor control using ST7FMC

3 BLDC motor control using ST7FMC

The main feature of ST7FMC is its powerful motor control macro cell, capable of generating control signals to drive a sensorless or sensored 3 phase BLDC or AC motor. STMicroelectronics application notes AN1946 [1] and AN2030 [2] explain, in detail, the procedure to control a 3 phase BLDC motor using ST7FMC.

Figure 5 shows the simplified block diagram of the hardware motor control macro cell. The macrocell has multiple timers performing various functions in parallel to generate control pulses for the motor. An auto scalable 8-bit timer (MTIM) monitors the time difference between successive phase back EMF zero crossings (Z events) of the motor. When a Z event occurs, the timer value is captured into MZREG and the timer restarts counting from zero, and, the previous content of MZREG is transferred to MZPRV. This timer is a part of what is called DELAY MANAGER that, based on this time difference and a delay coefficient (MWGHT), identifies the timing for next phase commutation instant (C events). All in parallel, a 12-bit free running counter generates the PWM carrier for inverter switching.

Figure 5. Simplified block diagram of Motor control Macro cell for BLDC motors

DELAY

BEMF ZERO-CROSSING

	or SPEED MEASURE UNIT (not	BEMF=	MCI
		[Z	MCI
			MCI
WEIGH	CAPTURE	MTI
		TIME
			Ex
		In
			MCVRE

DELAY = WEIGHT x	=	TACH	Vre
			Encoder
	COMMUTE		INPUT DETECTION

					MCO
MEASUREMENT		CURRENT	P		MCO
WINDOW			H		MCO
GENERATOR
			A		MCO
		VOLTAGE
			S		MCO
	(I
		(V			MCO
		MOD	U, V,	OAON	NMCE
			Phase	+
					MCAO
PWM				CFAV	MCAO
				-
					MCAOZ/
					MCCFI
						Vdd
		Phase		AD	MCCRE
						(V
				CHANNEL	C	(I
12-bit		(V	PCN	12-bit THREE-PHASE		R 3
				PWM GENERATOR

Phase			MCPWM
			MCPWM
Phase V
Phase W			MCPWM

[Z] : Back EMF Zero-crossing

Z n : Time elapsed between two consecutive Z [C] : Commutation

C n : Time delayed after Z event to generate C (I): Current

(V): Voltage

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BLDC motor control using ST7FMC	AN2267

Figure 6. Motor Control Macro cell - BLDC motor control configuration

Microcontroller

EF[2 : 0]

Z VD b it CPB

bit PZ b it

REO bit

DS,H

Filte r / D

n

CS,H

ZH

or or

or

2

E F[2 :0 ]

Q D

Filt e r / C

SR bit

1

or

CP

DH

SPLG

2

HDM n bit

CPBn bit

XT16 bi t

1

Fcpu

1 / 4

R+

I

+1

MTIM

1 /2

1 /20

= FFh?

4

ST3-0 bits

1 / 2Ratio

1 ¾ 1/128

-1

MZREG

SA3-0 &

< 55h?

SWA bit

R-

ck

OT1-0 bits

Z

1

clr

CH

I

MTIM[8-bit Up Counter]

8

0

ZH

MZREG Reg [Zn]

DH

MDREG Reg [D ]

ZS,H

n

MZPRV Reg [Zn1- ]

Compare

Compare

SZn

DCB bit

n-1

n

bit

SDM

bit

n

MWGHT Reg [an+1 ]

EF[2:0]

Filter / C

EF[2:0]

Filter / C

8

8

A x B/ 256

DS

Z S

SWA bit

8

MCOMP Reg [Cn+1]

CL

Compare

R-/+

Reg

Reg

CS,H

E

MISR

MIMR

ZS,H

DS,H

CS,H

ISnbit

+

-

CS,HVREF

	DS,H
		VR2-0
V
			12bit PWM ge nera tor
UCompare	SR bit		OS n bits			MREF	Reg
			3
V			Ch0		Dead Dead
S Q		MPHSTReg n	Ch3Ch2 Ch1			Time Time	FrequencyChopper
R			Ch5		Dead	Time	High
			Ch4
	DS,H				8
			6	DTGregister		2	AObit
			MPARReg			PCNbit=0
							6
		CFF[2:0]bit
			CL			+
	Filter / PWM					-

		Board + Motor
	MCIA
	MCIB
	MCIC
	MCVREF
MPWME Reg
	MCPWMU
	MCPWMV
	MCPWMW
		HV
	MCO0
x6	MCO2
	x6
	MCO4
		B
	A
	MCO1	C
	MCO3
	MCO5
6	1
MPOLReg	MOEbit
	NMCES
		MCPWMU/V/W

+MCAOP

-MCAON

	MCAOZ		VDD
	MCCFI	A	(I) R
			1ext
CFAV bit	MCCREF
		(V)	R
		Cext	2ext

A PWM output is generated as a result of comparison between this carrier and a compare register (MCPUH:MCPUL) that carries pulse width (duty cycle) information. This PWM signal is directed to one of the six inverter switches by a CHANNEL MANAGER that acts as a traffic diverter on the PWM output. The channel manager also selects a complementary switch, as programmed by the user, which together with the switch receiving PWM will force current into the motor windings. Based on the motor terminal voltages or Hall sensor outputs, an analog block identifies the motor phase BEMF Z events and captures the contents of MTIM timer into MZREG and the previous value of MZREG into MZPRV and this cycle repeats all over again.

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